1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * UART Constants File: sb1250_uart.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the SB1250's UARTs 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions as 27 * they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. Neither the "Broadcom 31 * Corporation" name nor any trademark or logo of Broadcom 32 * Corporation may be used to endorse or promote products 33 * derived from this software without the prior written 34 * permission of Broadcom Corporation. 35 * 36 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 37 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 38 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 39 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 40 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 41 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 42 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 43 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 44 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 45 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 46 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 47 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 48 * THE POSSIBILITY OF SUCH DAMAGE. 49 ********************************************************************* */ 50 51 52 #ifndef _SB1250_UART_H 53 #define _SB1250_UART_H 54 55 #include "sb1250_defs.h" 56 57 /* ********************************************************************** 58 * DUART Registers 59 ********************************************************************** */ 60 61 /* 62 * DUART Mode Register #1 (Table 10-3) 63 * Register: DUART_MODE_REG_1_A 64 * Register: DUART_MODE_REG_1_B 65 */ 66 67 #define S_DUART_BITS_PER_CHAR 0 68 #define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR) 69 #define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR) 70 71 #define K_DUART_BITS_PER_CHAR_RSV0 0 72 #define K_DUART_BITS_PER_CHAR_RSV1 1 73 #define K_DUART_BITS_PER_CHAR_7 2 74 #define K_DUART_BITS_PER_CHAR_8 3 75 76 #define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0) 77 #define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1) 78 #define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7) 79 #define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8) 80 81 82 #define M_DUART_PARITY_TYPE_EVEN 0x00 83 #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) 84 85 #define S_DUART_PARITY_MODE 3 86 #define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE) 87 #define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE) 88 89 #define K_DUART_PARITY_MODE_ADD 0 90 #define K_DUART_PARITY_MODE_ADD_FIXED 1 91 #define K_DUART_PARITY_MODE_NONE 2 92 93 #define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD) 94 #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) 95 #define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) 96 97 #define M_DUART_ERR_MODE _SB_MAKEMASK1(5) /* must be zero */ 98 99 #define M_DUART_RX_IRQ_SEL_RXRDY 0 100 #define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) 101 102 #define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7) 103 104 /* 105 * DUART Mode Register #2 (Table 10-4) 106 * Register: DUART_MODE_REG_2_A 107 * Register: DUART_MODE_REG_2_B 108 */ 109 110 #define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */ 111 112 #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) 113 #define M_DUART_STOP_BIT_LEN_1 0 114 115 #define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4) 116 117 118 #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ 119 120 #define S_DUART_CHAN_MODE 6 121 #define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE) 122 #define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE) 123 124 #define K_DUART_CHAN_MODE_NORMAL 0 125 #define K_DUART_CHAN_MODE_LCL_LOOP 2 126 #define K_DUART_CHAN_MODE_REM_LOOP 3 127 128 #define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL) 129 #define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP) 130 #define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP) 131 132 /* 133 * DUART Command Register (Table 10-5) 134 * Register: DUART_CMD_A 135 * Register: DUART_CMD_B 136 */ 137 138 #define M_DUART_RX_EN _SB_MAKEMASK1(0) 139 #define M_DUART_RX_DIS _SB_MAKEMASK1(1) 140 #define M_DUART_TX_EN _SB_MAKEMASK1(2) 141 #define M_DUART_TX_DIS _SB_MAKEMASK1(3) 142 143 #define S_DUART_MISC_CMD 4 144 #define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD) 145 #define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD) 146 147 #define K_DUART_MISC_CMD_NOACTION0 0 148 #define K_DUART_MISC_CMD_NOACTION1 1 149 #define K_DUART_MISC_CMD_RESET_RX 2 150 #define K_DUART_MISC_CMD_RESET_TX 3 151 #define K_DUART_MISC_CMD_NOACTION4 4 152 #define K_DUART_MISC_CMD_RESET_BREAK_INT 5 153 #define K_DUART_MISC_CMD_START_BREAK 6 154 #define K_DUART_MISC_CMD_STOP_BREAK 7 155 156 #define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0) 157 #define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1) 158 #define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX) 159 #define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX) 160 #define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4) 161 #define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT) 162 #define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) 163 #define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) 164 165 #define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) 166 167 /* 168 * DUART Status Register (Table 10-6) 169 * Register: DUART_STATUS_A 170 * Register: DUART_STATUS_B 171 * READ-ONLY 172 */ 173 174 #define M_DUART_RX_RDY _SB_MAKEMASK1(0) 175 #define M_DUART_RX_FFUL _SB_MAKEMASK1(1) 176 #define M_DUART_TX_RDY _SB_MAKEMASK1(2) 177 #define M_DUART_TX_EMT _SB_MAKEMASK1(3) 178 #define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4) 179 #define M_DUART_PARITY_ERR _SB_MAKEMASK1(5) 180 #define M_DUART_FRM_ERR _SB_MAKEMASK1(6) 181 #define M_DUART_RCVD_BRK _SB_MAKEMASK1(7) 182 183 /* 184 * DUART Baud Rate Register (Table 10-7) 185 * Register: DUART_CLK_SEL_A 186 * Register: DUART_CLK_SEL_B 187 */ 188 189 #define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0) 190 #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) 191 192 /* 193 * DUART Data Registers (Table 10-8 and 10-9) 194 * Register: DUART_RX_HOLD_A 195 * Register: DUART_RX_HOLD_B 196 * Register: DUART_TX_HOLD_A 197 * Register: DUART_TX_HOLD_B 198 */ 199 200 #define M_DUART_RX_DATA _SB_MAKEMASK(8,0) 201 #define M_DUART_TX_DATA _SB_MAKEMASK(8,0) 202 203 /* 204 * DUART Input Port Register (Table 10-10) 205 * Register: DUART_IN_PORT 206 */ 207 208 #define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0) 209 #define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1) 210 #define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2) 211 #define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3) 212 #define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4) 213 #define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5) 214 #define M_DUART_RIN0_PIN _SB_MAKEMASK1(6) 215 #define M_DUART_RIN1_PIN _SB_MAKEMASK1(7) 216 217 /* 218 * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13) 219 * Register: DUART_INPORT_CHNG 220 */ 221 222 #define S_DUART_IN_PIN_VAL 0 223 #define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL) 224 225 #define S_DUART_IN_PIN_CHNG 4 226 #define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG) 227 228 229 /* 230 * DUART Output port control register (Table 10-14) 231 * Register: DUART_OPCR 232 */ 233 234 #define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */ 235 #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) 236 #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ 237 #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) 238 #define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */ 239 240 /* 241 * DUART Aux Control Register (Table 10-15) 242 * Register: DUART_AUX_CTRL 243 */ 244 245 #define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0) 246 #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) 247 #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) 248 #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) 249 #define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4) 250 251 #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) 252 #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) 253 254 /* 255 * DUART Interrupt Status Register (Table 10-16) 256 * Register: DUART_ISR 257 */ 258 259 #define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) 260 #define M_DUART_ISR_RX_A _SB_MAKEMASK1(1) 261 #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) 262 #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) 263 #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) 264 #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) 265 #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) 266 #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) 267 268 /* 269 * DUART Channel A Interrupt Status Register (Table 10-17) 270 * DUART Channel B Interrupt Status Register (Table 10-18) 271 * Register: DUART_ISR_A 272 * Register: DUART_ISR_B 273 */ 274 275 #define M_DUART_ISR_TX _SB_MAKEMASK1(0) 276 #define M_DUART_ISR_RX _SB_MAKEMASK1(1) 277 #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) 278 #define M_DUART_ISR_IN _SB_MAKEMASK1(3) 279 #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) 280 281 /* 282 * DUART Interrupt Mask Register (Table 10-19) 283 * Register: DUART_IMR 284 */ 285 286 #define M_DUART_IMR_TX_A _SB_MAKEMASK1(0) 287 #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) 288 #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) 289 #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) 290 #define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0) 291 292 #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) 293 #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) 294 #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) 295 #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) 296 #define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4) 297 298 /* 299 * DUART Channel A Interrupt Mask Register (Table 10-20) 300 * DUART Channel B Interrupt Mask Register (Table 10-21) 301 * Register: DUART_IMR_A 302 * Register: DUART_IMR_B 303 */ 304 305 #define M_DUART_IMR_TX _SB_MAKEMASK1(0) 306 #define M_DUART_IMR_RX _SB_MAKEMASK1(1) 307 #define M_DUART_IMR_BRK _SB_MAKEMASK1(2) 308 #define M_DUART_IMR_IN _SB_MAKEMASK1(3) 309 #define M_DUART_IMR_ALL _SB_MAKEMASK(4,0) 310 #define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4) 311 312 313 /* 314 * DUART Output Port Set Register (Table 10-22) 315 * Register: DUART_SET_OPR 316 */ 317 318 #define M_DUART_SET_OPR0 _SB_MAKEMASK1(0) 319 #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) 320 #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) 321 #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) 322 #define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4) 323 324 /* 325 * DUART Output Port Clear Register (Table 10-23) 326 * Register: DUART_CLEAR_OPR 327 */ 328 329 #define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0) 330 #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) 331 #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) 332 #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) 333 #define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4) 334 335 /* 336 * DUART Output Port RTS Register (Table 10-24) 337 * Register: DUART_OUT_PORT 338 */ 339 340 #define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0) 341 #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) 342 #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) 343 #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) 344 #define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4) 345 346 #define M_DUART_OUT_PIN_SET(chan) \ 347 (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) 348 #define M_DUART_OUT_PIN_CLR(chan) \ 349 (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) 350 351 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 352 /* 353 * Full Interrupt Control Register 354 */ 355 356 #define S_DUART_SIG_FULL _SB_MAKE64(0) 357 #define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL) 358 #define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL) 359 #define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL) 360 361 #define S_DUART_INT_TIME _SB_MAKE64(4) 362 #define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) 363 #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) 364 #define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) 365 #endif /* 1250 PASS2 || 112x PASS1 */ 366 367 368 /* ********************************************************************** */ 369 370 371 #endif 372