1 /* $NetBSD: mips_3x30.c,v 1.12 2009/03/14 21:04:12 dsl Exp $ */ 2 3 /* 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: mips_3x30.c,v 1.12 2009/03/14 21:04:12 dsl Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/proc.h> 39 #include <sys/kernel.h> 40 41 #include <machine/trap.h> 42 #include <machine/psl.h> 43 #include <machine/cpu.h> 44 #include <machine/intr.h> 45 #include <machine/mainboard.h> 46 #include <machine/sysconf.h> 47 48 extern void MachFPInterrupt (u_int, u_int, u_int, struct frame *); 49 50 /* Local functions */ 51 void pizazz_init (void); 52 void pizazz_intr (u_int, u_int, u_int, u_int); 53 int pizazz_level0_intr (void *); 54 void pizazz_level5_intr (int, int, int); 55 void pizazz_intr_establish (int, int (*)(void *), void *); 56 57 #define INT_MASK_FPU MIPS_INT_MASK_3 58 59 void 60 pizazz_init(void) 61 { 62 platform.iobus = "obio"; 63 platform.cons_init = NULL; 64 platform.iointr = pizazz_intr; 65 platform.intr_establish = pizazz_intr_establish; 66 67 pizazz_intr_establish(SYS_INTR_LEVEL0, pizazz_level0_intr, NULL); 68 69 strcpy(cpu_model, "Mips 3230 Magnum (Pizazz)"); 70 cpuspeed = 25; 71 } 72 73 #define HANDLE_INTR(intr, mask) \ 74 do { \ 75 if (ipending & (mask)) { \ 76 CALL_INTR(intr); \ 77 } \ 78 } while (0) 79 80 void 81 pizazz_intr(u_int status, u_int cause, u_int pc, u_int ipending) 82 /* status: status register at time of the exception */ 83 /* cause: cause register at time of exception */ 84 /* pc: program counter where to continue */ 85 { 86 /* handle clock interrupts ASAP */ 87 if (ipending & MIPS_INT_MASK_2) { /* Timer Interrupt */ 88 void rambo_clkintr (struct clockframe *); 89 struct clockframe cf; 90 91 cf.pc = pc; 92 cf.sr = status; 93 94 rambo_clkintr(&cf); 95 96 /* keep clock interrupts enabled when we return */ 97 cause &= ~MIPS_INT_MASK_2; 98 } 99 100 /* If clock interrupts were enabled, re-enable them ASAP. */ 101 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_2)); 102 103 if (ipending & MIPS_INT_MASK_5) /* level 5 interrupt */ 104 pizazz_level5_intr(pc, cause, status); 105 106 HANDLE_INTR(SYS_INTR_FDC, MIPS_INT_MASK_4); 107 HANDLE_INTR(SYS_INTR_SCSI, MIPS_INT_MASK_1); 108 HANDLE_INTR(SYS_INTR_LEVEL0, MIPS_INT_MASK_0); 109 110 /* XXX: Keep FDC interrupt masked off */ 111 cause &= ~(MIPS_INT_MASK_0 | MIPS_INT_MASK_1 | MIPS_INT_MASK_5); 112 113 _splset((status & ~cause & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE); 114 115 /* FPU nofiticaition */ 116 if (ipending & INT_MASK_FPU) { 117 if (!USERMODE(status)) 118 panic("kernel used FPU: PC %x, CR %x, SR %x", 119 pc, cause, status); 120 #if !defined(SOFTFLOAT) 121 MachFPInterrupt(status, cause, pc, curlwp->l_md.md_regs); 122 #endif 123 } 124 } 125 126 /* 127 * Level 0 interrupt handler 128 * 129 * Pizazz shares Lance, SCC, Expansion slot and Keyboard on level 0 130 * A secondary interrupt status register shows the real interrupt source 131 */ 132 int 133 pizazz_level0_intr(void *arg) 134 { 135 register int stat; 136 137 /* stat register is active low */ 138 stat = ~*(volatile u_char *)INTREG_0; 139 140 if (stat & INT_ExpSlot) 141 CALL_INTR(SYS_INTR_ATBUS); 142 143 if (stat & INT_Lance) 144 CALL_INTR(SYS_INTR_ETHER); 145 146 if (stat & INT_SCC) 147 CALL_INTR(SYS_INTR_SCC0); 148 149 return 0; 150 } 151 152 /* 153 * Motherboard Parity Error 154 */ 155 void 156 pizazz_level5_intr(int pc, int cause, int status) 157 { 158 u_int32_t ereg; 159 160 ereg = *(u_int32_t *)RAMBO_ERREG; 161 162 printf("interrupt: pc=%p cr=%x sr=%x\n", (void *)pc, cause, status); 163 printf("parity error: %p mask: 0x%x\n", (void *)ereg, ereg & 0xf); 164 panic("memory fault"); 165 } 166 167 void 168 pizazz_intr_establish(level, func, arg) 169 int level; 170 int (*func) (void *); 171 void *arg; 172 { 173 if (level < 0 || level >= MAX_INTR_COOKIES) 174 panic("invalid interrupt level"); 175 176 if (intrtab[level].ih_fun != NULL) 177 panic("cannot share interrupt %d", level); 178 179 intrtab[level].ih_fun = func; 180 intrtab[level].ih_arg = arg; 181 } 182