1 /* $NetBSD: zs.c,v 1.14 2002/10/02 05:38:11 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross and Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include "opt_ddb.h" 47 #include "opt_kgdb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/device.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/syslog.h> 60 61 #include <machine/cpu.h> 62 #include <machine/mainboard.h> 63 #include <machine/autoconf.h> 64 #include <machine/prom.h> 65 #include <machine/z8530var.h> 66 67 #include <dev/cons.h> 68 #include <dev/ic/z8530reg.h> 69 70 #include "zsc.h" /* NZSC */ 71 #define NZS NZSC 72 73 /* Make life easier for the initialized arrays here. */ 74 #if NZS < 2 75 #undef NZS 76 #define NZS 2 77 #endif 78 79 /* 80 * Some warts needed by z8530tty.c - 81 * The default parity REALLY needs to be the same as the PROM uses, 82 * or you can not see messages done with printf during boot-up... 83 */ 84 int zs_def_cflag = (CREAD | CS8 | HUPCL); 85 86 87 #define PCLK 10000000 /* PCLK pin input clock rate */ 88 89 #ifndef ZS_DEFSPEED 90 #define ZS_DEFSPEED 9600 91 #endif 92 93 /* 94 * Define interrupt levels. 95 */ 96 #define ZSHARD_PRI 64 97 98 /* Register recovery time is 3.5 to 4 PCLK Cycles */ 99 #define ZS_RECOVERY 1 /* 1us = 10 PCLK Cycles */ 100 #define ZS_DELAY() delay(ZS_RECOVERY) 101 102 /* The layout of this is hardware-dependent (padding, order). */ 103 struct zschan { 104 u_char pad1[3]; 105 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 106 u_char pad2[3]; 107 volatile u_char zc_data; /* data */ 108 }; 109 struct zsdevice { 110 /* Yes, they are backwards. */ 111 struct zschan zs_chan_b; 112 struct zschan zs_chan_a; 113 }; 114 115 /* Return the byte offset of element within a structure */ 116 #define OFFSET(struct_def, el) ((size_t)&((struct_def *)0)->el) 117 118 #define ZS_CHAN_A OFFSET(struct zsdevice, zs_chan_a) 119 #define ZS_CHAN_B OFFSET(struct zsdevice, zs_chan_b) 120 #define ZS_REG_CSR OFFSET(struct zschan, zc_csr) 121 #define ZS_REG_DATA OFFSET(struct zschan, zc_data) 122 static int zs_chan_offset[] = {ZS_CHAN_A, ZS_CHAN_B}; 123 124 /* Flags from cninit() */ 125 static int zs_hwflags[NZS][2]; 126 127 /* Default speed for all channels */ 128 static int zs_defspeed = ZS_DEFSPEED; 129 static volatile int zssoftpending; 130 131 static u_char zs_init_reg[16] = { 132 0, /* 0: CMD (reset, etc.) */ 133 0, /* 1: No interrupts yet. */ 134 ZSHARD_PRI, /* 2: IVECT */ 135 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 136 ZSWR4_CLK_X16 | ZSWR4_ONESB, 137 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 138 0, /* 6: TXSYNC/SYNCLO */ 139 0, /* 7: RXSYNC/SYNCHI */ 140 0, /* 8: alias for data port */ 141 ZSWR9_MASTER_IE, 142 0, /*10: Misc. TX/RX control bits */ 143 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD | ZSWR11_TRXC_OUT_ENA, 144 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */ 145 0, /*13: BAUDHI (default=9600) */ 146 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 147 ZSWR15_BREAK_IE, 148 }; 149 150 151 /**************************************************************** 152 * Autoconfig 153 ****************************************************************/ 154 155 /* Definition of the driver for autoconfig. */ 156 static int zs_match __P((struct device *, struct cfdata *, void *)); 157 static void zs_attach __P((struct device *, struct device *, void *)); 158 static int zs_print __P((void *, const char *name)); 159 160 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 161 zs_match, zs_attach, NULL, NULL); 162 163 extern struct cfdriver zsc_cd; 164 165 static int zshard __P((void *)); 166 void zssoft __P((void *)); 167 static int zs_get_speed __P((struct zs_chanstate *)); 168 struct zschan *zs_get_chan_addr (int zs_unit, int channel); 169 int zs_getc __P((void *)); 170 void zs_putc __P((void *, int)); 171 172 /* 173 * Is the zs chip present? 174 */ 175 static int 176 zs_match(parent, cf, aux) 177 struct device *parent; 178 struct cfdata *cf; 179 void *aux; 180 { 181 struct confargs *ca = aux; 182 void *va; 183 184 if (strcmp(ca->ca_name, "zsc")) 185 return 0; 186 187 va = (void *)cf->cf_addr; 188 189 /* This returns -1 on a fault (bus error). */ 190 if (badaddr(va, 1)) 191 return 0; 192 return 1; 193 } 194 195 /* 196 * Attach a found zs. 197 * 198 * Match slave number to zs unit number, so that misconfiguration will 199 * not set up the keyboard as ttya, etc. 200 */ 201 static void 202 zs_attach(parent, self, aux) 203 struct device *parent; 204 struct device *self; 205 void *aux; 206 { 207 struct zsc_softc *zsc = (void *) self; 208 struct confargs *ca = aux; 209 struct zsc_attach_args zsc_args; 210 struct zs_chanstate *cs; 211 struct zs_channel *ch; 212 int zs_unit, channel, s; 213 214 zsc->zsc_bustag = ca->ca_bustag; 215 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 216 sizeof(struct zsdevice), 217 BUS_SPACE_MAP_LINEAR, 218 &zsc->zsc_base) != 0) { 219 printf(": cannot map registers\n"); 220 return; 221 } 222 223 zs_unit = zsc->zsc_dev.dv_unit; 224 printf("\n"); 225 226 /* 227 * Initialize software state for each channel. 228 */ 229 for (channel = 0; channel < 2; channel++) { 230 zsc_args.channel = channel; 231 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 232 ch = &zsc->zsc_cs_store[channel]; 233 cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch; 234 235 cs->cs_reg_csr = NULL; 236 cs->cs_reg_data = NULL; 237 cs->cs_channel = channel; 238 cs->cs_private = NULL; 239 cs->cs_ops = &zsops_null; 240 cs->cs_brg_clk = PCLK / 16; 241 242 if (bus_space_subregion(ca->ca_bustag, zsc->zsc_base, 243 zs_chan_offset[channel], 244 sizeof(struct zschan), 245 &ch->cs_regs) != 0) { 246 printf(": cannot map regs\n"); 247 return; 248 } 249 ch->cs_bustag = ca->ca_bustag; 250 251 memcpy(cs->cs_creg, zs_init_reg, 16); 252 memcpy(cs->cs_preg, zs_init_reg, 16); 253 254 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 255 cs->cs_defspeed = zs_get_speed(cs); 256 else 257 cs->cs_defspeed = zs_defspeed; 258 cs->cs_defcflag = zs_def_cflag; 259 260 /* Make these correspond to cs_defcflag (-crtscts) */ 261 cs->cs_rr0_dcd = ZSRR0_DCD; 262 cs->cs_rr0_cts = 0; 263 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 264 cs->cs_wr5_rts = 0; 265 266 /* 267 * Clear the master interrupt enable. 268 * The INTENA is common to both channels, 269 * so just do it on the A channel. 270 */ 271 if (channel == 0) { 272 zs_write_reg(cs, 9, 0); 273 } 274 /* 275 * Look for a child driver for this channel. 276 * The child attach will setup the hardware. 277 */ 278 if (!config_found(self, (void *)&zsc_args, zs_print)) { 279 /* No sub-driver. Just reset it. */ 280 u_char reset = (channel == 0) ? 281 ZSWR9_A_RESET : ZSWR9_B_RESET; 282 283 s = splhigh(); 284 zs_write_reg(cs, 9, reset); 285 splx(s); 286 } 287 } 288 289 290 zsc->sc_si = softintr_establish(IPL_SOFTSERIAL, zssoft, zsc); 291 bus_intr_establish(zsc->zsc_bustag, SYS_INTR_SCC0, 0, 0, zshard, NULL); 292 293 evcnt_attach_dynamic(&zsc->zs_intrcnt, EVCNT_TYPE_INTR, NULL, 294 self->dv_xname, "intr"); 295 296 /* 297 * Set the master interrupt enable and interrupt vector. 298 * (common to both channels, do it on A) 299 */ 300 cs = zsc->zsc_cs[0]; 301 s = splhigh(); 302 /* interrupt vector */ 303 zs_write_reg(cs, 2, zs_init_reg[2]); 304 /* master interrupt control (enable) */ 305 zs_write_reg(cs, 9, zs_init_reg[9]); 306 splx(s); 307 } 308 309 static int 310 zs_print(aux, name) 311 void *aux; 312 const char *name; 313 { 314 struct zsc_attach_args *args = aux; 315 316 if (name != NULL) 317 printf("%s: ", name); 318 319 if (args->channel != -1) 320 printf(" channel %d", args->channel); 321 322 return UNCONF; 323 } 324 325 /* 326 * Our ZS chips all share a common, autovectored interrupt, 327 * so we have to look at all of them on each interrupt. 328 */ 329 static int 330 zshard(arg) 331 void *arg; 332 { 333 register struct zsc_softc *zsc; 334 register int unit, rval, softreq; 335 336 rval = 0; 337 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 338 zsc = zsc_cd.cd_devs[unit]; 339 if (zsc == NULL) 340 continue; 341 rval |= zsc_intr_hard(zsc); 342 softreq = zsc->zsc_cs[0]->cs_softreq; 343 softreq |= zsc->zsc_cs[1]->cs_softreq; 344 if (softreq && (zssoftpending == 0)) { 345 zssoftpending = 1; 346 softintr_schedule(zsc->sc_si); 347 } 348 zsc->zs_intrcnt.ev_count++; 349 } 350 return rval; 351 } 352 353 /* 354 * Similar scheme as for zshard (look at all of them) 355 */ 356 void 357 zssoft(arg) 358 void *arg; 359 { 360 register struct zsc_softc *zsc; 361 register int s, unit; 362 363 /* This is not the only ISR on this IPL. */ 364 if (zssoftpending == 0) 365 return; 366 367 /* 368 * The soft intr. bit will be set by zshard only if 369 * the variable zssoftpending is zero. The order of 370 * these next two statements prevents our clearing 371 * the soft intr bit just after zshard has set it. 372 */ 373 /*isr_soft_clear(ZSSOFT_PRI);*/ 374 zssoftpending = 0; 375 376 /* Make sure we call the tty layer at spltty. */ 377 s = spltty(); 378 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 379 zsc = zsc_cd.cd_devs[unit]; 380 if (zsc == NULL) 381 continue; 382 (void) zsc_intr_soft(zsc); 383 } 384 splx(s); 385 return; 386 } 387 388 389 /* 390 * Compute the current baud rate given a ZS channel. 391 */ 392 static int 393 zs_get_speed(cs) 394 struct zs_chanstate *cs; 395 { 396 int tconst; 397 398 tconst = zs_read_reg(cs, 12); 399 tconst |= zs_read_reg(cs, 13) << 8; 400 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 401 } 402 403 /* 404 * MD functions for setting the baud rate and control modes. 405 */ 406 int 407 zs_set_speed(cs, bps) 408 struct zs_chanstate *cs; 409 int bps; /* bits per second */ 410 { 411 int tconst, real_bps; 412 413 #if 0 414 while (!(zs_read_csr(cs) & ZSRR0_TX_READY)) 415 {/*nop*/} 416 #endif 417 /* Wait for transmit buffer to empty */ 418 if (bps == 0) { 419 return (0); 420 } 421 422 #ifdef DIAGNOSTIC 423 if (cs->cs_brg_clk == 0) 424 panic("zs_set_speed"); 425 #endif 426 427 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 428 if (tconst < 0) 429 return (EINVAL); 430 431 /* Convert back to make sure we can do it. */ 432 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 433 434 /* XXX - Allow some tolerance here? */ 435 #if 0 436 if (real_bps != bps) 437 return (EINVAL); 438 #endif 439 440 cs->cs_preg[12] = tconst; 441 cs->cs_preg[13] = tconst >> 8; 442 443 /* Caller will stuff the pending registers. */ 444 return (0); 445 } 446 447 int 448 zs_set_modes(cs, cflag) 449 struct zs_chanstate *cs; 450 int cflag; /* bits per second */ 451 { 452 int s; 453 454 /* 455 * Output hardware flow control on the chip is horrendous: 456 * if carrier detect drops, the receiver is disabled, and if 457 * CTS drops, the transmitter is stoped IN MID CHARACTER! 458 * Therefore, NEVER set the HFC bit, and instead use the 459 * status interrupt to detect CTS changes. 460 */ 461 s = splzs(); 462 cs->cs_rr0_pps = 0; 463 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 464 cs->cs_rr0_dcd = 0; 465 if ((cflag & MDMBUF) == 0) 466 cs->cs_rr0_pps = ZSRR0_DCD; 467 } else 468 cs->cs_rr0_dcd = ZSRR0_DCD; 469 if ((cflag & CRTSCTS) != 0) { 470 cs->cs_wr5_dtr = ZSWR5_DTR; 471 cs->cs_wr5_rts = ZSWR5_RTS; 472 cs->cs_rr0_cts = ZSRR0_CTS; 473 } else if ((cflag & MDMBUF) != 0) { 474 cs->cs_wr5_dtr = 0; 475 cs->cs_wr5_rts = ZSWR5_DTR; 476 cs->cs_rr0_cts = ZSRR0_DCD; 477 } else { 478 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 479 cs->cs_wr5_rts = 0; 480 cs->cs_rr0_cts = 0; 481 } 482 splx(s); 483 484 /* Caller will stuff the pending registers. */ 485 return (0); 486 } 487 488 489 /* 490 * Read or write the chip with suitable delays. 491 */ 492 493 u_char 494 zs_read_reg(cs, reg) 495 struct zs_chanstate *cs; 496 u_char reg; 497 { 498 u_char val; 499 struct zs_channel *zsc = (struct zs_channel *)cs; 500 501 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 502 ZS_DELAY(); 503 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 504 ZS_DELAY(); 505 return val; 506 } 507 508 void 509 zs_write_reg(cs, reg, val) 510 struct zs_chanstate *cs; 511 u_char reg, val; 512 { 513 struct zs_channel *zsc = (struct zs_channel *)cs; 514 515 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 516 ZS_DELAY(); 517 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 518 ZS_DELAY(); 519 } 520 521 u_char zs_read_csr(cs) 522 struct zs_chanstate *cs; 523 { 524 struct zs_channel *zsc = (struct zs_channel *)cs; 525 register u_char val; 526 527 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 528 ZS_DELAY(); 529 return val; 530 } 531 532 void zs_write_csr(cs, val) 533 struct zs_chanstate *cs; 534 u_char val; 535 { 536 struct zs_channel *zsc = (struct zs_channel *)cs; 537 538 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 539 ZS_DELAY(); 540 } 541 542 u_char zs_read_data(cs) 543 struct zs_chanstate *cs; 544 { 545 struct zs_channel *zsc = (struct zs_channel *)cs; 546 register u_char val; 547 548 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA); 549 ZS_DELAY(); 550 return val; 551 } 552 553 void zs_write_data(cs, val) 554 struct zs_chanstate *cs; 555 u_char val; 556 { 557 struct zs_channel *zsc = (struct zs_channel *)cs; 558 559 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA, val); 560 ZS_DELAY(); 561 } 562 563 void 564 zs_abort(cs) 565 struct zs_chanstate *cs; 566 { 567 #if defined(KGDB) 568 zskgdb(cs); 569 #elif defined(DDB) 570 Debugger(); 571 #endif 572 } 573 574 575 /*********************************************************/ 576 /* Polled character I/O functions for console and KGDB */ 577 /*********************************************************/ 578 579 struct zschan * 580 zs_get_chan_addr(zs_unit, channel) 581 int zs_unit, channel; 582 { 583 struct zsdevice *addr; 584 struct zschan *zc; 585 586 if (zs_unit >= NZS) 587 return NULL; 588 589 addr = (struct zsdevice *) ZS0_ADDR; 590 591 if (channel == 0) { 592 zc = &addr->zs_chan_a; 593 } else { 594 zc = &addr->zs_chan_b; 595 } 596 return (zc); 597 } 598 599 int 600 zs_getc(arg) 601 void *arg; 602 { 603 register volatile struct zschan *zc = arg; 604 register int s, c, rr0; 605 606 s = splhigh(); 607 /* Wait for a character to arrive. */ 608 do { 609 rr0 = zc->zc_csr; 610 ZS_DELAY(); 611 } while ((rr0 & ZSRR0_RX_READY) == 0); 612 613 c = zc->zc_data; 614 ZS_DELAY(); 615 splx(s); 616 617 return (c); 618 } 619 620 /* 621 * Polled output char. 622 */ 623 void 624 zs_putc(arg, c) 625 void *arg; 626 int c; 627 { 628 register volatile struct zschan *zc = arg; 629 register int s, rr0; 630 631 s = splhigh(); 632 /* Wait for transmitter to become ready. */ 633 do { 634 rr0 = zc->zc_csr; 635 ZS_DELAY(); 636 } while ((rr0 & ZSRR0_TX_READY) == 0); 637 638 zc->zc_data = c; 639 wbflush(); 640 ZS_DELAY(); 641 splx(s); 642 } 643 644 /***************************************************************/ 645 646 static void zscnprobe __P((struct consdev *)); 647 static void zscninit __P((struct consdev *)); 648 static int zscngetc __P((dev_t)); 649 static void zscnputc __P((dev_t, int)); 650 static void zscnpollc __P((dev_t, int)); 651 652 static int cons_port; 653 654 struct consdev consdev_zs = { 655 zscnprobe, 656 zscninit, 657 zscngetc, 658 zscnputc, 659 zscnpollc 660 }; 661 662 void 663 zscnprobe(cn) 664 struct consdev *cn; 665 { 666 } 667 668 void 669 zscninit(cn) 670 struct consdev *cn; 671 { 672 extern const struct cdevsw zstty_cdevsw; 673 674 cons_port = prom_getconsole(); 675 cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), cons_port); 676 cn->cn_pri = CN_REMOTE; 677 zs_hwflags[0][cons_port] = ZS_HWFLAG_CONSOLE; 678 } 679 680 int 681 zscngetc(dev) 682 dev_t dev; 683 { 684 struct zschan *zs; 685 686 zs = zs_get_chan_addr(0, cons_port); 687 return zs_getc(zs); 688 } 689 690 void 691 zscnputc(dev, c) 692 dev_t dev; 693 int c; 694 { 695 struct zschan *zs; 696 697 zs = zs_get_chan_addr(0, cons_port); 698 zs_putc(zs, c); 699 } 700 701 void 702 zscnpollc(dev, on) 703 dev_t dev; 704 int on; 705 { 706 } 707