1 /* $NetBSD: pccreg.h,v 1.9 2001/08/12 18:33:13 scw Exp $ */ 2 3 /* 4 * 5 * Copyright (c) 1995 Charles D. Cranor 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles D. Cranor. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * peripheral channel controller on mvme147 36 */ 37 #ifndef __MVME68K_PCCREG_H 38 #define __MVME68K_PCCREG_H 39 40 /* 41 * Offsets to the MVME147's onboard device registers. 42 * (Relative to the bus_space_tag_t passed in from 'mainbus') 43 */ 44 #define PCC_LE_OFF 0x0800 /* offset of LANCE ethernet chip */ 45 #define PCC_VME_OFF 0x1000 /* offset of VME chip */ 46 #define PCC_LPT_OFF 0x1800 /* offset of parallel port register */ 47 #define PCC_ZS0_OFF 0x2000 /* offset of first 8530 UART */ 48 #define PCC_ZS1_OFF 0x2800 /* offset of second 8530 UART */ 49 #define PCC_WDSC_OFF 0x3000 /* offset of 33c93 SCSI chip */ 50 51 /* 52 * This is needed to figure out the boot device. 53 * (The physical address of the boot device's registers are passed in 54 * from the Boot ROM) 55 */ 56 #define PCC_PADDR(off) ((void *)(0xfffe0000u + (off))) 57 58 /* 59 * The PCC chip's own registers. These are 8-bits wide, unless 60 * otherwise indicated. 61 */ 62 #define PCCREG_DMA_TABLE_ADDR 0x00 /* DMA table address (32-bit) */ 63 #define PCCREG_DMA_DATA_ADDR 0x04 /* DMA data address (32-bit) */ 64 #define PCCREG_DMA_BYTE_COUNT 0x08 /* DMA byte count (32-bit) */ 65 #define PCCREG_DMA_DATA_HOLD 0x0c /* DMA data hold register (32-bit) */ 66 #define PCCREG_TMR1_PRELOAD 0x10 /* Timer1 preload (16-bit) */ 67 #define PCCREG_TMR1_COUNT 0x12 /* Timer1 count (16-bit) */ 68 #define PCCREG_TMR2_PRELOAD 0x14 /* Timer2 preload (16-bit) */ 69 #define PCCREG_TMR2_COUNT 0x16 /* Timer2 count (16-bit) */ 70 #define PCCREG_TMR1_INTR_CTRL 0x18 /* Timer1 interrupt ctrl */ 71 #define PCCREG_TMR1_CONTROL 0x19 /* Timer1 ctrl reg */ 72 #define PCCREG_TMR2_INTR_CTRL 0x1a /* Timer2 interrupt ctrl */ 73 #define PCCREG_TMR2_CONTROL 0x1b /* Timer2 ctrl reg */ 74 #define PCCREG_ACFAIL_INTR_CTRL 0x1c /* ACFAIL intr reg */ 75 #define PCCREG_WDOG_INTR_CTRL 0x1d /* Watchdog intr reg */ 76 #define PCCREG_PRNT_INTR_CTRL 0x1e /* Printer intr reg */ 77 #define PCCREG_PRNT_CONTROL 0x1f /* Printer ctrl */ 78 #define PCCREG_DMA_INTR_CTRL 0x20 /* DMA interrupt control */ 79 #define PCCREG_DMA_CONTROL 0x21 /* DMA csr */ 80 #define PCCREG_BUSERR_INTR_CTRL 0x22 /* Bus error interrupt */ 81 #define PCCREG_DMA_STATUS 0x23 /* DMA status register */ 82 #define PCCREG_ABORT_INTR_CTRL 0x24 /* ABORT interrupt control reg */ 83 #define PCCREG_TABLE_ADDR_FC 0x25 /* Table address function code reg */ 84 #define PCCREG_SERIAL_INTR_CTRL 0x26 /* Serial interrupt reg */ 85 #define PCCREG_GENERAL_CONTROL 0x27 /* General control register */ 86 #define PCCREG_LANCE_INTR_CTRL 0x28 /* Ethernet interrupt */ 87 #define PCCREG_GENERAL_STATUS 0x29 /* General status */ 88 #define PCCREG_SCSI_INTR_CTRL 0x2a /* SCSI interrupt reg */ 89 #define PCCREG_SLAVE_BASE_ADDR 0x2b /* Slave base addr reg */ 90 #define PCCREG_SOFT1_INTR_CTRL 0x2c /* Software interrupt #1 cr */ 91 #define PCCREG_VECTOR_BASE 0x2d /* Interrupt base vector register */ 92 #define PCCREG_SOFT2_INTR_CTRL 0x2e /* Software interrupt #2 cr */ 93 #define PCCREG_REVISION 0x2f /* Revision level */ 94 95 #define PCCREG_SIZE 0x30 96 97 /* 98 * Convenience macros for reading the PCC chip's registers 99 * through bus_space. 100 */ 101 #define pcc_reg_read(sc,r) \ 102 bus_space_read_1((sc)->sc_bust, (sc)->sc_bush, (r)) 103 #define pcc_reg_read16(sc,r) \ 104 bus_space_read_2((sc)->sc_bust, (sc)->sc_bush, (r)) 105 #define pcc_reg_read32(sc,r) \ 106 bus_space_read_4((sc)->sc_bust, (sc)->sc_bush, (r)) 107 #define pcc_reg_write(sc,r,v) \ 108 bus_space_write_1((sc)->sc_bust, (sc)->sc_bush, (r), (v)) 109 #define pcc_reg_write16(sc,r,v) \ 110 bus_space_write_2((sc)->sc_bust, (sc)->sc_bush, (r), (v)) 111 #define pcc_reg_write32(sc,r,v) \ 112 bus_space_write_4((sc)->sc_bust, (sc)->sc_bush, (r), (v)) 113 114 115 /* 116 * we lock off our interrupt vector at 0x40. 117 */ 118 119 #define PCC_VECBASE 0x40 120 #define PCC_NVEC 12 121 122 /* 123 * vectors we use 124 */ 125 126 #define PCCV_ACFAIL 0 127 #define PCCV_BERR 1 128 #define PCCV_ABORT 2 129 #define PCCV_ZS 3 130 #define PCCV_LE 4 131 #define PCCV_SCSI 5 132 #define PCCV_DMA 6 133 #define PCCV_PRINTER 7 134 #define PCCV_TIMER1 8 135 #define PCCV_TIMER2 9 136 #define PCCV_SOFT1 10 137 #define PCCV_SOFT2 11 138 139 /* 140 * enable interrupt 141 */ 142 143 #define PCC_ICLEAR 0x80 144 #define PCC_IENABLE 0x08 145 146 /* 147 * interrupt mask 148 */ 149 150 #define PCC_IMASK 0x7 151 152 /* 153 * clock/timer 154 */ 155 156 #define PCC_TIMERACK 0x80 /* ack intr */ 157 #define PCC_TIMER100HZ 63936 /* load value for 100Hz */ 158 #define PCC_TIMERCLEAR 0x0 /* reset and clear timer */ 159 #define PCC_TIMERENABLE 0x1 /* Enable clock */ 160 #define PCC_TIMERSTOP 0x3 /* stop clock, but don't clear it */ 161 #define PCC_TIMERSTART 0x7 /* start timer */ 162 #define PCC_TIMEROVFLSHIFT 4 163 164 #define pcc_timer_hz2lim(hz) (65536 - (160000/(hz))) 165 #define pcc_timer_us2lim(us) (65536 - (160000/(1000000/(us)))) 166 #define pcc_timer_cnt2us(cnt) ((((cnt) - PCC_TIMER100HZ) * 25) / 4) 167 168 /* 169 * serial control 170 */ 171 172 #define PCC_ZSEXTERN 0x10 /* let PCC supply vector */ 173 174 /* 175 * abort switch 176 */ 177 178 #define PCC_ABORT_IEN 0x08 /* enable interrupt */ 179 #define PCC_ABORT_ABS 0x40 /* current state of switch */ 180 #define PCC_ABORT_ACK 0x80 /* interrupt active; write to ack */ 181 182 /* 183 * general control register 184 */ 185 186 #define PCC_GENCR_IEN 0x10 /* global interrupt enable */ 187 188 /* 189 * slave base address register 190 */ 191 #define PCC_SLAVE_BASE_MASK (0x01fu) 192 193 #endif /* __MVME68K_PCCREG_H */ 194