1 /* $NetBSD: vme_pccreg.h,v 1.6 2008/04/28 20:23:29 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _MVME68K_VME_PCCREG_H 33 #define _MVME68K_VME_PCCREG_H 34 35 /* 36 * Register map of the Type 1 VMEchip found on the MVME-147 37 * Peripheral Channel Controller. 38 */ 39 40 /* 41 * Local control registers... 42 */ 43 #define VME1REG_SCON 0x01 44 #define VME1_SCON_SWITCH 0x01 /* SCON jumper is set */ 45 #define VME1_SCON_SRESET 0x02 /* assert SRESET on bus */ 46 #define VME1_SCON_SYSFAIL 0x04 /* assert SYSFAIL on bus */ 47 #define VME1_SCON_ROBIN 0x08 /* round robin bus requests */ 48 49 #define VME1REG_REQCONF 0x03 50 #define VME1_REQ_IPLMASK 0x03 /* interrupt level for requester */ 51 #define VME1_REQ_RNEVER 0x08 52 #define VME1_REQ_RWD 0x10 53 #define VME1_REQ_DHB 0x40 54 #define VME1_REQ_DWB 0x80 55 56 #define VME1REG_MASCONF 0x05 57 #define VME1_MAS_D16 0x01 /* force d8/16 accesses only */ 58 #define VME1_MAS_MASA24 0x02 /* send address mod for A24 access */ 59 #define VME1_MAS_MASA16 0x04 /* send address mod for A16 access */ 60 #define VME1_MAS_MASUAT 0x08 /* handle unaligned VME cycles */ 61 #define VME1_MAS_CFILL 0x10 /* DO NOT USE */ 62 #define VME1_MAS_MASWP 0x20 /* VME fast mode (DO NOT USE) */ 63 64 #define VME1REG_SLCONF 0x07 65 #define VME1_SLAVE_SLVD16 0x01 /* DO NOT USE */ 66 #define VME1_SLAVE_SLVWP 0x20 /* DO NOT USE */ 67 #define VME1_SLAVE_SLVEN 0x80 /* allow access to onboard DRAM */ 68 69 #define VME1REG_TIMERCONF 0x09 70 #define VME1_TIMER_LOCAL_MASK 0x03 71 #define VME1_TIMER_LOCAL_T0 0x00 /* local timeout 102 microsec */ 72 #define VME1_TIMER_LOCAL_T1 0x01 /* local timeout 205 microsec */ 73 #define VME1_TIMER_LOCAL_T2 0x02 /* local timeout 410 microsec */ 74 #define VME1_TIMER_LOCAL_T3 0x03 /* local timeout disabled */ 75 #define VME1_TIMER_VMEACC_MASK 0x0c 76 #define VME1_TIMER_VMEACC_T0 0x00 /* VME access timeout 102 microsec */ 77 #define VME1_TIMER_VMEACC_T1 0x04 /* VME access timeout 1.6 millisec */ 78 #define VME1_TIMER_VMEACC_T2 0x08 /* VME access timeout 51 millisec */ 79 #define VME1_TIMER_VMEACC_T3 0x0c /* VME access timeout disabled */ 80 #define VME1_TIMER_VMEGLO_MASK 0x30 81 #define VME1_TIMER_VMEGLO_T0 0x00 /* VME glob timeout 102 microsec */ 82 #define VME1_TIMER_VMEGLO_T1 0x10 /* VME glob timeout 205 microsec */ 83 #define VME1_TIMER_VMEGLO_T2 0x20 /* VME glob timeout 410 microsec */ 84 #define VME1_TIMER_VMEGLO_T3 0x30 /* VME glob timeout disabled */ 85 #define VME1_TIMER_ARBTO 0x40 /* enable VME arbitration timer */ 86 87 #define VME1REG_SLADDRMOD 0x0b 88 #define VME1_SLMOD_DATA 0x01 89 #define VME1_SLMOD_PRGRM 0x02 90 #define VME1_SLMOD_BLOCK 0x04 91 #define VME1_SLMOD_SHORT 0x08 92 #define VME1_SLMOD_STND 0x10 93 #define VME1_SLMOD_EXTED 0x20 94 #define VME1_SLMOD_USER 0x40 95 #define VME1_SLMOD_SUPER 0x80 96 97 #define VME1REG_MSADDRMOD 0x0d 98 #define VME1_MSMOD_AM_MASK 0x3f 99 #define VME1_MSMOD_AMSEL 0x80 100 101 #define VME1REG_IRQEN 0x0f 102 #define VME1_IRQ_VME(x) (1 << (x)) 103 104 #define VME1REG_UIREQEN 0x11 105 #define VME1REG_UIRQ 0x13 106 #define VME1REG_IRQ 0x15 107 #define VME1REG_VMEID 0x17 108 #define VME1REG_BUSERR 0x19 109 #define VME1REG_GCSR 0x1b 110 111 112 /* 113 * Global Status and Control registers. 114 */ 115 #define VME1REG_GCSR_GR0 0x21 116 #define VME1REG_GCSR_GR1 0x23 117 #define VME1REG_GCSR_BOARDID 0x25 118 #define VME1REG_GCSR_GPR0 0x27 119 #define VME1REG_GCSR_GPR1 0x29 120 #define VME1REG_GCSR_GPR2 0x2b 121 #define VME1REG_GCSR_GPR3 0x2d 122 #define VME1REG_GCSR_GPR4 0x2f 123 124 /* 125 * Length of the VME chip's register mapping 126 */ 127 #define VME1REG_SIZE 0x30 128 129 130 /* 131 * Convenience macros for reading and writing the registers 132 */ 133 #define vme1_reg_read(sc,r) \ 134 bus_space_read_1((sc)->sc_mvmebus.sc_bust, (sc)->sc_bush, (r)) 135 #define vme1_reg_write(sc,r,v) \ 136 bus_space_write_1((sc)->sc_mvmebus.sc_bust, (sc)->sc_bush, (r), (v)) 137 138 /* 139 * The Type 1 VMEchip decoder maps VME address space to system addresses 140 * like this: 141 * 142 * A24D32: 0x00000000 - 0x00ffffff 143 * A32D32: 0x01000000 - 0xefffffff 144 * A24D16: 0xf0000000 - 0xf0ffffff 145 * A32D16: 0xf1000000 - 0xff7fffff 146 * A16D16: 0xffff0000 - 0xffffffff 147 * 148 * Note that the first A24D32 range is overlayed with onboard RAM. Thus 149 * an 8Mb board will only allow A24D32:0x00800000 - 0x00ffffff. When 150 * onboard RAM is >= 16Mb, the A24D32 range is unavailable and the RAM 151 * starts encroaching on the A32D32 range. 152 */ 153 #define VME1_A24D32_LOC_START (0x00000000u) 154 #define VME1_A24D32_START (0x00000000u) 155 #define VME1_A24D32_END (0x00ffffffu) 156 157 #define VME1_A32D32_LOC_START (0x00000000u) 158 #define VME1_A32D32_START (0x01000000u) 159 #define VME1_A32D32_END (0xefffffffu) 160 161 #define VME1_A24D16_LOC_START (0xf0000000u) 162 #define VME1_A24D16_START (0x00000000u) 163 #define VME1_A24D16_END (0x00ffffffu) 164 165 #define VME1_A32D16_LOC_START (0x00000000u) 166 #define VME1_A32D16_START (0xf1000000u) 167 #define VME1_A32D16_END (0xff7fffffu) 168 169 #define VME1_A16D16_LOC_START (0xffff0000u) 170 #define VME1_A16D16_START (0x00000000u) 171 #define VME1_A16D16_END (0x0000ffffu) 172 173 #define VME1_A32_MASK (0xffffffffu) 174 #define VME1_A24_MASK (0x00ffffffu) 175 #define VME1_A16_MASK (0x0000ffffu) 176 177 #endif /* _MVME68K_VME_PCCREG_H */ 178