1/* $NetBSD: nwmmu.S,v 1.6 2002/04/05 16:58:10 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 2000, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com>, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <machine/asm.h> 40#include <arm/armreg.h> 41#include <arm/arm32/pte.h> 42 43 .section .start,"ax",%progbits 44 45 .global _C_LABEL(nwstart) 46_C_LABEL(nwstart): 47 /* 48 * The NetWinder's NeTTrom has disabled the MMU 49 * and loaded us at 0x0000c000. 50 * 51 * We are going to plop a 16K L1 table at 0x00008000 and: 52 * 53 * 1. Map the entire address space VA==PA. 54 * 55 * 2. Double-map the first 64MB of RAM at 0xf0000000. 56 * 57 * 3. Map the 21285's PCI I/O space at the virtual 58 * address that we will later map it to in 59 * netwinder_start(). 60 */ 61 62 /* 63 * Step 1: Map the entire address space VA==PA. 64 */ 65 add r0, pc, #(Ltable - . - 8) 66 ldr r0, [r0] /* r0 = &l1table */ 67 68 mov r3, #(L1_S_AP(AP_KRW)) 69 orr r3, r3, #(L1_TYPE_S) 70 mov r2, #0x100000 /* advance by 1MB */ 71 mov r1, #0x1000 /* 4096MB */ 721: 73 str r3, [r0], #0x04 74 add r3, r3, r2 75 subs r1, r1, #1 76 bgt 1b 77 78 /* 79 * Step 2: Map VA 0xf0000000->0xf3ffffff to PA 0x00000000->0x03ffffff. 80 */ 81 add r0, pc, #(Ltable - . - 8) 82 ldr r0, [r0] /* r0 = &l1table */ 83 84 mov r3, #(L1_S_AP(AP_KRW)) 85 orr r3, r3, #(L1_TYPE_S) 86 add r0, r0, #(0xf00 * 4) /* offset to 0xf00xxxxx */ 87 mov r1, #0x40 /* 64MB */ 881: 89 str r3, [r0], #0x04 90 add r3, r3, r2 91 subs r1, r1, #1 92 bgt 1b 93 94 /* 95 * Step 3: Map VA 0xfd200000 to PA 0x7c000000 96 */ 97 add r0, pc, #(Ltable - . - 8) 98 ldr r0, [r0] /* r0 = &l1table */ 99 100 mov r3, #(L1_S_AP(AP_KRW)) 101 orr r3, r3, #(L1_TYPE_S) 102 orr r3, r3, #0x7c000000 103 add r0, r0, #(0xfd0 * 4) /* offset to 0xfd0xxxxx */ 104 str r3, [r0, #0x08] /* -> 0xfd2xxxxx */ 105 106 /* OK! Page table is set up. Give it to the CPU. */ 107 add r0, pc, #(Ltable - . - 8) 108 ldr r0, [r0] 109 mcr p15, 0, r0, c2, c0, 0 110 111 /* Flush the old TLBs, just in case. */ 112 mcr p15, 0, r0, c8, c7, 0 113 114 /* Set the Domain Access register. Very important! */ 115 mov r0, #1 116 mcr p15, 0, r0, c3, c0, 0 117 118 /* OK, let's enable the MMU. */ 119 mrc p15, 0, r2, c1, c0, 0 120 orr r2, r2, #CPU_CONTROL_MMU_ENABLE 121 mcr p15, 0, r2, c1, c0, 0 122 123 nop 124 nop 125 nop 126 127 /* ...and now we jump to the "real" kernel entry point! */ 128 add r0, pc, #(Lstart - . - 8) 129 ldr pc, [r0] 130 131Ltable: 132 .word 0x00008000 133 134Lstart: 135 .word start 136