1 /* $NetBSD: espreg.h,v 1.4 2001/09/16 10:39:10 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Rolf Grossmann. All rights reserved. 5 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Peter Galbavy. 17 * This product includes software developed by Rolf Grossmann. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Register addresses, relative to some base address. 35 */ 36 37 #define ESP_DCTL 0x20 /* RW - DMA Control */ 38 #define ESPDCTL_CLKMSK 0xc0 /* Clock Selection Bits */ 39 #define ESPDCTL_10MHZ 0x00 /* 10 MHz Clock */ 40 #define ESPDCTL_12MHZ 0x40 /* 12.5 MHz Clock */ 41 #define ESPDCTL_16MHZ 0xc0 /* 16.6 MHz Clock */ 42 #define ESPDCTL_20MHZ 0x80 /* 20 MHz Clock */ 43 #define ESPDCTL_INTENB 0x20 /* Interrupt Enable */ 44 #define ESPDCTL_DMAMOD 0x10 /* 1 = Enable DMA */ 45 #define ESPDCTL_DMARD 0x08 /* 1 = scsi->mem (read) */ 46 #define ESPDCTL_FLUSH 0x04 /* Flush Fifo */ 47 #define ESPDCTL_RESET 0x02 /* Reset SCSI Chip */ 48 #define ESPDCTL_WD3392 0x01 /* 0 = NCR 5390 */ 49 50 #define ESP_DCTL_BITS \ 51 "\20\06INTENB\05DMAMOD\04DMARD\03FLUSH\02RESET\01WD3392" 52 53 #define ESP_DSTAT 0x21 /* RW - DMA Status */ 54 #define ESPDSTAT_STATE 0xc0 /* DMA/SCSI Bank State */ 55 #define ESPDSTAT_D0S0 0x00 /* DMA rdy b. 0, SCSI b. 0 */ 56 #define ESPDSTAT_D0S1 0x40 /* DMA req b. 0, SCSI b. 1 */ 57 #define ESPDSTAT_D1S1 0x80 /* DMA rdy b. 0, SCSI b. 1 */ 58 59 60 #define ESP_DEVICE_SIZE (ESP_DSTAT+1) 61