1 /* $NetBSD: mb8795reg.h,v 1.2 2001/03/31 06:56:54 dbj Exp $ */ 2 /* 3 * Copyright (c) 1998 Darrin B. Jewell 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Darrin B. Jewell 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Fujitsu Ethernet Data Link Controller (MB8795) 34 * and the Fujitsu Manchester Encoder/Decoder (MB502). 35 */ 36 37 #if 0 38 struct xe_regs { 39 unsigned char xe_txstat; /* tx status */ 40 unsigned char xe_txmask; /* tx interrupt condition mask */ 41 unsigned char xe_rxstat; /* rx status */ 42 unsigned char xe_rxmask; /* rx interrupt condition mask */ 43 unsigned char xe_txmode; /* tx control/mode register */ 44 unsigned char xe_rxmode; /* rx control/mode register */ 45 unsigned char xe_reset; /* reset mode */ 46 unsigned char xe_tdc_lsb; /* transmit data count LSB */ 47 unsigned char xe_addr[6]; /* physical address */ 48 unsigned char xe_reserved; 49 unsigned char xe_tdc_msb; /* transmit data count MSB */ 50 }; 51 #endif 52 53 /* transmitter status (address 0) */ 54 #define XE_TXSTAT 0 55 56 #define XE_TXSTAT_READY 0x80 /* ready for packet */ 57 #define XE_TXSTAT_BUSY 0x40 /* receive carrier detect */ 58 #define XE_TXSTAT_TXRECV 0x20 /* transmission received */ 59 #define XE_TXSTAT_SHORTED 0x10 /* possible coax short */ 60 #define XE_TXSTAT_UNDERFLOW 0x08 /* underflow on xmit */ 61 #define XE_TXSTAT_COLLERR 0x04 /* collision detected */ 62 #define XE_TXSTAT_COLLERR16 0x02 /* 16th collision error */ 63 #define XE_TXSTAT_PARERR 0x01 /* parity error in tx data */ 64 #define XE_TXSTAT_CLEAR 0xff /* clear all status bits */ 65 66 #define XE_TXSTAT_BITS \ 67 "\20\10READY\07BUSY\06TXRECV\05SHORTED\ 68 \04UNDERFLOW\03COLLERR\02COLLERR16\01PARERR" 69 70 /* transmit masks (address 1) */ 71 #define XE_TXMASK 1 72 73 #define XE_TXMASK_READYIE 0x80 /* tx int on packet ready */ 74 #define XE_TXMASK_TXRXIE 0x20 /* tx int on transmit rec'd */ 75 #define XE_TXMASK_UNDERFLOWIE 0x08 /* tx int on underflow */ 76 #define XE_TXMASK_COLLIE 0x04 /* tx int on collision */ 77 #define XE_TXMASK_COLL16IE 0x02 /* tx int on 16th collision */ 78 #define XE_TXMASK_PARERRIE 0x01 /* tx int on parity error */ 79 80 #define XE_TXMASK_BITS \ 81 "\20\10READYIE\06TXRXIE\04UNDERFLOWIE\03COLLIE\02COLL16IE\01PARERRIE" 82 83 /* cummulative receiver status (address 2) */ 84 #define XE_RXSTAT 2 85 86 #define XE_RXSTAT_OK 0x80 /* packet received is correct */ 87 #define XE_RXSTAT_RESET 0x10 /* reset packet received */ 88 #define XE_RXSTAT_SHORT 0x08 /* < minimum length */ 89 #define XE_RXSTAT_ALIGNERR 0x04 /* alignment error */ 90 #define XE_RXSTAT_CRCERR 0x02 /* CRC error */ 91 #define XE_RXSTAT_OVERFLOW 0x01 /* receiver FIFO overflow */ 92 #define XE_RXSTAT_CLEAR 0xff /* clear all status bits */ 93 94 #define XE_RXSTAT_BITS \ 95 "\20\10OK\05RESET\04SHORT\03ALIGNERR\02CRCERR\01OVERFLOW" 96 97 /* receiver masks (address 3) */ 98 #define XE_RXMASK 3 99 100 #define XE_RXMASK_OKIE 0x80 /* rx int on packet ok */ 101 #define XE_RXMASK_RESETIE 0x10 /* rx int on reset packet */ 102 #define XE_RXMASK_SHORTIE 0x08 /* rx int on short packet */ 103 #define XE_RXMASK_ALIGNERRIE 0x04 /* rx int on align error */ 104 #define XE_RXMASK_CRCERRIE 0x02 /* rx int on CRC error */ 105 #define XE_RXMASK_OVERFLOWIE 0x01 /* rx int on overflow error */ 106 107 #define XE_RXMASK_BITS \ 108 "\20\10OKIE\05RESETIE\04SHORTIE\03ALIGNERRIE\02CRCERRIE\01OVERFLOWIE" 109 110 /* transmitter mode (address 4) */ 111 #define XE_TXMODE 4 112 113 #define XE_TXMODE_COLLMASK 0xF0 /* collision count */ 114 #define XE_TXMODE_PARIGNORE 0x08 /* ignore parity */ 115 #define XE_TXMODE_LB_DISABLE 0x02 /* loop back disabled */ 116 #define XE_TXMODE_DISCONTENT 0x01 /* disable contention (rx carrier) */ 117 118 /* Should probably figure out how to put in the COLLMASK value in here */ 119 #define XE_TXMODE_BITS \ 120 "\20\04PARIGNORE\02LB_DISABLE\01DISCONTENT" 121 122 /* receiver mode (address 5) */ 123 #define XE_RXMODE 5 124 125 #define XE_RXMODE_TEST 0x80 /* Must be zero for normal op */ 126 #define XE_RXMODE_ADDRSIZE 0x10 /* reduces NODE match to 5 chars */ 127 #define XE_RXMODE_SHORTENABLE 0x08 /* rx packets >= 10 bytes */ 128 #define XE_RXMODE_RESETENABLE 0x04 /* must be zero */ 129 #define XE_RXMODE_PROMISCUOUS 0x03 /* accept all packets */ 130 #define XE_RXMODE_MULTICAST 0x02 /* accept broad/multicasts */ 131 #define XE_RXMODE_NORMAL 0x01 /* accept broad/limited multicasts */ 132 #define XE_RXMODE_OFF 0x00 /* accept no packets */ 133 134 /* this define is less useful for the promiscuous bits, bit I leave it here */ 135 #define XE_RXMODE_BITS \ 136 "\20\10TEST\05ADDRSIZE\04SHORTENABLE\03RESETENABLE\02MULTICAST\01NORMAL" 137 138 /* reset mode (address 6) */ 139 #define XE_RESET_MODE 0x80 /* reset mode */ 140 #define XE_RESET 6 141 142 #define XE_TDC_LSB 7 143 #define XE_ENADDR 8 144 #define XE_TDC_MSB 15 145 146 #define ENRX_EOP 0x80000000 /* end-of-packet flag */ 147 #define ENRX_BOP 0x40000000 /* beginning-of-packet flag */ 148 #define ENTX_EOP 0x80000000 /* end-of-packet flag */ 149 150 /* Size of register area to be mapped */ 151 #define XE_SIZE 16 152