1 /* $NetBSD: nextdmareg.h,v 1.8 2002/09/11 01:46:32 mycroft Exp $ */ 2 /* 3 * Copyright (c) 1998 Darrin B. Jewell 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Darrin B. Jewell 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* I think the chip can handle 64k per chain, but I don't 33 * know how much per segment for sure. We might try 34 * experimenting with this value. Can we cross page boundaries? 35 */ 36 #define MAX_DMASIZE 8192 37 38 /* from nextdev/dma.h */ 39 40 #if 0 41 #define DMA_BEGINALIGNMENT 4 /* initial buffer must be on long */ 42 #else 43 /* But to make cache handling easier, we put it on a cache line anyway. */ 44 #define DMA_BEGINALIGNMENT 16 45 #endif 46 #define DMA_ENDALIGNMENT 16 /* DMA must end on quad longword */ 47 48 #define DMA_ALIGN(type, addr) \ 49 ((type)(((unsigned)(addr)+DMA_BEGINALIGNMENT-1) \ 50 &~(DMA_BEGINALIGNMENT-1))) 51 52 #define DMA_ENDALIGN(type, addr) \ 53 ((type)(((unsigned)(addr)+DMA_ENDALIGNMENT-1) \ 54 &~(DMA_ENDALIGNMENT-1))) 55 56 #define DMA_BEGINALIGNED(addr) (((unsigned)(addr)&(DMA_BEGINALIGNMENT-1))==0) 57 #define DMA_ENDALIGNED(addr) (((unsigned)(addr)&(DMA_ENDALIGNMENT-1))==0) 58 59 #if 0 60 struct dma_dev { /* format of dma device registers */ 61 int dd_csr; /* control & status register */ 62 char dd_pad[0x3fec]; /* csr not contiguous with next */ 63 char *dd_saved_next; /* saved pointers for HW restart */ 64 char *dd_saved_limit; 65 char *dd_saved_start; 66 char *dd_saved_stop; 67 char *dd_next; /* next word to dma */ 68 char *dd_limit; /* dma complete when next == limit */ 69 char *dd_start; /* start of 2nd buf to dma */ 70 char *dd_stop; /* end of 2nd buf to dma */ 71 char dd_pad2[0x1f0]; 72 char *dd_next_initbuf; /* next register that inits dma buffering */ 73 }; 74 #endif 75 76 #define DD_CSR 0 77 #define DD_SAVED_NEXT (DD_CSR +sizeof(int) + 0x3fec) 78 #define DD_SAVED_LIMIT (DD_SAVED_NEXT +sizeof(char *)) 79 #define DD_SAVED_START (DD_SAVED_LIMIT +sizeof(char *)) 80 #define DD_SAVED_STOP (DD_SAVED_START +sizeof(char *)) 81 #define DD_NEXT (DD_SAVED_STOP +sizeof(char *)) 82 #define DD_LIMIT (DD_NEXT +sizeof(char *)) 83 #define DD_START (DD_LIMIT +sizeof(char *)) 84 #define DD_STOP (DD_START +sizeof(char *)) 85 #define DD_NEXT_INITBUF (DD_STOP +sizeof(char *) + 0x1f0) 86 87 #define DD_SIZE (DD_NEXT_INITBUF+sizeof(char *)) 88 /* 89 * bits in dd_csr 90 */ 91 /* read bits */ 92 #define DMACSR_ENABLE 0x01000000 /* enable dma transfer */ 93 #define DMACSR_SUPDATE 0x02000000 /* single update */ 94 #define DMACSR_READ 0x04000000 /* dma is ina read operation */ 95 #define DMACSR_COMPLETE 0x08000000 /* current dma has completed */ 96 #define DMACSR_BUSEXC 0x10000000 /* bus exception occurred */ 97 /* write bits */ 98 #define DMACSR_SETENABLE 0x00010000 /* set enable */ 99 #define DMACSR_SETSUPDATE 0x00020000 /* set single update */ 100 #define DMACSR_SETREAD 0x00040000 /* dma from dev to mem */ 101 #define DMACSR_SETWRITE 0x00000000 /* dma from mem to dev */ 102 #define DMACSR_CLRCOMPLETE 0x00080000 /* clear complete conditional */ 103 #define DMACSR_RESET 0x00100000 /* clr cmplt, sup, enable */ 104 #define DMACSR_INITBUF 0x00200000 /* initialize DMA buffers */ 105 #define DMACSR_INITBUFTURBO 0x00800000 106 107 #define DMACSR_BITS \ 108 "\20\35BUSEXC\34COMPLETE\33READ\32SUPDATE\31ENABLE\26INITBUF\25RESET\24CLRCOMPLETE\23SETREAD\22SETSUPDATE\21SETENABLE" 109