xref: /netbsd/sys/arch/next68k/include/bus_dma.h (revision bf9ec67e)
1 /* $NetBSD: bus_dma.h,v 1.9 2001/07/19 15:32:16 thorpej Exp $ */
2 
3 /*
4  * This file was extracted from from alpha/include/bus.h
5  * and should probably be resynced when needed.
6  * Darrin B. Jewell <dbj@netbsd.org> Sat Jul 31 06:11:33 UTC 1999
7  * original cvs id: NetBSD: bus.h,v 1.29 1999/06/18 04:49:24 cgd Exp
8  */
9 
10 
11 /*-
12  * Copyright (c) 1997, 1998, 2001 The NetBSD Foundation, Inc.
13  * All rights reserved.
14  *
15  * This code is derived from software contributed to The NetBSD Foundation
16  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
17  * NASA Ames Research Center.
18  *
19  * Redistribution and use in source and binary forms, with or without
20  * modification, are permitted provided that the following conditions
21  * are met:
22  * 1. Redistributions of source code must retain the above copyright
23  *    notice, this list of conditions and the following disclaimer.
24  * 2. Redistributions in binary form must reproduce the above copyright
25  *    notice, this list of conditions and the following disclaimer in the
26  *    documentation and/or other materials provided with the distribution.
27  * 3. All advertising materials mentioning features or use of this software
28  *    must display the following acknowledgement:
29  *	This product includes software developed by the NetBSD
30  *	Foundation, Inc. and its contributors.
31  * 4. Neither the name of The NetBSD Foundation nor the names of its
32  *    contributors may be used to endorse or promote products derived
33  *    from this software without specific prior written permission.
34  *
35  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
36  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
37  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
38  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
39  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
40  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
41  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
42  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
43  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
44  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
45  * POSSIBILITY OF SUCH DAMAGE.
46  */
47 
48 /*
49  * Copyright (c) 1996 Carnegie-Mellon University.
50  * All rights reserved.
51  *
52  * Author: Chris G. Demetriou
53  *
54  * Permission to use, copy, modify and distribute this software and
55  * its documentation is hereby granted, provided that both the copyright
56  * notice and this permission notice appear in all copies of the
57  * software, derivative works or modified versions, and any portions
58  * thereof, and that both notices appear in supporting documentation.
59  *
60  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
61  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
62  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
63  *
64  * Carnegie Mellon requests users of this software to return to
65  *
66  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
67  *  School of Computer Science
68  *  Carnegie Mellon University
69  *  Pittsburgh PA 15213-3890
70  *
71  * any improvements or extensions that they make and grant Carnegie the
72  * rights to redistribute these changes.
73  */
74 
75 #ifndef _NEXT68K_BUS_DMA_H_
76 #define	_NEXT68K_BUS_DMA_H_
77 
78 /*
79  * Bus DMA methods.
80  */
81 
82 /*
83  * Flags used in various bus DMA methods.
84  */
85 #define	BUS_DMA_WAITOK		0x000	/* safe to sleep (pseudo-flag) */
86 #define	BUS_DMA_NOWAIT		0x001	/* not safe to sleep */
87 #define	BUS_DMA_ALLOCNOW	0x002	/* perform resource allocation now */
88 #define	BUS_DMA_COHERENT	0x004	/* hint: map memory DMA coherent */
89 #define	BUS_DMA_STREAMING	0x008	/* hint: sequential, unidirectional */
90 #define	BUS_DMA_BUS1		0x010	/* placeholders for bus functions... */
91 #define	BUS_DMA_BUS2		0x020
92 #define	BUS_DMA_BUS3		0x040
93 #define	BUS_DMA_BUS4		0x080
94 #define	BUS_DMA_READ		0x100	/* mapping is device -> memory only */
95 #define	BUS_DMA_WRITE		0x200	/* mapping is memory -> device only */
96 
97 /* Forwards needed by prototypes below. */
98 struct mbuf;
99 struct uio;
100 
101 /*
102  * Operations performed by bus_dmamap_sync().
103  */
104 #define	BUS_DMASYNC_PREREAD	0x01	/* pre-read synchronization */
105 #define	BUS_DMASYNC_POSTREAD	0x02	/* post-read synchronization */
106 #define	BUS_DMASYNC_PREWRITE	0x04	/* pre-write synchronization */
107 #define	BUS_DMASYNC_POSTWRITE	0x08	/* post-write synchronization */
108 
109 typedef struct next68k_bus_dma_tag *bus_dma_tag_t;
110 typedef struct next68k_bus_dmamap *bus_dmamap_t;
111 
112 /*
113  *	bus_dma_segment_t
114  *
115  *	Describes a single contiguous DMA transaction.  Values
116  *	are suitable for programming into DMA registers.
117  */
118 struct next68k_bus_dma_segment {
119 	bus_addr_t	ds_addr;	/* DMA address */
120 	bus_size_t	ds_len;		/* length of transfer */
121 };
122 typedef struct next68k_bus_dma_segment	bus_dma_segment_t;
123 
124 /*
125  *	bus_dma_tag_t
126  *
127  *	A machine-dependent opaque type describing the implementation of
128  *	DMA for a given bus.
129  */
130 struct next68k_bus_dma_tag {
131 	void	*_cookie;		/* cookie used in the guts */
132 
133 	/*
134 	 * Some chipsets have a built-in boundary constraint, independent
135 	 * of what the device requests.  This allows that boundary to
136 	 * be specified.  If the device has a more restrictive constraint,
137 	 * the map will use that, otherwise this boundary will be used.
138 	 * This value is ignored if 0.
139 	 */
140 	bus_size_t _boundary;
141 
142 	/*
143 	 * DMA mapping methods.
144 	 */
145 	int	(*_dmamap_create) __P((bus_dma_tag_t, bus_size_t, int,
146 		    bus_size_t, bus_size_t, int, bus_dmamap_t *));
147 	void	(*_dmamap_destroy) __P((bus_dma_tag_t, bus_dmamap_t));
148 	int	(*_dmamap_load) __P((bus_dma_tag_t, bus_dmamap_t, void *,
149 		    bus_size_t, struct proc *, int));
150 	int	(*_dmamap_load_mbuf) __P((bus_dma_tag_t, bus_dmamap_t,
151 		    struct mbuf *, int));
152 	int	(*_dmamap_load_uio) __P((bus_dma_tag_t, bus_dmamap_t,
153 		    struct uio *, int));
154 	int	(*_dmamap_load_raw) __P((bus_dma_tag_t, bus_dmamap_t,
155 		    bus_dma_segment_t *, int, bus_size_t, int));
156 	void	(*_dmamap_unload) __P((bus_dma_tag_t, bus_dmamap_t));
157 	void	(*_dmamap_sync) __P((bus_dma_tag_t, bus_dmamap_t,
158 		    bus_addr_t, bus_size_t, int));
159 
160 	/*
161 	 * DMA memory utility functions.
162 	 */
163 	int	(*_dmamem_alloc) __P((bus_dma_tag_t, bus_size_t, bus_size_t,
164 		    bus_size_t, bus_dma_segment_t *, int, int *, int));
165 	void	(*_dmamem_free) __P((bus_dma_tag_t,
166 		    bus_dma_segment_t *, int));
167 	int	(*_dmamem_map) __P((bus_dma_tag_t, bus_dma_segment_t *,
168 		    int, size_t, caddr_t *, int));
169 	void	(*_dmamem_unmap) __P((bus_dma_tag_t, caddr_t, size_t));
170 	paddr_t	(*_dmamem_mmap) __P((bus_dma_tag_t, bus_dma_segment_t *,
171 		    int, off_t, int, int));
172 };
173 
174 #define	bus_dmamap_create(t, s, n, m, b, f, p)			\
175 	(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
176 #define	bus_dmamap_destroy(t, p)				\
177 	(*(t)->_dmamap_destroy)((t), (p))
178 #define	bus_dmamap_load(t, m, b, s, p, f)			\
179 	(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
180 #define	bus_dmamap_load_mbuf(t, m, b, f)			\
181 	(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
182 #define	bus_dmamap_load_uio(t, m, u, f)				\
183 	(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
184 #define	bus_dmamap_load_raw(t, m, sg, n, s, f)			\
185 	(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
186 #define	bus_dmamap_unload(t, p)					\
187 	(*(t)->_dmamap_unload)((t), (p))
188 #define	bus_dmamap_sync(t, p, o, l, ops)			\
189 	(*(t)->_dmamap_sync)((t), (p), (o), (l), (ops))
190 #define	bus_dmamem_alloc(t, s, a, b, sg, n, r, f)		\
191 	(*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
192 #define	bus_dmamem_free(t, sg, n)				\
193 	(*(t)->_dmamem_free)((t), (sg), (n))
194 #define	bus_dmamem_map(t, sg, n, s, k, f)			\
195 	(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
196 #define	bus_dmamem_unmap(t, k, s)				\
197 	(*(t)->_dmamem_unmap)((t), (k), (s))
198 #define	bus_dmamem_mmap(t, sg, n, o, p, f)			\
199 	(*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
200 
201 /*
202  *	bus_dmamap_t
203  *
204  *	Describes a DMA mapping.
205  */
206 struct next68k_bus_dmamap {
207 	/*
208 	 * PRIVATE MEMBERS: not for use by machine-independent code.
209 	 */
210 	bus_size_t	_dm_size;	/* largest DMA transfer mappable */
211 	int		_dm_segcnt;	/* number of segs this map can map */
212 	bus_size_t	_dm_maxsegsz;	/* largest possible segment */
213 	bus_size_t	_dm_boundary;	/* don't cross this */
214 	int		_dm_flags;	/* misc. flags */
215 
216 	/* Machine dependant fields: */
217 	bus_size_t  dm_xfer_len;			/* length of successful transfer */
218 
219 	/*
220 	 * PUBLIC MEMBERS: these are used by machine-independent code.
221 	 */
222 	bus_size_t	dm_mapsize;	/* size of the mapping */
223 	int		dm_nsegs;	/* # valid segments in mapping */
224 	bus_dma_segment_t dm_segs[1];	/* segments; variable length */
225 
226 };
227 
228 #ifdef _NEXT68K_BUS_DMA_PRIVATE
229 int	_bus_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, bus_size_t,
230 	    bus_size_t, int, bus_dmamap_t *));
231 void	_bus_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t));
232 
233 int	_bus_dmamap_load_direct __P((bus_dma_tag_t, bus_dmamap_t,
234 	    void *, bus_size_t, struct proc *, int));
235 int	_bus_dmamap_load_mbuf_direct __P((bus_dma_tag_t,
236 	    bus_dmamap_t, struct mbuf *, int));
237 int	_bus_dmamap_load_uio_direct __P((bus_dma_tag_t,
238 	    bus_dmamap_t, struct uio *, int));
239 int	_bus_dmamap_load_raw_direct __P((bus_dma_tag_t,
240 	    bus_dmamap_t, bus_dma_segment_t *, int, bus_size_t, int));
241 
242 void	_bus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t));
243 void	_bus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
244 	    bus_size_t, int));
245 
246 int	_bus_dmamem_alloc __P((bus_dma_tag_t tag, bus_size_t size,
247 	    bus_size_t alignment, bus_size_t boundary,
248 	    bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags));
249 void	_bus_dmamem_free __P((bus_dma_tag_t tag, bus_dma_segment_t *segs,
250 	    int nsegs));
251 int	_bus_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs,
252 	    int nsegs, size_t size, caddr_t *kvap, int flags));
253 void	_bus_dmamem_unmap __P((bus_dma_tag_t tag, caddr_t kva,
254 	    size_t size));
255 paddr_t	_bus_dmamem_mmap __P((bus_dma_tag_t tag, bus_dma_segment_t *segs,
256 	    int nsegs, off_t off, int prot, int flags));
257 #endif /* _NEXT68K_BUS_DMA_PRIVATE */
258 
259 #endif /* _NEXT68K_BUS_DMA_H_ */
260