1 /* $NetBSD: wdc_spd.c,v 1.1 2001/10/16 15:38:35 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 43 #define __read_1(a) \ 44 ({ \ 45 u_int32_t a_ = (a); \ 46 u_int8_t r = (*(__volatile__ u_int8_t *)a_); \ 47 \ 48 if (a_ == 0xb400004e) /* (wdc)STAT LED off */ \ 49 SPD_LED_OFF(); \ 50 \ 51 (r); \ 52 }) 53 #define __write_1(a, v) \ 54 { \ 55 u_int32_t a_ = (a); \ 56 (*(__volatile__ u_int8_t *)a_) = (v); \ 57 \ 58 if (a_ == 0xb400004e) /* (wdc)CMD LED on */ \ 59 SPD_LED_ON(); \ 60 } 61 #define _PLAYSTATION2_BUS_SPACE_PRIVATE 62 #include <machine/bus.h> 63 64 #include <dev/ata/atavar.h> 65 #include <dev/ic/wdcvar.h> 66 67 #include <playstation2/ee/eevar.h> 68 #include <playstation2/dev/spdvar.h> 69 #include <playstation2/dev/spdreg.h> 70 71 #define WDC_SPD_HDD_AUXREG_OFFSET 0x1c 72 73 struct wdc_spd_softc { 74 struct wdc_softc sc_wdcdev; 75 struct channel_softc *wdc_chanptr; 76 struct channel_softc wdc_channel; 77 void *sc_ih; 78 }; 79 80 #ifdef DEBUG 81 #define STATIC 82 #else 83 #define STATIC static 84 #endif 85 86 STATIC int wdc_spd_match(struct device *, struct cfdata *, void *); 87 STATIC void wdc_spd_attach(struct device *, struct device *, void *); 88 89 struct cfattach wdc_spd_ca = { 90 sizeof (struct wdc_spd_softc), wdc_spd_match, wdc_spd_attach 91 }; 92 93 extern struct cfdriver wdc_cd; 94 95 STATIC void __wdc_spd_enable(void); 96 STATIC void __wdc_spd_disable(void) __attribute__((__unused__)); 97 STATIC void __wdc_spd_bus_space(struct channel_softc *); 98 99 /* 100 * wdc register is 16 bit wide. 101 */ 102 #define VADDR(h, o) ((h) + ((o) << 1)) 103 _BUS_SPACE_READ(_wdc_spd, 1, 8) 104 _BUS_SPACE_READ(_wdc_spd, 2, 16) 105 _BUS_SPACE_READ_MULTI(_wdc_spd, 1, 8) 106 _BUS_SPACE_READ_MULTI(_wdc_spd, 2, 16) 107 _BUS_SPACE_READ_REGION(_wdc_spd, 1, 8) 108 _BUS_SPACE_READ_REGION(_wdc_spd, 2, 16) 109 _BUS_SPACE_WRITE(_wdc_spd, 1, 8) 110 _BUS_SPACE_WRITE(_wdc_spd, 2, 16) 111 _BUS_SPACE_WRITE_MULTI(_wdc_spd, 1, 8) 112 _BUS_SPACE_WRITE_MULTI(_wdc_spd, 2, 16) 113 _BUS_SPACE_WRITE_REGION(_wdc_spd, 1, 8) 114 _BUS_SPACE_WRITE_REGION(_wdc_spd, 2, 16) 115 _BUS_SPACE_SET_MULTI(_wdc_spd, 1, 8) 116 _BUS_SPACE_SET_MULTI(_wdc_spd, 2, 16) 117 _BUS_SPACE_SET_REGION(_wdc_spd, 1, 8) 118 _BUS_SPACE_SET_REGION(_wdc_spd, 2, 16) 119 _BUS_SPACE_COPY_REGION(_wdc_spd, 1, 8) 120 _BUS_SPACE_COPY_REGION(_wdc_spd, 2, 16) 121 #undef VADDR 122 123 STATIC const struct playstation2_bus_space _wdc_spd_space = { 124 pbs_map : _BUS_SPACE_NO_MAP, 125 pbs_unmap : _BUS_SPACE_NO_UNMAP, 126 pbs_subregion : _BUS_SPACE_NO_SUBREGION, 127 pbs_alloc : _BUS_SPACE_NO_ALLOC, 128 pbs_free : _BUS_SPACE_NO_FREE, 129 pbs_vaddr : _BUS_SPACE_NO_VADDR, 130 pbs_r_1 : _wdc_spd_read_1, 131 pbs_r_2 : _wdc_spd_read_2, 132 pbs_r_4 : _BUS_SPACE_NO_READ(4, 32), 133 pbs_r_8 : _BUS_SPACE_NO_READ(8, 64), 134 pbs_rm_1 : _wdc_spd_read_multi_1, 135 pbs_rm_2 : _wdc_spd_read_multi_2, 136 pbs_rm_4 : _BUS_SPACE_NO_READ_MULTI(4, 32), 137 pbs_rm_8 : _BUS_SPACE_NO_READ_MULTI(8, 64), 138 pbs_rr_1 : _wdc_spd_read_region_1, 139 pbs_rr_2 : _wdc_spd_read_region_2, 140 pbs_rr_4 : _BUS_SPACE_NO_READ_REGION(4, 32), 141 pbs_rr_8 : _BUS_SPACE_NO_READ_REGION(8, 64), 142 pbs_w_1 : _wdc_spd_write_1, 143 pbs_w_2 : _wdc_spd_write_2, 144 pbs_w_4 : _BUS_SPACE_NO_WRITE(4, 32), 145 pbs_w_8 : _BUS_SPACE_NO_WRITE(8, 64), 146 pbs_wm_1 : _wdc_spd_write_multi_1, 147 pbs_wm_2 : _wdc_spd_write_multi_2, 148 pbs_wm_4 : _BUS_SPACE_NO_WRITE_MULTI(4, 32), 149 pbs_wm_8 : _BUS_SPACE_NO_WRITE_MULTI(8, 64), 150 pbs_wr_1 : _wdc_spd_write_region_1, 151 pbs_wr_2 : _wdc_spd_write_region_2, 152 pbs_wr_4 : _BUS_SPACE_NO_WRITE_REGION(4, 32), 153 pbs_wr_8 : _BUS_SPACE_NO_WRITE_REGION(8, 64), 154 pbs_sm_1 : _wdc_spd_set_multi_1, 155 pbs_sm_2 : _wdc_spd_set_multi_2, 156 pbs_sm_4 : _BUS_SPACE_NO_SET_MULTI(4, 32), 157 pbs_sm_8 : _BUS_SPACE_NO_SET_MULTI(8, 64), 158 pbs_sr_1 : _wdc_spd_set_region_1, 159 pbs_sr_2 : _wdc_spd_set_region_2, 160 pbs_sr_4 : _BUS_SPACE_NO_SET_REGION(4, 32), 161 pbs_sr_8 : _BUS_SPACE_NO_SET_REGION(8, 64), 162 pbs_c_1 : _wdc_spd_copy_region_1, 163 pbs_c_2 : _wdc_spd_copy_region_2, 164 pbs_c_4 : _BUS_SPACE_NO_COPY_REGION(4, 32), 165 pbs_c_8 : _BUS_SPACE_NO_COPY_REGION(8, 64), 166 }; 167 168 int 169 wdc_spd_match(struct device *parent, struct cfdata *cf, void *aux) 170 { 171 struct spd_attach_args *spa = aux; 172 struct channel_softc ch; 173 int i, result; 174 175 if (spa->spa_slot != SPD_HDD) 176 return (0); 177 178 memset(&ch, 0, sizeof(ch)); 179 __wdc_spd_bus_space(&ch); 180 181 for (i = 0, result = 0; i < 8; i++) { /* 8 sec */ 182 if (result == 0) 183 result = wdcprobe(&ch); 184 delay(1000000); 185 } 186 187 return (result); 188 } 189 190 void 191 wdc_spd_attach(struct device *parent, struct device *self, void *aux) 192 { 193 struct spd_attach_args *spa = aux; 194 struct wdc_spd_softc *sc = (void *)self; 195 struct wdc_softc *wdc = &sc->sc_wdcdev; 196 struct channel_softc *ch = &sc->wdc_channel; 197 198 printf(": %s\n", spa->spa_product_name); 199 200 __wdc_spd_bus_space(ch); 201 202 wdc->cap = 203 WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA | WDC_CAPABILITY_DATA16; 204 wdc->PIO_cap = 0; 205 sc->wdc_chanptr = &sc->wdc_channel; 206 wdc->channels = &sc->wdc_chanptr; 207 wdc->nchannels = 1; 208 ch->channel = 0; 209 ch->wdc = &sc->sc_wdcdev; 210 ch->ch_queue = malloc(sizeof(struct channel_queue), M_DEVBUF, 211 M_NOWAIT); 212 213 if (ch->ch_queue == NULL) { 214 printf("%s: can't allocate memory for command queue", 215 wdc->sc_dev.dv_xname); 216 return; 217 } 218 219 spd_intr_establish(SPD_HDD, wdcintr, &sc->wdc_channel); 220 221 __wdc_spd_enable(); 222 223 wdcattach(&sc->wdc_channel); 224 } 225 226 void 227 __wdc_spd_bus_space(struct channel_softc *ch) 228 { 229 230 ch->cmd_iot = &_wdc_spd_space; 231 ch->cmd_ioh = SPD_HDD_IO_BASE; 232 ch->ctl_iot = &_wdc_spd_space; 233 ch->ctl_ioh = SPD_HDD_IO_BASE + WDC_SPD_HDD_AUXREG_OFFSET; 234 ch->data32iot = ch->cmd_iot; 235 ch->data32ioh = ch->cmd_ioh; 236 } 237 238 void 239 __wdc_spd_enable() 240 { 241 u_int16_t r; 242 243 r = _reg_read_2(SPD_INTR_ENABLE_REG16); 244 r |= SPD_INTR_HDD; 245 _reg_write_2(SPD_INTR_ENABLE_REG16, r); 246 } 247 248 void 249 __wdc_spd_disable() 250 { 251 u_int16_t r; 252 253 r = _reg_read_2(SPD_INTR_ENABLE_REG16); 254 r &= ~SPD_INTR_HDD; 255 _reg_write_2(SPD_INTR_ENABLE_REG16, r); 256 } 257