1 /* $NetBSD: dmacreg.h,v 1.1 2001/10/16 15:38:36 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 typedef u_int64_t dmatag_t; 40 41 #define DMAC_BLOCK_SIZE 16 42 #define DMAC_SLICE_SIZE 128 43 #define DMAC_TRANSFER_QWCMAX 0xffff 44 45 /* all register length are 32bit */ 46 #define DMAC_REGBASE MIPS_PHYS_TO_KSEG1(0x10008000) 47 #define DMAC_REGSIZE 0x00010000 48 49 /* 50 * DMAC common registers. 51 */ 52 #define D_CTRL_REG MIPS_PHYS_TO_KSEG1(0x1000e000) /* DMA control */ 53 #define D_STAT_REG MIPS_PHYS_TO_KSEG1(0x1000e010) /* interrupt status */ 54 #define D_PCR_REG MIPS_PHYS_TO_KSEG1(0x1000e020) /* priority control */ 55 #define D_SQWC_REG MIPS_PHYS_TO_KSEG1(0x1000e030) /* interleave size */ 56 #define D_RBOR_REG MIPS_PHYS_TO_KSEG1(0x1000e040) /* ring buffer addr */ 57 #define D_RBSR_REG MIPS_PHYS_TO_KSEG1(0x1000e050) /* ring buffer size */ 58 #define D_STADR_REG MIPS_PHYS_TO_KSEG1(0x1000e060) /* stall address */ 59 #define D_ENABLER_REG MIPS_PHYS_TO_KSEG1(0x1000f520) /* DMA enable (r) */ 60 #define D_ENABLEW_REG MIPS_PHYS_TO_KSEG1(0x1000f590) /* DMA enable (w) */ 61 62 /* 63 * Channel registers. (10ch) 64 */ 65 #define DMA_CH_VIF0 0 /* to (priority 0) */ 66 #define DMA_CH_VIF1 1 /* both */ 67 #define DMA_CH_GIF 2 /* to */ 68 #define DMA_CH_FROMIPU 3 69 #define DMA_CH_TOIPU 4 70 #define DMA_CH_SIF0 5 /* from */ 71 #define DMA_CH_SIF1 6 /* to */ 72 #define DMA_CH_SIF2 7 /* both (priority 1) */ 73 #define DMA_CH_FROMSPR 8 /* burst channel */ 74 #define DMA_CH_TOSPR 9 /* burst channel */ 75 #define DMA_CH_VALID(x) (((x) >= 0) && ((x) <= 9)) 76 77 #define D_CHCR_OFS 0x00 78 #define D_MADR_OFS 0x10 79 #define D_QWC_OFS 0x20 80 #define D_TADR_OFS 0x30 81 #define D_ASR0_OFS 0x40 82 #define D_ASR1_OFS 0x50 83 #define D_SADR_OFS 0x80 84 85 #define D0_REGBASE MIPS_PHYS_TO_KSEG1(0x10008000) 86 #define D1_REGBASE MIPS_PHYS_TO_KSEG1(0x10009000) 87 #define D2_REGBASE MIPS_PHYS_TO_KSEG1(0x1000a000) 88 #define D3_REGBASE MIPS_PHYS_TO_KSEG1(0x1000b000) 89 #define D4_REGBASE MIPS_PHYS_TO_KSEG1(0x1000b400) 90 #define D5_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c000) 91 #define D6_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c400) 92 #define D7_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c800) 93 #define D8_REGBASE MIPS_PHYS_TO_KSEG1(0x1000d000) 94 #define D9_REGBASE MIPS_PHYS_TO_KSEG1(0x1000d400) 95 96 #define D_CHCR_REG(base) (base) 97 #define D_MADR_REG(base) (base + D_MADR_OFS) 98 #define D_QWC_REG(base) (base + D_QWC_OFS) 99 #define D_TADR_REG(base) (base + D_TADR_OFS) 100 #define D_ASR0_REG(base) (base + D_ASR0_OFS) 101 #define D_ASR1_REG(base) (base + D_ASR1_OFS) 102 #define D_SADR_REG(base) (base + D_SADR_OFS) 103 104 #define D0_CHCR_REG MIPS_PHYS_TO_KSEG1(0x10008000) 105 #define D0_MADR_REG MIPS_PHYS_TO_KSEG1(0x10008010) 106 #define D0_QWC_REG MIPS_PHYS_TO_KSEG1(0x10008020) 107 #define D0_TADR_REG MIPS_PHYS_TO_KSEG1(0x10008030) 108 #define D0_ASR0_REG MIPS_PHYS_TO_KSEG1(0x10008040) 109 #define D0_ASR1_REG MIPS_PHYS_TO_KSEG1(0x10008050) 110 111 #define D1_CHCR_REG MIPS_PHYS_TO_KSEG1(0x10009000) 112 #define D1_MADR_REG MIPS_PHYS_TO_KSEG1(0x10009010) 113 #define D1_QWC_REG MIPS_PHYS_TO_KSEG1(0x10009020) 114 #define D1_TADR_REG MIPS_PHYS_TO_KSEG1(0x10009030) 115 #define D1_ASR0_REG MIPS_PHYS_TO_KSEG1(0x10009040) 116 #define D1_ASR1_REG MIPS_PHYS_TO_KSEG1(0x10009050) 117 118 #define D2_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000a000) 119 #define D2_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000a010) 120 #define D2_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000a020) 121 #define D2_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000a030) 122 #define D2_ASR0_REG MIPS_PHYS_TO_KSEG1(0x1000a040) 123 #define D2_ASR1_REG MIPS_PHYS_TO_KSEG1(0x1000a050) 124 125 #define D3_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000b000) 126 #define D3_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000b010) 127 #define D3_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000b020) 128 129 #define D4_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000b400) 130 #define D4_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000b410) 131 #define D4_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000b420) 132 #define D4_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000b430) 133 134 #define D5_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c000) 135 #define D5_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c010) 136 #define D5_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c020) 137 138 #define D6_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c400) 139 #define D6_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c410) 140 #define D6_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c420) 141 #define D6_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000c430) 142 143 #define D7_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c800) 144 #define D7_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c810) 145 #define D7_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c820) 146 147 #define D8_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000d000) 148 #define D8_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000d010) 149 #define D8_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000d020) 150 #define D8_SADR_REG MIPS_PHYS_TO_KSEG1(0x1000d080) 151 152 #define D9_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000d400) 153 #define D9_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000d410) 154 #define D9_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000d420) 155 #define D9_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000d430) 156 #define D9_SADR_REG MIPS_PHYS_TO_KSEG1(0x1000d480) 157 158 /* 159 * DMA control 160 */ 161 #define D_CTRL_DMAE 0x00000001 /* all DMA enable/disable */ 162 #define D_CTRL_RELE 0x00000002 /* Cycle stealing on/off */ 163 /* Memory FIFO drain control */ 164 #define D_CTRL_MFD_MASK 0x3 165 #define D_CTRL_MFD_SHIFT 2 166 #define D_CTRL_MFD(x) \ 167 (((x) >> D_CTRL_MFD_SHIFT) & D_CTRL_MFD_MASK) 168 #define D_CTRL_MFD_CLR(x) \ 169 ((x) & ~(D_CTRL_MFD_MASK << D_CTRL_MFD_SHIFT)) 170 #define D_CTRL_MFD_SET(x, val) \ 171 ((x) | (((val) << D_CTRL_MFD_SHIFT) & \ 172 (D_CTRL_MFD_MASK << D_CTRL_MFD_SHIFT))) 173 #define D_CTRL_MFD_DISABLE 0 174 #define D_CTRL_MFD_VIF1 2 175 #define D_CTRL_MFD_GIF 3 176 177 /* Stall control source channel */ 178 #define D_CTRL_STS_MASK 0x3 179 #define D_CTRL_STS_SHIFT 4 180 #define D_CTRL_STS(x) \ 181 (((x) >> D_CTRL_STS_SHIFT) & D_CTRL_STS_MASK) 182 #define D_CTRL_STS_CLR(x) \ 183 ((x) & ~(D_CTRL_STS_MASK << D_CTRL_STS_SHIFT)) 184 #define D_CTRL_STS_SET(x, val) \ 185 ((x) | (((val) << D_CTRL_STS_SHIFT) & \ 186 (D_CTRL_STS_MASK << D_CTRL_STS_SHIFT))) 187 #define D_CTRL_STS_NONE 0 188 #define D_CTRL_STS_SIF0 1 189 #define D_CTRL_STS_FROMSPR 2 190 #define D_CTRL_STS_FROMIPU 3 191 192 /* Stall control drain channel */ 193 #define D_CTRL_STD_MASK 0x3 194 #define D_CTRL_STD_SHIFT 6 195 #define D_CTRL_STD(x) \ 196 (((x) >> D_CTRL_STD_SHIFT) & D_CTRL_STD_MASK) 197 #define D_CTRL_STD_CLR(x) \ 198 ((x) & ~(D_CTRL_STD_MASK << D_CTRL_STD_SHIFT)) 199 #define D_CTRL_STD_SET(x, val) \ 200 ((x) | (((val) << D_CTRL_STD_SHIFT) & \ 201 (D_CTRL_STD_MASK << D_CTRL_STD_SHIFT))) 202 #define D_CTRL_STD_NONE 0 203 #define D_CTRL_STD_VIF1 1 204 #define D_CTRL_STD_GIF 2 205 #define D_CTRL_STD_SIF1 3 206 207 /* 208 * Release cycle 209 * for burst channel Cycle steanling on mode only. 210 */ 211 #define D_CTRL_RCYC_MASK 0x7 212 #define D_CTRL_RCYC_SHIFT 8 213 #define D_CTRL_RCYC(x) \ 214 (((x) >> D_CTRL_RCYC_SHIFT) & D_CTRL_RCYC_MASK) 215 #define D_CTRL_RCYC_CLR(x) \ 216 ((x) & ~(D_CTRL_RCYC_MASK << D_CTRL_RCYC_SHIFT)) 217 #define D_CTRL_RCYC_SET(x, val) \ 218 ((x) | (((val) << D_CTRL_RCYC_SHIFT) & \ 219 (D_CTRL_RCYC_MASK << D_CTRL_RCYC_SHIFT))) 220 #define D_CTRL_RCYC_CYCLE(x) (8 << (x)) 221 222 /* 223 * Interrupt status register (write clear/invert) 224 * DMAC interrupt line connected to MIPS HwINT1 225 */ 226 /* MFIFO empty interrupt enable */ 227 #define D_STAT_MEIM 0x40000000 228 /* DMA stall interrupt enable */ 229 #define D_STAT_SIM 0x20000000 230 /* Channel interrupt enable */ 231 #define D_STAT_CIM_MASK 0x3ff 232 #define D_STAT_CIM_SHIFT 16 233 #define D_STAT_CIM(x) (((x) >> D_STAT_CIM_SHIFT) & D_STAT_CIM_MASK) 234 #define D_STAT_CIM_BIT(x) ((1 << (x)) << D_STAT_CIM_SHIFT) 235 #define D_STAT_CIM9 0x02000000 236 #define D_STAT_CIM8 0x01000000 237 #define D_STAT_CIM7 0x00800000 238 #define D_STAT_CIM6 0x00400000 239 #define D_STAT_CIM5 0x00200000 240 #define D_STAT_CIM4 0x00100000 241 #define D_STAT_CIM3 0x00080000 242 #define D_STAT_CIM2 0x00040000 243 #define D_STAT_CIM1 0x00020000 244 #define D_STAT_CIM0 0x00010000 245 /* BUSERR interrupt status */ 246 #define D_STAT_BEIS 0x00008000 247 /* MFIFO empty interrupt status */ 248 #define D_STAT_MEIS 0x00004000 249 /* DMA stall interrupt status */ 250 #define D_STAT_SIS 0x00002000 251 /* Channel interrupt status */ 252 #define D_STAT_CIS_MASK 0x3ff 253 #define D_STAT_CIS_SHIFT 0 254 #define D_STAT_CIS_BIT(x) (1 << (x)) 255 #define D_STAT_CIS9 0x00000200 256 #define D_STAT_CIS8 0x00000100 257 #define D_STAT_CIS7 0x00000080 258 #define D_STAT_CIS6 0x00000040 259 #define D_STAT_CIS5 0x00000020 260 #define D_STAT_CIS4 0x00000010 261 #define D_STAT_CIS3 0x00000008 262 #define D_STAT_CIS2 0x00000004 263 #define D_STAT_CIS1 0x00000002 264 #define D_STAT_CIS0 0x00000001 265 266 /* 267 * Priority control register. 268 */ 269 /* Priority control enable */ 270 #define D_PCR_PCE 0x80000000 271 /* Channel DMA enable (packet priority control enable) */ 272 #define D_PCR_CDE_MASK 0x3ff 273 #define D_PCR_CDE_SHIFT 16 274 #define D_PCR_CDE(x) \ 275 (((x) >> D_PCR_CDE_SHIFT) & D_PCR_CDE_MASK) 276 #define D_PCR_CDE_CLR(x) \ 277 ((x) & ~(D_PCR_CDE_MASK << D_PCR_CDE_SHIFT)) 278 #define D_PCR_CDE_SET(x, val) \ 279 ((x) | (((val) << D_PCR_CDE_SHIFT) & \ 280 (D_PCR_CDE_MASK << D_PCR_CDE_SHIFT))) 281 #define D_PCR_CDE9 0x02000000 282 #define D_PCR_CDE8 0x01000000 283 #define D_PCR_CDE7 0x00800000 284 #define D_PCR_CDE6 0x00400000 285 #define D_PCR_CDE5 0x00200000 286 #define D_PCR_CDE4 0x00100000 287 #define D_PCR_CDE3 0x00080000 288 #define D_PCR_CDE2 0x00040000 289 #define D_PCR_CDE1 0x00020000 290 #define D_PCR_CDE0 0x00010000 291 /* COP control (interrupt status connect to CPCOND[0] or not) */ 292 #define D_PCR_CPC_MASK 0x3ff 293 #define D_PCR_CPC_SHIFT 0 294 #define D_PCR_CPC(x) ((x) & D_PCR_CPC_MASK) 295 #define D_PCR_CPC_CLR(x) ((x) & ~D_PCR_CPC_MASK) 296 #define D_PCR_CPC_SET(x, val) ((x) | ((val) & D_PCR_CPC_MASK)) 297 #define D_PCR_CPC_BIT(x) (1 << (x)) 298 #define D_PCR_CPC9 0x00000200 299 #define D_PCR_CPC8 0x00000100 300 #define D_PCR_CPC7 0x00000080 301 #define D_PCR_CPC6 0x00000040 302 #define D_PCR_CPC5 0x00000020 303 #define D_PCR_CPC4 0x00000010 304 #define D_PCR_CPC3 0x00000008 305 #define D_PCR_CPC2 0x00000004 306 #define D_PCR_CPC1 0x00000002 307 #define D_PCR_CPC0 0x00000001 308 309 /* 310 * Interleave size register 311 */ 312 /* Transfer quadword counter */ 313 #define D_SQWC_TQWC_MASK 0xff 314 #define D_SQWC_TQWC_SHIFT 16 315 #define D_SQWC_TQWC(x) \ 316 (((x) >> D_SQWC_TQWC_SHIFT) & D_SQWC_TQWC_MASK) 317 #define D_SQWC_TQWC_CLR(x) \ 318 ((x) & ~(D_SQWC_TQWC_MASK << D_SQWC_TQWC_SHIFT)) 319 #define D_SQWC_TQWC_SET(x, val) \ 320 ((x) | (((val) << D_SQWC_TQWC_SHIFT) & \ 321 (D_SQWC_TQWC_MASK << D_SQWC_TQWC_SHIFT))) 322 /* Skip quadword counter */ 323 #define D_SQWC_SQWC_MASK 0xff 324 #define D_SQWC_SQWC_SHIFT 0 325 #define D_SQWC_SQWC(x) \ 326 (((x) >> D_SQWC_SQWC_SHIFT) & D_SQWC_SQWC_MASK) 327 #define D_SQWC_SQWC_CLR(x) \ 328 ((x) & ~(D_SQWC_SQWC_MASK << D_SQWC_SQWC_SHIFT)) 329 #define D_SQWC_SQWC_SET(x, val) \ 330 ((x) | (((val) << D_SQWC_SQWC_SHIFT) & \ 331 (D_SQWC_SQWC_MASK << D_SQWC_SQWC_SHIFT))) 332 333 /* 334 * Ring buffer address register 335 * 16byte alignment address [30:4] 336 */ 337 338 /* 339 * Ring buffer size register 340 * must be 2 ** n qword. [30:4] 341 */ 342 343 /* 344 * Stall address register 345 * [30:0] (qword alignment) 346 */ 347 348 /* 349 * DMA suspend register 350 */ 351 #define D_ENABLE_SUSPEND 0x00010000 352 353 354 /* 355 * Channel specific register. 356 */ 357 358 /* CHANNEL CONTROL REGISTER */ 359 /* upper 16bit of DMA tag last read. */ 360 #define D_CHCR_TAG_MASK 0xff 361 #define D_CHCR_TAG_SHIFT 16 362 #define D_CHCR_TAG(x) \ 363 (((x) >> D_CHCR_TAG_SHIFT) & D_CHCR_TAG_MASK) 364 #define D_CHCR_TAG_CLR(x) \ 365 ((x) & ~(D_CHCR_TAG_MASK << D_CHCR_TAG_SHIFT)) 366 #define D_CHCR_TAG_SET(x, val) \ 367 ((x) | (((val) << D_CHCR_TAG_SHIFT) & \ 368 (D_CHCR_TAG_MASK << D_CHCR_TAG_SHIFT))) 369 /* DMA start */ 370 #define D_CHCR_STR 0x00000100 371 /* Tag interrupt enable (IRQ bit of DMAtag) */ 372 #define D_CHCR_TIE 0x00000080 373 /* Tag transfer enable (Source chain mode only) */ 374 #define D_CHCR_TTE 0x00000040 375 /* Address stack pointer */ 376 #define D_CHCR_ASP_MASK 0x3 377 #define D_CHCR_ASP_SHIFT 4 378 #define D_CHCR_ASP(x) \ 379 (((x) >> D_CHCR_ASP_SHIFT) & D_CHCR_ASP_MASK) 380 #define D_CHCR_ASP_CLR(x) \ 381 ((x) & ~(D_CHCR_ASP_MASK << D_CHCR_ASP_SHIFT)) 382 #define D_CHCR_ASP_SET(x, val) \ 383 ((x) | (((val) << D_CHCR_ASP_SHIFT) & \ 384 (D_CHCR_ASP_MASK << D_CHCR_ASP_SHIFT))) 385 #define D_CHCR_ASP_PUSHED_NONE 0 386 #define D_CHCR_ASP_PUSHED_1 1 387 #define D_CHCR_ASP_PUSHED_2 2 388 /* Logical transfer mode */ 389 #define D_CHCR_MOD_MASK 0x3 390 #define D_CHCR_MOD_SHIFT 2 391 #define D_CHCR_MOD(x) \ 392 (((x) >> D_CHCR_MOD_SHIFT) & D_CHCR_MOD_MASK) 393 #define D_CHCR_MOD_CLR(x) \ 394 ((x) & ~(D_CHCR_MOD_MASK << D_CHCR_MOD_SHIFT)) 395 #define D_CHCR_MOD_SET(x, val) \ 396 ((x) | (((val) << D_CHCR_MOD_SHIFT) & \ 397 (D_CHCR_MOD_MASK << D_CHCR_MOD_SHIFT))) 398 #define D_CHCR_MOD_NORMAL 0 399 #define D_CHCR_MOD_CHAIN 1 400 #define D_CHCR_MOD_INTERLEAVE 2 401 /* 402 * DMA transfer direction (1 ... from Memory, 0 ... to Memory) 403 * (VIF1, SIF2 only. i.e. `both'-direction channel requires this) 404 */ 405 #define D_CHCR_DIR 0x00000001 406 407 /* 408 * TRANSFER ADDRESS REGISTER (D-RAM address) 409 * 16 byte alignment. In FROMSPR, TOSPR channel, D_MADR_SPR always 0 410 */ 411 #define D_MADR_SPR 0x80000000 412 413 /* 414 * TAG ADDRESS REGISTER (next tag address) 415 * 16 byte alignment. 416 */ 417 #define D_TADR_SPR 0x80000000 418 419 /* 420 * TAG ADDRESS STACK REGISTER (2 stage) 421 * 16 byte alignment. 422 */ 423 #define D_ASR_SPR 0x80000000 424 425 /* 426 * SPR TRANSFER ADDRESS REGISTER (SPR address) 427 * 16 byte alignment. FROMSPR, TOSPR only. 428 */ 429 #define D_SADR_MASK 0x3fff 430 #define D_SADR_SHIFT 0 431 #define D_SADR(x) \ 432 ((u_int32_t)(x) & D_SADR_MASK) 433 /* 434 * TRANSFER SIZE REGISTER 435 * min 16 byte to max 1 Mbyte. 436 */ 437 #define D_QWC_MASK 0xffff 438 #define D_QWC_SHIFT 0 439 #define D_QWC(x) (((x) >> D_QWC_SHIFT) & D_QWC_MASK) 440 #define D_QWC_CLR(x) ((x) & ~(D_QWC_MASK << D_QWC_SHIFT)) 441 #define D_QWC_SET(x, val) \ 442 ((x) | (((val) << D_QWC_SHIFT) & D_QWC_MASK << D_QWC_SHIFT)) 443 444 /* 445 * Source/Destination Chain Tag definition. 446 * SC ... VIF0, VIF1, GIF, toIPU, SIF1, toSPR 447 * DC ... SIF0, fromSPR 448 */ 449 /* 450 * DMA address 451 * At least, 16byte align. 452 * but 64byte align is recommended. because EE D-cash line size is 64byte. 453 * To gain maximum DMA speed, use 128 byte align. 454 */ 455 #define DMATAG_ADDR_MASK 0xffffffff 456 #define DMATAG_ADDR_SHIFT 32 457 #define DMATAG_ADDR(x) \ 458 ((u_int32_t)(((x) >> DMATAG_ADDR_SHIFT) & DMATAG_ADDR_MASK)) 459 #define DMATAG_ADDR_SET(x, val) \ 460 ((dmatag_t)(x) | (((dmatag_t)(val)) << DMATAG_ADDR_SHIFT)) 461 462 #define DMATAG_ADDR32_INVALID(x) ((x) & 0xf) /* 16byte alignment */ 463 464 /* 465 * DMA controller command 466 */ 467 #define DMATAG_CMD_MASK 0xffffffff 468 #define DMATAG_CMD_SHIFT 0 469 #define DMATAG_CMD(x) \ 470 ((u_int32_t)((x) & DMATAG_CMD_MASK)) 471 472 #define DMATAG_CMD_IRQ 0x80000000 473 474 #define DMATAG_CMD_ID_MASK 0x7 475 #define DMATAG_CMD_ID_SHIFT 28 476 #define DMATAG_CMD_ID(x) \ 477 (((x) >> DMATAG_CMD_ID_SHIFT) & DMATAG_CMD_ID_MASK) 478 #define DMATAG_CMD_ID_CLR(x) \ 479 ((x) & ~(DMATAG_CMD_ID_MASK << DMATAG_CMD_ID_SHIFT)) 480 #define DMATAG_CMD_ID_SET(x, val) \ 481 ((x) | (((val) << DMATAG_CMD_ID_SHIFT) & \ 482 (DMATAG_CMD_ID_MASK << DMATAG_CMD_ID_SHIFT))) 483 #define DMATAG_CMD_SCID_REFE 0 484 #define DMATAG_CMD_SCID_CNT 1 485 #define DMATAG_CMD_SCID_NEXT 2 486 #define DMATAG_CMD_SCID_REF 3 487 #define DMATAG_CMD_SCID_REFS 4 /* VIF1, GIF, SIF1 only */ 488 #define DMATAG_CMD_SCID_CALL 5 /* VIF0, VIF1, GIF only */ 489 #define DMATAG_CMD_SCID_RET 6 /* VIF0, VIF1, GIF only */ 490 #define DMATAG_CMD_SCID_END 7 491 492 #define DMATAG_CMD_DCID_CNTS 0 /* SIF0, fromSPR only */ 493 #define DMATAG_CMD_DCID_CNT 1 494 #define DMATAG_CMD_DCID_END 7 495 496 #define DMATAG_CMD_PCE_MASK 0x3 497 #define DMATAG_CMD_PCE_SHIFT 26 498 #define DMATAG_CMD_PCE(x) \ 499 (((x) >> DMATAG_CMD_PCE_SHIFT) & DMATAG_CMD_PCE_MASK) 500 #define DMATAG_CMD_PCE_CLR(x) \ 501 ((x) & ~(DMATAG_CMD_PCE_MASK << DMATAG_CMD_PCE_SHIFT)) 502 #define DMATAG_CMD_PCE_SET(x, val) \ 503 ((x) | (((val) << DMATAG_CMD_PCE_SHIFT) & \ 504 (DMATAG_CMD_PCE_MASK << DMATAG_CMD_PCE_SHIFT))) 505 #define DMATAG_CMD_PCE_NONE 0 506 #define DMATAG_CMD_PCE_DISABLE 2 507 #define DMATAG_CMD_PCE_ENABLE 3 508 509 #define DMATAG_CMD_QWC_MASK 0xffff 510 #define DMATAG_CMD_QWC_SHIFT 0 511 #define DMATAG_CMD_QWC(x) \ 512 (((x) >> DMATAG_CMD_QWC_SHIFT) & DMATAG_CMD_QWC_MASK) 513 #define DMATAG_CMD_QWC_CLR(x) \ 514 ((x) & ~(DMATAG_CMD_QWC_MASK << DMATAG_CMD_QWC_SHIFT)) 515 #define DMATAG_CMD_QWC_SET(x, val) \ 516 ((x) | (((val) << DMATAG_CMD_QWC_SHIFT) & \ 517 (DMATAG_CMD_QWC_MASK << DMATAG_CMD_QWC_SHIFT))) 518