1 /* $NetBSD: gsreg.h,v 1.1 2001/10/16 15:38:38 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #define GS_S_PMODE_REG MIPS_PHYS_TO_KSEG1(0x12000000) 40 #define GS_S_SMODE1_REG MIPS_PHYS_TO_KSEG1(0x12000010) 41 #define GS_S_SMODE2_REG MIPS_PHYS_TO_KSEG1(0x12000020) 42 #define GS_S_SRFSH_REG MIPS_PHYS_TO_KSEG1(0x12000030) 43 #define GS_S_SYNCH1_REG MIPS_PHYS_TO_KSEG1(0x12000040) 44 #define GS_S_SYNCH2_REG MIPS_PHYS_TO_KSEG1(0x12000050) 45 #define GS_S_SYNCV_REG MIPS_PHYS_TO_KSEG1(0x12000060) 46 #define GS_S_DISPFB1_REG MIPS_PHYS_TO_KSEG1(0x12000070) 47 #define GS_S_DISPLAY1_REG MIPS_PHYS_TO_KSEG1(0x12000080) 48 #define GS_S_DISPFB2_REG MIPS_PHYS_TO_KSEG1(0x12000090) 49 #define GS_S_DISPLAY2_REG MIPS_PHYS_TO_KSEG1(0x120000a0) 50 #define GS_S_EXTBUF_REG MIPS_PHYS_TO_KSEG1(0x120000b0) 51 #define GS_S_EXTDATA_REG MIPS_PHYS_TO_KSEG1(0x120000c0) 52 #define GS_S_EXTWRITE_REG MIPS_PHYS_TO_KSEG1(0x120000d0) 53 #define GS_S_BGCOLOR_REG MIPS_PHYS_TO_KSEG1(0x120000e0) 54 #define GS_S_CSR_REG MIPS_PHYS_TO_KSEG1(0x12001000) 55 #define GS_S_IMR_REG MIPS_PHYS_TO_KSEG1(0x12001010) 56 #define GS_S_BUSDIR_REG MIPS_PHYS_TO_KSEG1(0x12001040) 57 #define GS_S_SIGLBLID_REG MIPS_PHYS_TO_KSEG1(0x12001080) 58 59 #define SMODE1(vhp, vcksel, slck2, nvck, clksel, pevs, pehs, pvs, phs, \ 60 gcont, spml, pck2, xpck, sint, prst, ex, cmod, slck, t1248, lc, rc) \ 61 (((u_int64_t)(vhp) << 36) | \ 62 ((u_int64_t)(vcksel) << 34) | \ 63 ((u_int64_t)(slck2) << 33) | \ 64 ((u_int64_t)(nvck) << 32) | \ 65 ((u_int64_t)(clksel) << 30) | \ 66 ((u_int64_t)(pevs) << 29) | \ 67 ((u_int64_t)(pehs) << 28) | \ 68 ((u_int64_t)(pvs) << 27) | \ 69 ((u_int64_t)(phs) << 26) | \ 70 ((u_int64_t)(gcont) << 25) | \ 71 ((u_int64_t)(spml) << 21) | \ 72 ((u_int64_t)(pck2) << 19) | \ 73 ((u_int64_t)(xpck) << 18) | \ 74 ((u_int64_t)(sint) << 17) | \ 75 ((u_int64_t)(prst) << 16) | \ 76 ((u_int64_t)(ex) << 15) | \ 77 ((u_int64_t)(cmod) << 13) | \ 78 ((u_int64_t)(slck) << 12) | \ 79 ((u_int64_t)(t1248) << 10) | \ 80 ((u_int64_t)(lc) << 3) | \ 81 ((u_int64_t)(rc) << 0)) 82 83 #define SMODE2(dpms, ffmd, inter) \ 84 (((u_int64_t)(dpms) << 2) | \ 85 ((u_int64_t)(ffmd) << 1) | \ 86 ((u_int64_t)(inter) << 0)) 87 88 #define SRFSH(x) (x) 89 90 #define SYNCH1(hs, hsvs, hseq, hbp, hfp) \ 91 (((u_int64_t)(hs) << 43) | \ 92 ((u_int64_t)(hsvs) << 32) | \ 93 ((u_int64_t)(hseq) << 22) | \ 94 ((u_int64_t)(hbp) << 11) | \ 95 ((u_int64_t)(hfp) << 0)) 96 97 #define SYNCH2(hb, hf) \ 98 (((u_int64_t)(hb) << 11) | \ 99 ((u_int64_t)(hf) << 0)) 100 101 #define SYNCV(vs, vdp, vbpe, vbp, vfpe, vfp) \ 102 (((u_int64_t)(vs) << 53) | \ 103 ((u_int64_t)(vdp) << 42) | \ 104 ((u_int64_t)(vbpe) << 32) | \ 105 ((u_int64_t)(vbp) << 20) | \ 106 ((u_int64_t)(vfpe) << 10) | \ 107 ((u_int64_t)(vfp) << 0)) 108 109 #define DISPLAY(dh, dw, magv, magh, dy, dx) \ 110 (((u_int64_t)(dh) << 44) | \ 111 ((u_int64_t)(dw) << 32) | \ 112 ((u_int64_t)(magv) << 27) | \ 113 ((u_int64_t)(magh) << 23) | \ 114 ((u_int64_t)(dy) << 12) | \ 115 ((u_int64_t)(dx) << 0)) 116