1 /* $NetBSD: bus_dma.c,v 1.33 2001/11/14 18:15:33 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include "opt_cputype.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/mbuf.h> 45 #include <sys/proc.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #define _PMAX_BUS_DMA_PRIVATE 50 #include <machine/bus.h> 51 52 #include <mips/cache.h> 53 54 static int _bus_dmamap_load_buffer __P((bus_dmamap_t, 55 void *, bus_size_t, struct proc *, int, vaddr_t *, 56 int *, int)); 57 58 paddr_t kvtophys __P((vaddr_t)); /* XXX */ 59 60 /* 61 * The default DMA tag for all busses on the DECstation. 62 */ 63 struct pmax_bus_dma_tag pmax_default_bus_dma_tag = { 64 _bus_dmamap_create, 65 _bus_dmamap_destroy, 66 _bus_dmamap_load, 67 _bus_dmamap_load_mbuf, 68 _bus_dmamap_load_uio, 69 _bus_dmamap_load_raw, 70 _bus_dmamap_unload, 71 NULL, 72 _bus_dmamem_alloc, 73 _bus_dmamem_free, 74 _bus_dmamem_map, 75 _bus_dmamem_unmap, 76 _bus_dmamem_mmap, 77 }; 78 79 void 80 pmax_bus_dma_init(void) 81 { 82 #ifdef MIPS1 83 if (CPUISMIPS3 == 0) 84 pmax_default_bus_dma_tag._dmamap_sync = _bus_dmamap_sync_r3k; 85 #endif 86 #ifdef MIPS3 87 if (CPUISMIPS3) 88 pmax_default_bus_dma_tag._dmamap_sync = _bus_dmamap_sync_r4k; 89 #endif 90 } 91 92 /* 93 * Common function for DMA map creation. May be called by bus-specific 94 * DMA map creation functions. 95 */ 96 int 97 _bus_dmamap_create(t, size, nsegments, maxsegsz, boundary, flags, dmamp) 98 bus_dma_tag_t t; 99 bus_size_t size; 100 int nsegments; 101 bus_size_t maxsegsz; 102 bus_size_t boundary; 103 int flags; 104 bus_dmamap_t *dmamp; 105 { 106 struct pmax_bus_dmamap *map; 107 void *mapstore; 108 size_t mapsize; 109 110 /* 111 * Allcoate and initialize the DMA map. The end of the map 112 * is a variable-sized array of segments, so we allocate enough 113 * room for them in one shot. 114 * 115 * Note we don't preserve the WAITOK or NOWAIT flags. Preservation 116 * of ALLOCNOW notifes others that we've reserved these resources, 117 * and they are not to be freed. 118 * 119 * The bus_dmamap_t includes one bus_dma_segment_t, hence 120 * the (nsegments - 1). 121 */ 122 mapsize = sizeof(struct pmax_bus_dmamap) + 123 (sizeof(bus_dma_segment_t) * (nsegments - 1)); 124 if ((mapstore = malloc(mapsize, M_DMAMAP, 125 (flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK)) == NULL) 126 return (ENOMEM); 127 128 memset(mapstore, 0, mapsize); 129 map = (struct pmax_bus_dmamap *)mapstore; 130 map->_dm_size = size; 131 map->_dm_segcnt = nsegments; 132 map->_dm_maxsegsz = maxsegsz; 133 map->_dm_boundary = boundary; 134 map->_dm_flags = flags & ~(BUS_DMA_WAITOK|BUS_DMA_NOWAIT); 135 map->_dm_proc = NULL; 136 map->dm_mapsize = 0; /* no valid mappings */ 137 map->dm_nsegs = 0; 138 139 *dmamp = map; 140 return (0); 141 } 142 143 /* 144 * Common function for DMA map destruction. May be called by bus-specific 145 * DMA map destruction functions. 146 */ 147 void 148 _bus_dmamap_destroy(t, map) 149 bus_dma_tag_t t; 150 bus_dmamap_t map; 151 { 152 153 free(map, M_DMAMAP); 154 } 155 156 /* 157 * Utility function to load a linear buffer. lastaddrp holds state 158 * between invocations (for multiple-buffer loads). segp contains 159 * the starting segment on entrance, and the ending segment on exit. 160 * first indicates if this is the first invocation of this function. 161 */ 162 static int 163 _bus_dmamap_load_buffer(map, buf, buflen, p, flags, 164 lastaddrp, segp, first) 165 bus_dmamap_t map; 166 void *buf; 167 bus_size_t buflen; 168 struct proc *p; 169 int flags; 170 vaddr_t *lastaddrp; 171 int *segp; 172 int first; 173 { 174 bus_size_t sgsize; 175 bus_addr_t curaddr, lastaddr, baddr, bmask; 176 vaddr_t vaddr = (vaddr_t)buf; 177 int seg; 178 179 lastaddr = *lastaddrp; 180 bmask = ~(map->_dm_boundary - 1); 181 182 for (seg = *segp; buflen > 0 ; ) { 183 /* 184 * Get the physical address for this segment. 185 */ 186 if (p != NULL) 187 (void) pmap_extract(p->p_vmspace->vm_map.pmap, 188 vaddr, &curaddr); 189 else 190 curaddr = kvtophys(vaddr); 191 192 /* 193 * Compute the segment size, and adjust counts. 194 */ 195 sgsize = NBPG - ((u_long)vaddr & PGOFSET); 196 if (buflen < sgsize) 197 sgsize = buflen; 198 199 /* 200 * Make sure we don't cross any boundaries. 201 */ 202 if (map->_dm_boundary > 0) { 203 baddr = (curaddr + map->_dm_boundary) & bmask; 204 if (sgsize > (baddr - curaddr)) 205 sgsize = (baddr - curaddr); 206 } 207 208 /* 209 * Insert chunk into a segment, coalescing with 210 * the previous segment if possible. 211 */ 212 if (first) { 213 map->dm_segs[seg].ds_addr = curaddr; 214 map->dm_segs[seg].ds_len = sgsize; 215 map->dm_segs[seg]._ds_vaddr = vaddr; 216 first = 0; 217 } else { 218 if (curaddr == lastaddr && 219 (map->dm_segs[seg].ds_len + sgsize) <= 220 map->_dm_maxsegsz && 221 (map->_dm_boundary == 0 || 222 (map->dm_segs[seg].ds_addr & bmask) == 223 (curaddr & bmask))) 224 map->dm_segs[seg].ds_len += sgsize; 225 else { 226 if (++seg >= map->_dm_segcnt) 227 break; 228 map->dm_segs[seg].ds_addr = curaddr; 229 map->dm_segs[seg].ds_len = sgsize; 230 map->dm_segs[seg]._ds_vaddr = vaddr; 231 } 232 } 233 234 lastaddr = curaddr + sgsize; 235 vaddr += sgsize; 236 buflen -= sgsize; 237 } 238 239 *segp = seg; 240 *lastaddrp = lastaddr; 241 242 /* 243 * Did we fit? 244 */ 245 if (buflen != 0) 246 return (EFBIG); /* XXX better return value here? */ 247 248 return (0); 249 } 250 251 /* 252 * Common function for loading a direct-mapped DMA map with a linear 253 * buffer. 254 */ 255 int 256 _bus_dmamap_load(t, map, buf, buflen, p, flags) 257 bus_dma_tag_t t; 258 bus_dmamap_t map; 259 void *buf; 260 bus_size_t buflen; 261 struct proc *p; 262 int flags; 263 { 264 vaddr_t lastaddr; 265 int seg, error; 266 267 /* 268 * Make sure that on error condition we return "no valid mappings". 269 */ 270 map->dm_mapsize = 0; 271 map->dm_nsegs = 0; 272 273 if (buflen > map->_dm_size) 274 return (EINVAL); 275 276 seg = 0; 277 error = _bus_dmamap_load_buffer(map, buf, buflen, 278 p, flags, &lastaddr, &seg, 1); 279 if (error == 0) { 280 map->dm_mapsize = buflen; 281 map->dm_nsegs = seg + 1; 282 map->_dm_proc = p; 283 284 /* 285 * For linear buffers, we support marking the mapping 286 * as COHERENT. 287 * 288 * XXX Check TLB entries for cache-inhibit bits? 289 */ 290 if (buf >= (void *)MIPS_KSEG1_START && 291 buf < (void *)MIPS_KSEG2_START) 292 map->_dm_flags |= PMAX_DMAMAP_COHERENT; 293 } 294 return (error); 295 } 296 297 /* 298 * Like _bus_dmamap_load(), but for mbufs. 299 */ 300 int 301 _bus_dmamap_load_mbuf(t, map, m0, flags) 302 bus_dma_tag_t t; 303 bus_dmamap_t map; 304 struct mbuf *m0; 305 int flags; 306 { 307 vaddr_t lastaddr; 308 int seg, error, first; 309 struct mbuf *m; 310 311 /* 312 * Make sure that on error condition we return "no valid mappings." 313 */ 314 map->dm_mapsize = 0; 315 map->dm_nsegs = 0; 316 317 #ifdef DIAGNOSTIC 318 if ((m0->m_flags & M_PKTHDR) == 0) 319 panic("_bus_dmamap_load_mbuf: no packet header"); 320 #endif 321 322 if (m0->m_pkthdr.len > map->_dm_size) 323 return (EINVAL); 324 325 first = 1; 326 seg = 0; 327 error = 0; 328 for (m = m0; m != NULL && error == 0; m = m->m_next) { 329 error = _bus_dmamap_load_buffer(map, 330 m->m_data, m->m_len, NULL, flags, &lastaddr, &seg, first); 331 first = 0; 332 } 333 if (error == 0) { 334 map->dm_mapsize = m0->m_pkthdr.len; 335 map->dm_nsegs = seg + 1; 336 map->_dm_proc = NULL; /* always kernel */ 337 } 338 return (error); 339 } 340 341 /* 342 * Like _bus_dmamap_load(), but for uios. 343 */ 344 int 345 _bus_dmamap_load_uio(t, map, uio, flags) 346 bus_dma_tag_t t; 347 bus_dmamap_t map; 348 struct uio *uio; 349 int flags; 350 { 351 vaddr_t lastaddr; 352 int seg, i, error, first; 353 bus_size_t minlen, resid; 354 struct proc *p = NULL; 355 struct iovec *iov; 356 caddr_t addr; 357 358 /* 359 * Make sure that on error condition we return "no valid mappings." 360 */ 361 map->dm_mapsize = 0; 362 map->dm_nsegs = 0; 363 364 resid = uio->uio_resid; 365 iov = uio->uio_iov; 366 367 if (uio->uio_segflg == UIO_USERSPACE) { 368 p = uio->uio_procp; 369 #ifdef DIAGNOSTIC 370 if (p == NULL) 371 panic("_bus_dmamap_load_uio: USERSPACE but no proc"); 372 #endif 373 } 374 375 first = 1; 376 seg = 0; 377 error = 0; 378 for (i = 0; i < uio->uio_iovcnt && resid != 0 && error == 0; i++) { 379 /* 380 * Now at the first iovec to load. Load each iovec 381 * until we have exhausted the residual count. 382 */ 383 minlen = resid < iov[i].iov_len ? resid : iov[i].iov_len; 384 addr = iov[i].iov_base; 385 386 error = _bus_dmamap_load_buffer(map, addr, minlen, 387 p, flags, &lastaddr, &seg, first); 388 first = 0; 389 390 resid -= minlen; 391 } 392 if (error == 0) { 393 map->dm_mapsize = uio->uio_resid; 394 map->dm_nsegs = seg + 1; 395 map->_dm_proc = p; 396 } 397 return (error); 398 } 399 400 /* 401 * Like _bus_dmamap_load(), but for raw memory. 402 */ 403 int 404 _bus_dmamap_load_raw(t, map, segs, nsegs, size, flags) 405 bus_dma_tag_t t; 406 bus_dmamap_t map; 407 bus_dma_segment_t *segs; 408 int nsegs; 409 bus_size_t size; 410 int flags; 411 { 412 413 panic("_bus_dmamap_load_raw: not implemented"); 414 } 415 416 /* 417 * Common function for unloading a DMA map. May be called by 418 * chipset-specific DMA map unload functions. 419 */ 420 void 421 _bus_dmamap_unload(t, map) 422 bus_dma_tag_t t; 423 bus_dmamap_t map; 424 { 425 426 /* 427 * No resources to free; just mark the mappings as 428 * invalid. 429 */ 430 map->dm_mapsize = 0; 431 map->dm_nsegs = 0; 432 map->_dm_flags &= ~PMAX_DMAMAP_COHERENT; 433 map->_dm_proc = NULL; 434 } 435 436 #ifdef MIPS1 437 /* 438 * Common function for DMA map synchronization. May be called 439 * by chipset-specific DMA map synchronization functions. 440 * 441 * This is the R3000 version. 442 */ 443 void 444 _bus_dmamap_sync_r3k(t, map, offset, len, ops) 445 bus_dma_tag_t t; 446 bus_dmamap_t map; 447 bus_addr_t offset; 448 bus_size_t len; 449 int ops; 450 { 451 bus_size_t minlen; 452 bus_addr_t addr; 453 int i; 454 455 /* 456 * Mixing PRE and POST operations is not allowed. 457 */ 458 if ((ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) != 0 && 459 (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) != 0) 460 panic("_bus_dmamap_sync_r3k: mix PRE and POST"); 461 462 #ifdef DIAGNOSTIC 463 if (offset >= map->dm_mapsize) 464 panic("_bus_dmamap_sync_r3k: bad offset %lu (map size is %lu)", 465 offset, map->dm_mapsize); 466 if (len == 0 || (offset + len) > map->dm_mapsize) 467 panic("_bus_dmamap_sync_r3k: bad length"); 468 #endif 469 470 /* 471 * The R3000 cache is write-though. Therefore, we only need 472 * to drain the write buffer on PREWRITE. The cache is not 473 * coherent, however, so we need to invalidate the data cache 474 * on PREREAD (should we do it POSTREAD instead?). 475 * 476 * POSTWRITE (and POSTREAD, currently) are noops. 477 */ 478 479 if (ops & BUS_DMASYNC_PREWRITE) { 480 /* 481 * Flush the write buffer. 482 */ 483 wbflush(); 484 } 485 486 /* 487 * If we're not doing PREREAD, nothing more to do. 488 */ 489 if ((ops & BUS_DMASYNC_PREREAD) == 0) 490 return; 491 492 /* 493 * No cache invlidation is necessary if the DMA map covers 494 * COHERENT DMA-safe memory (which is mapped un-cached). 495 */ 496 if (map->_dm_flags & PMAX_DMAMAP_COHERENT) 497 return; 498 499 /* 500 * If we are going to hit something as large or larger 501 * than the entire data cache, just nail the whole thing. 502 * 503 * NOTE: Even though this is `wbinv_all', since the cache is 504 * write-though, it just invalidates it. 505 */ 506 if (len >= mips_pdcache_size) { 507 mips_dcache_wbinv_all(); 508 return; 509 } 510 511 for (i = 0; i < map->dm_nsegs && len != 0; i++) { 512 /* Find the beginning segment. */ 513 if (offset >= map->dm_segs[i].ds_len) { 514 offset -= map->dm_segs[i].ds_len; 515 continue; 516 } 517 518 /* 519 * Now at the first segment to sync; nail 520 * each segment until we have exhausted the 521 * length. 522 */ 523 minlen = len < map->dm_segs[i].ds_len - offset ? 524 len : map->dm_segs[i].ds_len - offset; 525 526 addr = map->dm_segs[i].ds_addr; 527 528 #ifdef BUS_DMA_DEBUG 529 printf("bus_dmamap_sync_r3k: flushing segment %d " 530 "(0x%lx..0x%lx) ...", i, addr + offset, 531 addr + offset + minlen - 1); 532 #endif 533 mips_dcache_inv_range( 534 MIPS_PHYS_TO_KSEG0(addr + offset), minlen); 535 #ifdef BUS_DMA_DEBUG 536 printf("\n"); 537 #endif 538 offset = 0; 539 len -= minlen; 540 } 541 } 542 #endif /* MIPS1 */ 543 544 #ifdef MIPS3 545 /* 546 * Common function for DMA map synchronization. May be called 547 * by chipset-specific DMA map synchronization functions. 548 * 549 * This is the R4000 version. 550 */ 551 void 552 _bus_dmamap_sync_r4k(t, map, offset, len, ops) 553 bus_dma_tag_t t; 554 bus_dmamap_t map; 555 bus_addr_t offset; 556 bus_size_t len; 557 int ops; 558 { 559 bus_size_t minlen; 560 bus_addr_t addr; 561 int i, useindex; 562 563 /* 564 * Mising PRE and POST operations is not allowed. 565 */ 566 if ((ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) != 0 && 567 (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) != 0) 568 panic("_bus_dmamap_sync_r4k: mix PRE and POST"); 569 570 #ifdef DIAGNOSTIC 571 if (offset >= map->dm_mapsize) 572 panic("_bus_dmamap_sync_r4k: bad offset %lu (map size is %lu)", 573 offset, map->dm_mapsize); 574 if (len == 0 || (offset + len) > map->dm_mapsize) 575 panic("_bus_dmamap_sync_r4k: bad length"); 576 #endif 577 578 /* 579 * The R4000 cache is virtually-indexed, write-back. This means 580 * we need to do the following things: 581 * 582 * PREREAD -- Invalidate D-cache. Note we might have 583 * to also write-back here if we have to use an Index 584 * op, or if the buffer start/end is not cache-line aligned. 585 * 586 * PREWRITE -- Write-back the D-cache. If we have to use 587 * an Index op, we also have to invalidate. Note that if 588 * we are doing PREREAD|PREWRITE, we can collapse everything 589 * into a single op. 590 * 591 * POSTREAD -- Nothing. 592 * 593 * POSTWRITE -- Nothing. 594 */ 595 596 /* 597 * Flush the write buffer. 598 * XXX Is this always necessary? 599 */ 600 wbflush(); 601 602 ops &= (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 603 if (ops == 0) 604 return; 605 606 /* 607 * If the mapping is of COHERENT DMA-safe memory, no cache 608 * flush is necessary. 609 */ 610 if (map->_dm_flags & PMAX_DMAMAP_COHERENT) 611 return; 612 613 /* 614 * If the mapping belongs to the kernel, or if it belongs 615 * to the currently-running process (XXX actually, vmspace), 616 * then we can use Hit ops. Otherwise, Index ops. 617 * 618 * This should be true the vast majority of the time. 619 */ 620 if (__predict_true(map->_dm_proc == NULL || map->_dm_proc == curproc)) 621 useindex = 0; 622 else 623 useindex = 1; 624 625 for (i = 0; i < map->dm_nsegs && len != 0; i++) { 626 /* Find the beginning segment. */ 627 if (offset >= map->dm_segs[i].ds_len) { 628 offset -= map->dm_segs[i].ds_len; 629 continue; 630 } 631 632 /* 633 * Now at the first segment to sync; nail 634 * each segment until we have exhausted the 635 * length. 636 */ 637 minlen = len < map->dm_segs[i].ds_len - offset ? 638 len : map->dm_segs[i].ds_len - offset; 639 640 addr = map->dm_segs[i]._ds_vaddr; 641 642 #ifdef BUS_DMA_DEBUG 643 printf("bus_dmamap_sync: flushing segment %d " 644 "(0x%lx..0x%lx) ...", i, addr + offset, 645 addr + offset + minlen - 1); 646 #endif 647 648 /* 649 * If we are forced to use Index ops, it's always a 650 * Write-back,Invalidate, so just do one test. 651 */ 652 if (__predict_false(useindex)) { 653 mips_dcache_wbinv_range_index(addr + offset, minlen); 654 #ifdef BUS_DMA_DEBUG 655 printf("\n"); 656 #endif 657 offset = 0; 658 len -= minlen; 659 continue; 660 } 661 662 switch (ops) { 663 case BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE: 664 mips_dcache_wbinv_range(addr + offset, minlen); 665 break; 666 667 case BUS_DMASYNC_PREREAD: 668 #if 1 669 mips_dcache_wbinv_range(addr + offset, minlen); 670 #else 671 mips_dcache_inv_range(addr + offset, minlen); 672 #endif 673 break; 674 675 case BUS_DMASYNC_PREWRITE: 676 mips_dcache_wb_range(addr + offset, minlen); 677 break; 678 } 679 #ifdef BUS_DMA_DEBUG 680 printf("\n"); 681 #endif 682 offset = 0; 683 len -= minlen; 684 } 685 } 686 #endif /* MIPS3 */ 687 688 /* 689 * Common function for DMA-safe memory allocation. May be called 690 * by bus-specific DMA memory allocation functions. 691 */ 692 int 693 _bus_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 694 bus_dma_tag_t t; 695 bus_size_t size, alignment, boundary; 696 bus_dma_segment_t *segs; 697 int nsegs; 698 int *rsegs; 699 int flags; 700 { 701 extern paddr_t avail_start, avail_end; /* XXX */ 702 vaddr_t curaddr, lastaddr; 703 psize_t high; 704 struct vm_page *m; 705 struct pglist mlist; 706 int curseg, error; 707 708 /* Always round the size. */ 709 size = round_page(size); 710 711 high = avail_end - PAGE_SIZE; 712 713 /* 714 * Allocate pages from the VM system. 715 */ 716 TAILQ_INIT(&mlist); 717 error = uvm_pglistalloc(size, avail_start, high, alignment, boundary, 718 &mlist, nsegs, (flags & BUS_DMA_NOWAIT) == 0); 719 if (error) 720 return (error); 721 722 /* 723 * Compute the location, size, and number of segments actually 724 * returned by the VM code. 725 */ 726 m = mlist.tqh_first; 727 curseg = 0; 728 lastaddr = segs[curseg].ds_addr = VM_PAGE_TO_PHYS(m); 729 segs[curseg].ds_len = PAGE_SIZE; 730 m = m->pageq.tqe_next; 731 732 for (; m != NULL; m = m->pageq.tqe_next) { 733 curaddr = VM_PAGE_TO_PHYS(m); 734 #ifdef DIAGNOSTIC 735 if (curaddr < avail_start || curaddr >= high) { 736 printf("uvm_pglistalloc returned non-sensical" 737 " address 0x%lx\n", curaddr); 738 panic("_bus_dmamem_alloc"); 739 } 740 #endif 741 if (curaddr == (lastaddr + PAGE_SIZE)) 742 segs[curseg].ds_len += PAGE_SIZE; 743 else { 744 curseg++; 745 segs[curseg].ds_addr = curaddr; 746 segs[curseg].ds_len = PAGE_SIZE; 747 } 748 lastaddr = curaddr; 749 } 750 751 *rsegs = curseg + 1; 752 753 return (0); 754 } 755 756 /* 757 * Common function for freeing DMA-safe memory. May be called by 758 * bus-specific DMA memory free functions. 759 */ 760 void 761 _bus_dmamem_free(t, segs, nsegs) 762 bus_dma_tag_t t; 763 bus_dma_segment_t *segs; 764 int nsegs; 765 { 766 struct vm_page *m; 767 bus_addr_t addr; 768 struct pglist mlist; 769 int curseg; 770 771 /* 772 * Build a list of pages to free back to the VM system. 773 */ 774 TAILQ_INIT(&mlist); 775 for (curseg = 0; curseg < nsegs; curseg++) { 776 for (addr = segs[curseg].ds_addr; 777 addr < (segs[curseg].ds_addr + segs[curseg].ds_len); 778 addr += PAGE_SIZE) { 779 m = PHYS_TO_VM_PAGE(addr); 780 TAILQ_INSERT_TAIL(&mlist, m, pageq); 781 } 782 } 783 784 uvm_pglistfree(&mlist); 785 } 786 787 /* 788 * Common function for mapping DMA-safe memory. May be called by 789 * bus-specific DMA memory map functions. 790 */ 791 int 792 _bus_dmamem_map(t, segs, nsegs, size, kvap, flags) 793 bus_dma_tag_t t; 794 bus_dma_segment_t *segs; 795 int nsegs; 796 size_t size; 797 caddr_t *kvap; 798 int flags; 799 { 800 vaddr_t va; 801 bus_addr_t addr; 802 int curseg; 803 804 /* 805 * If we're only mapping 1 segment, use KSEG0 or KSEG1, to avoid 806 * TLB thrashing. 807 */ 808 if (nsegs == 1) { 809 if (flags & BUS_DMA_COHERENT) 810 *kvap = (caddr_t)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr); 811 else 812 *kvap = (caddr_t)MIPS_PHYS_TO_KSEG0(segs[0].ds_addr); 813 return (0); 814 } 815 816 size = round_page(size); 817 818 va = uvm_km_valloc(kernel_map, size); 819 820 if (va == 0) 821 return (ENOMEM); 822 823 *kvap = (caddr_t)va; 824 825 for (curseg = 0; curseg < nsegs; curseg++) { 826 for (addr = segs[curseg].ds_addr; 827 addr < (segs[curseg].ds_addr + segs[curseg].ds_len); 828 addr += NBPG, va += NBPG, size -= NBPG) { 829 if (size == 0) 830 panic("_bus_dmamem_map: size botch"); 831 pmap_enter(pmap_kernel(), va, addr, 832 VM_PROT_READ | VM_PROT_WRITE, 833 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED); 834 835 /* XXX Do something about COHERENT here. */ 836 } 837 } 838 pmap_update(pmap_kernel()); 839 840 return (0); 841 } 842 843 /* 844 * Common function for unmapping DMA-safe memory. May be called by 845 * bus-specific DMA memory unmapping functions. 846 */ 847 void 848 _bus_dmamem_unmap(t, kva, size) 849 bus_dma_tag_t t; 850 caddr_t kva; 851 size_t size; 852 { 853 854 #ifdef DIAGNOSTIC 855 if ((u_long)kva & PGOFSET) 856 panic("_bus_dmamem_unmap"); 857 #endif 858 859 /* 860 * Nothing to do if we mapped it with KSEG0 or KSEG1 (i.e. 861 * not in KSEG2). 862 */ 863 if (kva >= (caddr_t)MIPS_KSEG0_START && 864 kva < (caddr_t)MIPS_KSEG2_START) 865 return; 866 867 size = round_page(size); 868 uvm_km_free(kernel_map, (vaddr_t)kva, size); 869 } 870 871 /* 872 * Common functin for mmap(2)'ing DMA-safe memory. May be called by 873 * bus-specific DMA mmap(2)'ing functions. 874 */ 875 paddr_t 876 _bus_dmamem_mmap(t, segs, nsegs, off, prot, flags) 877 bus_dma_tag_t t; 878 bus_dma_segment_t *segs; 879 int nsegs; 880 off_t off; 881 int prot, flags; 882 { 883 int i; 884 885 for (i = 0; i < nsegs; i++) { 886 #ifdef DIAGNOSTIC 887 if (off & PGOFSET) 888 panic("_bus_dmamem_mmap: offset unaligned"); 889 if (segs[i].ds_addr & PGOFSET) 890 panic("_bus_dmamem_mmap: segment unaligned"); 891 if (segs[i].ds_len & PGOFSET) 892 panic("_bus_dmamem_mmap: segment size not multiple" 893 " of page size"); 894 #endif 895 if (off >= segs[i].ds_len) { 896 off -= segs[i].ds_len; 897 continue; 898 } 899 900 return (mips_btop(segs[i].ds_addr + off)); 901 } 902 903 /* Page not found. */ 904 return (-1); 905 } 906