1 /* $NetBSD: dec_3100.c,v 1.35 2001/09/18 16:15:19 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1988 University of Utah. 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * the Systems Programming Group of the University of Utah Computer 40 * Science Department, The Mach Operating System project at 41 * Carnegie-Mellon University and Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 */ 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/device.h> 77 78 #include <machine/cpu.h> 79 #include <machine/intr.h> 80 #include <machine/sysconf.h> 81 82 #include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 83 84 #include <pmax/pmax/machdep.h> 85 #include <pmax/pmax/kn01.h> 86 #include <pmax/dev/pmvar.h> 87 #include <pmax/dev/dcvar.h> 88 89 #include <pmax/ibus/ibusvar.h> 90 91 #include "rasterconsole.h" 92 #include "pm.h" 93 94 void dec_3100_init __P((void)); /* XXX */ 95 static void dec_3100_bus_reset __P((void)); 96 97 static void dec_3100_cons_init __P((void)); 98 static void dec_3100_errintr __P((void)); 99 static void dec_3100_intr __P((unsigned, unsigned, unsigned, unsigned)); 100 static void dec_3100_intr_establish __P((struct device *, void *, 101 int, int (*)(void *), void *)); 102 103 #define kn01_wbflush() mips1_wbflush() /* XXX to be corrected XXX */ 104 105 void 106 dec_3100_init() 107 { 108 const char *submodel; 109 110 platform.iobus = "baseboard"; 111 platform.bus_reset = dec_3100_bus_reset; 112 platform.cons_init = dec_3100_cons_init; 113 platform.iointr = dec_3100_intr; 114 platform.intr_establish = dec_3100_intr_establish; 115 platform.memsize = memsize_scan; 116 /* no high resolution timer available */ 117 118 splvec.splbio = MIPS_SPL0; 119 splvec.splnet = MIPS_SPL_0_1; 120 splvec.spltty = MIPS_SPL_0_1_2; 121 splvec.splvm = MIPS_SPLHIGH; /* ??? */ 122 splvec.splclock = MIPS_SPL_0_1_2_3; 123 splvec.splstatclock = MIPS_SPL_0_1_2_3; 124 125 /* calibrate cpu_mhz value */ 126 mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_3); 127 128 if (cpu_mhz < 15) 129 submodel = "2100 (PMIN)"; 130 else 131 submodel = "3100 (PMAX)"; 132 sprintf(cpu_model, "DECstation %s", submodel); 133 } 134 135 /* 136 * Initialize the memory system and I/O buses. 137 */ 138 static void 139 dec_3100_bus_reset() 140 { 141 /* nothing to do */ 142 kn01_wbflush(); 143 } 144 145 static void 146 dec_3100_cons_init() 147 { 148 int kbd, crt, screen; 149 150 kbd = crt = screen = 0; 151 prom_findcons(&kbd, &crt, &screen); 152 153 if (screen > 0) { 154 #if NRASTERCONSOLE > 0 && NPM > 0 155 if (pm_cnattach() > 0) { 156 dckbd_cnattach(KN01_SYS_DZ); 157 return; 158 } 159 #else 160 printf("No framebuffer device configured: "); 161 printf("using serial console\n"); 162 #endif 163 } 164 /* 165 * Delay to allow PROM putchars to complete. 166 * FIFO depth * character time, 167 * character time = (1000000 / (defaultrate / 10)) 168 */ 169 DELAY(160000000 / 9600); /* XXX */ 170 171 dc_cnattach(KN01_SYS_DZ, kbd); 172 } 173 174 #define CALLINTR(vvv, cp0) \ 175 do { \ 176 if (ipending & (cp0)) { \ 177 intrcnt[vvv] += 1; \ 178 (*intrtab[vvv].ih_func)(intrtab[vvv].ih_arg); \ 179 } \ 180 } while (0) 181 182 static void 183 dec_3100_intr(status, cause, pc, ipending) 184 unsigned status; 185 unsigned cause; 186 unsigned pc; 187 unsigned ipending; 188 { 189 /* handle clock interrupts ASAP */ 190 if (ipending & MIPS_INT_MASK_3) { 191 struct clockframe cf; 192 193 __asm __volatile("lbu $0,48(%0)" :: 194 "r"(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK))); 195 cf.pc = pc; 196 cf.sr = status; 197 hardclock(&cf); 198 pmax_clock_evcnt.ev_count++; 199 200 /* keep clock interrupts enabled when we return */ 201 cause &= ~MIPS_INT_MASK_3; 202 } 203 204 /* If clock interrupts were enabled, re-enable them ASAP. */ 205 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 206 207 CALLINTR(SYS_DEV_SCSI, MIPS_INT_MASK_0); 208 CALLINTR(SYS_DEV_LANCE, MIPS_INT_MASK_1); 209 CALLINTR(SYS_DEV_SCC0, MIPS_INT_MASK_2); 210 211 if (ipending & MIPS_INT_MASK_4) { 212 dec_3100_errintr(); 213 pmax_memerr_evcnt.ev_count++; 214 } 215 _splset(MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 216 } 217 218 219 static void 220 dec_3100_intr_establish(dev, cookie, level, handler, arg) 221 struct device *dev; 222 void *cookie; 223 int level; 224 int (*handler) __P((void *)); 225 void *arg; 226 { 227 228 intrtab[(int)cookie].ih_func = handler; 229 intrtab[(int)cookie].ih_arg = arg; 230 } 231 232 233 /* 234 * Handle memory errors. 235 */ 236 static void 237 dec_3100_errintr() 238 { 239 u_int16_t csr; 240 241 csr = *(u_int16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR); 242 243 if (csr & KN01_CSR_MERR) { 244 printf("Memory error at 0x%x\n", 245 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_ERRADR)); 246 panic("Mem error interrupt"); 247 } 248 csr = (csr & ~KN01_CSR_MBZ) | 0xff; 249 *(volatile u_int16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR) = csr; 250 } 251