1 /* $NetBSD: kmin.h,v 1.8 2000/02/29 04:41:55 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * The Mach Operating System project at Carnegie-Mellon University, 9 * Ralph Campbell and Rick Macklem. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)kmin.h 8.1 (Berkeley) 6/10/93 40 */ 41 42 /* 43 * Mach Operating System 44 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 45 * All Rights Reserved. 46 * 47 * Permission to use, copy, modify and distribute this software and 48 * its documentation is hereby granted, provided that both the copyright 49 * notice and this permission notice appear in all copies of the 50 * software, derivative works or modified versions, and any portions 51 * thereof, and that both notices appear in supporting documentation. 52 * 53 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 54 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 55 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 56 * 57 * Carnegie Mellon requests users of this software to return to 58 * 59 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 60 * School of Computer Science 61 * Carnegie Mellon University 62 * Pittsburgh PA 15213-3890 63 * 64 * any improvements or extensions that they make and grant Carnegie the 65 * rights to redistribute these changes. 66 */ 67 /* 68 * HISTORY 69 * Log: kmin.h,v 70 * Revision 2.3 92/03/02 18:33:43 rpd 71 * Split out the ASIC defns into separate file, which is 72 * in common with MAXine. Added some nitwits defines. 73 * [92/03/02 02:28:27 af] 74 * 75 * Revision 2.2 91/08/24 12:21:08 af 76 * Documented new SCSI registers, which were missing in the 3min prototype. 77 * [91/08/22 11:14:57 af] 78 * 79 * Created, from the DEC specs: 80 * "3MIN System Module Functional Specification" Revision 1.7 81 * Workstation Systems Engineering, Palo Alto, CA. Sept 14, 1990. 82 * "KN02BA Daughter Card Functional Specification" Revision 1.0 83 * Workstation Systems Engineering, Palo Alto, CA. Aug 14, 1990. 84 * [91/06/21 af] 85 * 86 */ 87 /* 88 * File: kmin.h 89 * Author: Alessandro Forin, Carnegie Mellon University 90 * Date: 6/91 91 * 92 * Definitions specific to the KN02BA/KN02DA processors and 3MIN 93 * system module (54-20604-01) 94 */ 95 96 #ifndef MIPS_KMIN_H 97 #define MIPS_KMIN_H 1 98 99 /* 100 * 3MIN's Physical address space 101 */ 102 #define KMIN_PHYS_MIN 0x00000000 /* 512 Meg */ 103 #define KMIN_PHYS_MAX 0x1fffffff 104 105 /* 106 * Memory map 107 */ 108 #define KMIN_PHYS_MEMORY_START 0x00000000 109 #define KMIN_PHYS_MEMORY_END 0x07ffffff /* 128 Meg in 8 slots */ 110 111 /* 112 * I/O map 113 */ 114 #define KMIN_PHYS_RESERVED 0x08000000 /* Reserved */ 115 /* 64 Meg */ 116 117 #define KMIN_PHYS_MREGS_START 0x0c000000 /* Memory control registers */ 118 #define KMIN_PHYS_MREGS_END 0x0dffffff /* 32 Meg */ 119 #define KMIN_PHYS_CREGS_START 0x0e000000 /* CPU ASIC control regs */ 120 #define KMIN_PHYS_CREGS_END 0x0fffffff /* 32 Meg */ 121 122 #define KMIN_PHYS_TC_0_START 0x10000000 /* TURBOchannel, slot 0 */ 123 #define KMIN_PHYS_TC_0_END 0x13ffffff /* 64 Meg, option0 */ 124 125 #define KMIN_PHYS_TC_1_START 0x14000000 /* TURBOchannel, slot 1 */ 126 #define KMIN_PHYS_TC_1_END 0x17ffffff /* 64 Meg, option1 */ 127 128 #define KMIN_PHYS_TC_2_START 0x18000000 /* TURBOchannel, slot 2 */ 129 #define KMIN_PHYS_TC_2_END 0x1bffffff /* 64 Meg, option2 */ 130 131 #define KMIN_PHYS_TC_3_START 0x1c000000 /* TURBOchannel, slot 3 */ 132 #define KMIN_PHYS_TC_3_END 0x1fffffff /* 64 Meg, system devices */ 133 134 #define KMIN_PHYS_TC_START KMIN_PHYS_TC_0_START 135 #define KMIN_PHYS_TC_END KMIN_PHYS_TC_3_END /* 256 Meg */ 136 137 #define KMIN_TC_NSLOTS 4 138 #define KMIN_TC_MIN 0 139 #define KMIN_TC_MAX 2 /* don't look at system slot */ 140 141 /* 142 * System module space (IOASIC) 143 */ 144 #define KMIN_SYS_ASIC ( KMIN_PHYS_TC_3_START + 0x0000000 ) 145 #define KMIN_SYS_ROM_START ( KMIN_SYS_ASIC + IOASIC_SLOT_0_START ) 146 #define KMIN_SYS_ASIC_REGS ( KMIN_SYS_ASIC + IOASIC_SLOT_1_START ) 147 #define KMIN_SYS_ETHER_ADDRESS ( KMIN_SYS_ASIC + IOASIC_SLOT_2_START ) 148 #define KMIN_SYS_LANCE ( KMIN_SYS_ASIC + IOASIC_SLOT_3_START ) 149 #define KMIN_SYS_SCC_0 ( KMIN_SYS_ASIC + IOASIC_SLOT_4_START ) 150 #define KMIN_SYS_SCC_1 ( KMIN_SYS_ASIC + IOASIC_SLOT_6_START ) 151 #define KMIN_SYS_CLOCK ( KMIN_SYS_ASIC + IOASIC_SLOT_8_START ) 152 #define KMIN_SYS_SCSI ( KMIN_SYS_ASIC + IOASIC_SLOT_12_START ) 153 #define KMIN_SYS_SCSI_DMA ( KMIN_SYS_ASIC + IOASIC_SLOT_14_START ) 154 #define KMIN_SYS_BOOT_ROM_START ( KMIN_PHYS_TC_3_START + 0x3c00000 ) 155 #define KMIN_SYS_BOOT_ROM_END ( KMIN_PHYS_TC_3_START + 0x3c40000 ) 156 157 /* 158 * Interrupts 159 */ 160 #define KMIN_INT_FPA IP_LEV7 /* Floating Point coproc */ 161 #define KMIN_INT_HALTB IP_LEV6 /* Halt button */ 162 #define KMIN_INT_TC3 IP_LEV5 /* TC slot 3, system */ 163 #define KMIN_INT_TC2 IP_LEV4 /* TC option slot 2 */ 164 #define KMIN_INT_TC1 IP_LEV3 /* TC option slot 1 */ 165 #define KMIN_INT_TC0 IP_LEV2 /* TC option slot 0 */ 166 167 /* 168 * System registers addresses (MREG and CREG space, and IO Control ASIC) 169 */ 170 #define KMIN_REG_MER 0x0c400000 /* Memory error register */ 171 #define KMIN_REG_MSR 0x0c800000 /* Memory size register */ 172 173 #define KMIN_REG_CNFG 0x0e000000 /* Config mem timeouts */ 174 #define KMIN_REG_AER 0x0e000004 /* Address error register */ 175 #define KMIN_REG_BOOT 0x0e000008 /* Boot 0 register */ 176 #define KMIN_REG_TIMEOUT 0x0e00000c /* Mem access timeout reg */ 177 178 #define KMIN_REG_SCSI_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCSI_DMAPTR ) 179 #define KMIN_REG_SCSI_DMANPTR ( KMIN_SYS_ASIC + IOASIC_SCSI_NEXTPTR ) 180 #define KMIN_REG_LANCE_DMAPTR ( KMIN_SYS_ASIC + IOASIC_LANCE_DMAPTR ) 181 #define KMIN_REG_SCC_T1_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCC_T1_DMAPTR ) 182 #define KMIN_REG_SCC_R1_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCC_R1_DMAPTR ) 183 #define KMIN_REG_SCC_T2_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCC_T2_DMAPTR ) 184 #define KMIN_REG_SCC_R2_DMAPTR ( KMIN_SYS_ASIC + IOASIC_SCC_R2_DMAPTR ) 185 #define KMIN_REG_CSR ( KMIN_SYS_ASIC + IOASIC_CSR ) 186 #define KMIN_REG_INTR ( KMIN_SYS_ASIC + IOASIC_INTR ) 187 #define KMIN_REG_IMSK ( KMIN_SYS_ASIC + IOASIC_IMSK ) 188 #define KMIN_REG_CURADDR ( KMIN_SYS_ASIC + IOASIC_CURADDR ) 189 190 #define KMIN_REG_LANCE_DECODE ( KMIN_SYS_ASIC + IOASIC_LANCE_DECODE ) 191 #define KMIN_REG_SCSI_DECODE ( KMIN_SYS_ASIC + IOASIC_SCSI_DECODE ) 192 #define KMIN_REG_SCC0_DECODE ( KMIN_SYS_ASIC + IOASIC_SCC0_DECODE ) 193 #define KMIN_REG_SCC1_DECODE ( KMIN_SYS_ASIC + IOASIC_SCC1_DECODE ) 194 # define KMIN_LANCE_CONFIG 3 195 # define KMIN_SCSI_CONFIG 14 196 # define KMIN_SCC0_CONFIG (0x10|4) 197 # define KMIN_SCC1_CONFIG (0x10|6) 198 199 #define KMIN_REG_SCSI_SCR ( KMIN_SYS_ASIC + IOASIC_SCSI_SCR ) 200 #define KMIN_REG_SCSI_SDR0 ( KMIN_SYS_ASIC + IOASIC_SCSI_SDR0 ) 201 #define KMIN_REG_SCSI_SDR1 ( KMIN_SYS_ASIC + IOASIC_SCSI_SDR1 ) 202 203 204 /* 205 * System registers defines (MREG and CREG) 206 */ 207 /* Memory error register */ 208 #define KMIN_MER_xxx 0xfffe30ff /* undefined */ 209 #define KMIN_MER_PAGE_BRY 0x00010000 /* rw: Page boundary error */ 210 #define KMIN_MER_TLEN 0x00008000 /* rw: Xfer length error */ 211 #define KMIN_MER_PARDIS 0x00004000 /* rw: Dis parity err intr */ 212 #define KMIN_MER_LASTBYTE 0x00000f00 /* rz: Last byte in error: */ 213 # define KMIN_LASTB31 0x00000800 /* upper byte of word */ 214 # define KMIN_LASTB23 0x00000400 /* .. through .. */ 215 # define KMIN_LASTB15 0x00000200 /* .. the .. */ 216 # define KMIN_LASTB07 0x00000100 /* .. lower byte */ 217 218 /* Memory size register */ 219 #define KMIN_MSR_SIZE_16Mb 0x00002000 /* rw: using 16Mb mem banks */ 220 #define KMIN_MSR_xxx 0xffffdfff /* undefined */ 221 222 /* NOTES 223 224 Memory access priority is, from higher to lower: 225 - DRAM refresh 226 - IO DMA (IO Control ASIC) 227 - Processor 228 - Slot 2 DMA 229 - Slot 1 DMA 230 - Slot 0 DMA 231 232 Memory performance is (with 80ns mem cycles) 233 - single word read 5 cyc 10.0 Mb/s 234 - word write 3 cyc 16.7 Mb/s 235 - single byte write 3 cyc 4.2 Mb/s 236 - 64w DMA read 68 cyc 47.1 Mb/s 237 - 64w DMA write 66 cyc 48.5 Mb/s 238 - Refresh 5 cyc N/A 239 */ 240 241 /* Timeout config register */ 242 #define KMIN_CNFG_VALUE_12Mhz 127 243 #define KMIN_CNFG_VALUE_25Mhz 0 244 245 /* Address error register */ 246 #define KMIN_AER_ADDR_MASK 0x1ffffffc /* ro: phys addr in error */ 247 248 /* Boot 0 register */ 249 #define KMIN_BOOT_FROM_SLOT0 0x00000001 /* rw: diag board boot */ 250 251 /* Memory access timeout interrupt register */ 252 #define KMIN_TIMEO_INTR 0x00000001 /* rc: intr pending */ 253 254 /* 255 * More system registers defines (IOASIC) 256 */ 257 /* (re)defines for the system Status and Control register (SSR) */ 258 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ 259 #define KMIN_CSR_DIAGDN 0x00008000 /* rw */ 260 #define KMIN_CSR_TXDIS_2 0x00004000 /* rw */ 261 #define KMIN_CSR_TXDIS_1 0x00002000 /* rw */ 262 #define KMIN_CSR_SCC_ENABLE 0x00000800 /* rw */ 263 #define KMIN_CSR_RTC_ENABLE 0x00000400 /* rw */ 264 #define KMIN_CSR_SCSI_ENABLE 0x00000200 /* rw */ 265 #define KMIN_CSR_LANCE_ENABLE 0x00000100 /* rw */ 266 #define KMIN_CSR_LEDS 0x000000ff /* rw */ 267 268 /* (re)defines for the System Interrupt and Mask Registers */ 269 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ 270 #define KMIN_INTR_NVR_JUMPER 0x00004000 /* ro */ 271 #define KMIN_INTR_TIMEOUT 0x00001000 /* ro */ 272 #define KMIN_INTR_NRMOD_JUMPER 0x00000400 /* ro */ 273 #define KMIN_INTR_SCSI 0x00000200 /* ro */ 274 #define KMIN_INTR_LANCE 0x00000100 /* ro */ 275 #define KMIN_INTR_SCC_1 0x00000080 /* ro */ 276 #define KMIN_INTR_SCC_0 0x00000040 /* ro */ 277 #define KMIN_INTR_CLOCK 0x00000020 /* ro */ 278 #define KMIN_INTR_PSWARN 0x00000010 /* ro */ 279 #define KMIN_INTR_SCSI_FIFO 0x00000004 /* ro */ 280 #define KMIN_INTR_PBNC 0x00000002 /* ro */ 281 #define KMIN_INTR_PBNO 0x00000001 /* ro */ 282 #define KMIN_INTR_ASIC 0xff0f0004 283 #define KMIN_IM0 0xff0f13f0 /* all good ones enabled */ 284 285 #endif /* MIPS_KMIN_H */ 286