1 /* $NetBSD: kn02.h,v 1.10 2005/12/11 12:18:39 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * The Mach Operating System project at Carnegie-Mellon University, 9 * Ralph Campbell and Rick Macklem. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)kn02.h 8.1 (Berkeley) 6/10/93 36 */ 37 38 /* 39 * Mach Operating System 40 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 41 * All Rights Reserved. 42 * 43 * Permission to use, copy, modify and distribute this software and 44 * its documentation is hereby granted, provided that both the copyright 45 * notice and this permission notice appear in all copies of the 46 * software, derivative works or modified versions, and any portions 47 * thereof, and that both notices appear in supporting documentation. 48 * 49 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 50 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 51 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 52 * 53 * Carnegie Mellon requests users of this software to return to 54 * 55 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 56 * School of Computer Science 57 * Carnegie Mellon University 58 * Pittsburgh PA 15213-3890 59 * 60 * any improvements or extensions that they make and grant Carnegie the 61 * rights to redistribute these changes. 62 */ 63 /* 64 * HISTORY 65 * Log: kn02.h,v 66 * Revision 2.5 91/05/14 17:23:30 mrt 67 * Correcting copyright 68 * 69 * Revision 2.4 91/02/05 17:42:03 mrt 70 * Added author notices 71 * [91/02/04 11:14:23 mrt] 72 * 73 * Changed to use new Mach copyright 74 * [91/02/02 12:12:58 mrt] 75 * 76 * Revision 2.3 90/12/05 23:32:04 af 77 * 78 * 79 * Revision 2.1.1.2 90/11/01 02:48:10 af 80 * Reworked a bit, made reentrant. 81 * 82 * Revision 2.1.1.1 90/10/03 11:48:22 af 83 * Created, from the DEC specs: 84 * "DECstation 5000/200 KN02 System Module Functional Specification" 85 * Workstation Systems Engineering, Palo Alto, CA. Aug 27, 1990. 86 * [90/09/03 af] 87 */ 88 /* 89 * File: kn02.h 90 * Author: Alessandro Forin, Carnegie Mellon University 91 * Date: 9/90 92 * 93 * Definitions specific to the KN02 processor (3max) 94 */ 95 96 #ifndef MIPS_KN02_H 97 #define MIPS_KN02_H 1 98 99 /* 100 * KN02's Physical address space 101 */ 102 #define KN02_PHYS_MIN 0x00000000 /* 512 Meg */ 103 #define KN02_PHYS_MAX 0x1fffffff 104 105 /* 106 * Memory map 107 */ 108 #define KN02_PHYS_MEMORY_START 0x00000000 109 #define KN02_PHYS_MEMORY_END 0x1dffffff /* 480 Meg in 15 slots */ 110 111 /* 112 * I/O map 113 */ 114 #define KN02_PHYS_TC_0_START 0x1e000000 /* TURBOchannel, slot 0 */ 115 #define KN02_PHYS_TC_0_END 0x1e3fffff /* 4 Meg, option0 */ 116 117 #define KN02_PHYS_TC_1_START 0x1e400000 /* TURBOchannel, slot 1 */ 118 #define KN02_PHYS_TC_1_END 0x1e7fffff /* 4 Meg, option1 */ 119 120 #define KN02_PHYS_TC_2_START 0x1e800000 /* TURBOchannel, slot 2 */ 121 #define KN02_PHYS_TC_2_END 0x1ebfffff /* 4 Meg, option2 */ 122 123 #define KN02_PHYS_TC_3_START 0x1ec00000 /* TURBOchannel, slot 3 */ 124 #define KN02_PHYS_TC_3_END 0x1effffff /* 4 Meg, reserved*/ 125 126 #define KN02_PHYS_TC_4_START 0x1f000000 /* TURBOchannel, slot 4 */ 127 #define KN02_PHYS_TC_4_END 0x1f3fffff /* 4 Meg, reserved*/ 128 129 #define KN02_PHYS_TC_5_START 0x1f400000 /* TURBOchannel, slot 5 */ 130 #define KN02_PHYS_TC_5_END 0x1f7fffff /* 4 Meg, SCSI */ 131 132 #define KN02_PHYS_TC_6_START 0x1f800000 /* TURBOchannel, slot 6 */ 133 #define KN02_PHYS_TC_6_END 0x1fbfffff /* 4 Meg, ether */ 134 135 #define KN02_PHYS_TC_7_START 0x1fc00000 /* TURBOchannel, slot 7 */ 136 #define KN02_PHYS_TC_7_END 0x1fffffff /* 4 Meg, system devices */ 137 138 #define KN02_PHYS_TC_START KN02_PHYS_TC_0_START 139 #define KN02_PHYS_TC_END KN02_PHYS_TC_7_END /* 32 Meg */ 140 141 #define KN02_TC_NSLOTS 8 142 #define KN02_TC_MIN 0 143 #define KN02_TC_MAX 6 /* don't look at system slot */ 144 145 /* 146 * System devices 147 */ 148 #define KN02_SYS_ROM_START KN02_PHYS_TC_7_START+0x000000 149 #define KN02_SYS_ROM_END KN02_PHYS_TC_7_START+0x07ffff 150 #define KN02_SYS_RESERVED KN02_PHYS_TC_7_START+0x080000 151 #define KN02_SYS_CHKSYN KN02_PHYS_TC_7_START+0x100000 152 #define KN02_SYS_ERRADR KN02_PHYS_TC_7_START+0x180000 153 #define KN02_SYS_DZ KN02_PHYS_TC_7_START+0x200000 154 #define KN02_SYS_CLOCK KN02_PHYS_TC_7_START+0x280000 155 #define KN02_SYS_CSR KN02_PHYS_TC_7_START+0x300000 156 #define KN02_SYS_ROM1_START KN02_PHYS_TC_7_START+0x380000 157 #define KN02_SYS_ROM1_END KN02_PHYS_TC_7_START+0x3fffff 158 159 /* 160 * Interrupts 161 */ 162 #define KN02_INT_FPA IP_LEV7 /* Floating Point coproc */ 163 #define KN02_INT_RES1 IP_LEV6 /* reserved, unused */ 164 #define KN02_INT_MEM IP_LEV5 /* memory controller */ 165 #define KN02_INT_RES2 IP_LEV4 /* reserved, unused */ 166 #define KN02_INT_CLOCK IP_LEV3 /* RTC chip */ 167 #define KN02_INT_IO IP_LEV2 /* I/O slots */ 168 169 /* 170 * System board registers 171 */ 172 /* system Status and Control register */ 173 #define KN02_CSR_IOINT 0x000000ff /* ro Interrupt pending */ 174 # define KN02_IP_DZ 0x00000080 /* serial lines */ 175 # define KN02_IP_LANCE 0x00000040 /* thin ethernet */ 176 # define KN02_IP_SCSI 0x00000020 /* ASC scsi controller */ 177 # define KN02_IP_XXXX 0x00000018 /* unused */ 178 # define KN02_IP_SLOT2 0x00000004 /* option slot 2 */ 179 # define KN02_IP_SLOT1 0x00000002 /* option slot 1 */ 180 # define KN02_IP_SLOT0 0x00000001 /* option slot 0 */ 181 182 #define KN02_CSR_BAUD38 0x00000100 /* rw Max DZ baud rate */ 183 #define KN02_CSR_DIAGDN 0x00000200 /* rw Diag jumper */ 184 #define KN02_CSR_BNK32M 0x00000400 /* rw Memory bank stride */ 185 #define KN02_CSR_TXDIS 0x00000800 /* rw Disable DZ xmit */ 186 #define KN02_CSR_LEDIAG 0x00001000 /* rw Latch ECC */ 187 #define KN02_CSR_CORRECT 0x00002000 /* rw ECC corrects single bit */ 188 #define KN02_CSR_ECCMD 0x0000c000 /* rw ECC logic mode */ 189 #define KN02_CSR_IOINTEN 0x00ff0000 /* rw Interrupt enable */ 190 #define KN02_CSR_IOINTEN_SHIFT 16 191 #define KN02_CSR_NRMMOD 0x01000000 /* ro Diag jumper state */ 192 #define KN02_CSR_REFEVEN 0x02000000 /* ro Refreshing even mem bank */ 193 #define KN02_CSR_PRSVNVR 0x04000000 /* ro Preserve NVR jumper */ 194 #define KN02_CSR_PSWARN 0x08000000 /* ro PS overheating */ 195 #define KN02_CSR_RRESERVED 0xf0000000 /* rz */ 196 197 #define KN02_CSR_LEDS 0x000000ff /* wo Diag LEDs */ 198 #define KN02_CSR_WRESERVED 0xff000000 /* wz */ 199 200 /* Error address status register */ 201 #define KN02_ERR_ADDRESS 0x07ffffff /* phys address */ 202 #define KN02_ERR_RESERVED 0x08000000 /* unused */ 203 #define KN02_ERR_ECCERR 0x10000000 /* ECC error */ 204 #define KN02_ERR_WRITE 0x20000000 /* read/write transaction */ 205 #define KN02_ERR_CPU 0x40000000 /* CPU or device initiator */ 206 #define KN02_ERR_VALID 0x80000000 /* Info is valid */ 207 208 /* ECC check/syndrome status register */ 209 #define KN02_ECC_SYNLO 0x0000007f /* syndrome, even bank */ 210 #define KN02_ECC_SNGLO 0x00000080 /* single bit err, " */ 211 #define KN02_ECC_CHKLO 0x00007f00 /* check bits, " " */ 212 #define KN02_ECC_VLDLO 0x00008000 /* info valid for " */ 213 #define KN02_ECC_SYNHI 0x007f0000 /* syndrome, odd bank */ 214 #define KN02_ECC_SNGHI 0x00800000 /* single bit err, " */ 215 #define KN02_ECC_CHKHI 0x7f000000 /* check bits, " " */ 216 #define KN02_ECC_VLDHI 0x80000000 /* info valid for " */ 217 218 #endif /* MIPS_KN02_H */ 219