1 /* $NetBSD: kn03.h,v 1.10 2000/02/29 04:41:57 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * The Mach Operating System project at Carnegie-Mellon University, 9 * Ralph Campbell and Rick Macklem. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)kn03.h 8.1 (Berkeley) 6/10/93 40 */ 41 42 /* 43 * Mach Operating System 44 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 45 * All Rights Reserved. 46 * 47 * Permission to use, copy, modify and distribute this software and 48 * its documentation is hereby granted, provided that both the copyright 49 * notice and this permission notice appear in all copies of the 50 * software, derivative works or modified versions, and any portions 51 * thereof, and that both notices appear in supporting documentation. 52 * 53 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 54 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 55 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 56 * 57 * Carnegie Mellon requests users of this software to return to 58 * 59 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 60 * School of Computer Science 61 * Carnegie Mellon University 62 * Pittsburgh PA 15213-3890 63 * 64 * any improvements or extensions that they make and grant Carnegie the 65 * rights to redistribute these changes. 66 */ 67 /* 68 * Definitions specific to the KN03GA processors and 3MAX+ 69 * DECstation 5000/240 mother board. 70 */ 71 72 #ifndef MIPS_KN03_H 73 #define MIPS_KN03_H 1 74 75 /* 76 * 3MAX+'s Physical address space 77 */ 78 #define KN03_PHYS_MIN 0x00000000 /* 512 Meg */ 79 #define KN03_PHYS_MAX 0x1fffffff 80 81 /* 82 * Memory map 83 */ 84 #define KN03_PHYS_MEMORY_START 0x00000000 85 #define KN03_PHYS_MEMORY_END 0x1dffffff /* 480 Meg */ 86 87 /* 88 * I/O map 89 */ 90 #define KN03_PHYS_TC_0_START 0x1e000000 /* TURBOchannel, slot 0 */ 91 #define KN03_PHYS_TC_0_END 0x1e7fffff /* 8 Meg, option0 */ 92 93 #define KN03_PHYS_TC_1_START 0x1e800000 /* TURBOchannel, slot 1 */ 94 #define KN03_PHYS_TC_1_END 0x1effffff /* 8 Meg, option1 */ 95 96 #define KN03_PHYS_TC_2_START 0x1f000000 /* TURBOchannel, slot 2 */ 97 #define KN03_PHYS_TC_2_END 0x1f7fffff /* 8 Meg, option2 */ 98 99 #define KN03_PHYS_TC_3_START 0x1f800000 /* TURBOchannel, slot 3 */ 100 #define KN03_PHYS_TC_3_END 0x1fffffff /* 8 Meg, system devices */ 101 102 #define KN03_PHYS_TC_START KN03_PHYS_TC_0_START 103 #define KN03_PHYS_TC_END KN03_PHYS_TC_3_END 104 105 #define KN03_TC_NSLOTS 4 106 #define KN03_TC_MIN 0 107 #define KN03_TC_MAX 2 /* don't look at system slot */ 108 109 /* 110 * System module space (IOASIC) 111 */ 112 #define KN03_SYS_ASIC ( KN03_PHYS_TC_3_START + 0x0000000 ) 113 #define KN03_SYS_ROM_START ( KN03_SYS_ASIC + IOASIC_SLOT_0_START ) 114 #define KN03_SYS_ASIC_REGS ( KN03_SYS_ASIC + IOASIC_SLOT_1_START ) 115 #define KN03_SYS_ETHER_ADDRESS ( KN03_SYS_ASIC + IOASIC_SLOT_2_START ) 116 #define KN03_SYS_LANCE ( KN03_SYS_ASIC + IOASIC_SLOT_3_START ) 117 #define KN03_SYS_SCC_0 ( KN03_SYS_ASIC + IOASIC_SLOT_4_START ) 118 #define KN03_SYS_SCC_1 ( KN03_SYS_ASIC + IOASIC_SLOT_6_START ) 119 #define KN03_SYS_CLOCK ( KN03_SYS_ASIC + IOASIC_SLOT_8_START ) 120 #define KN03_SYS_ERRADR ( KN03_SYS_ASIC + IOASIC_SLOT_9_START ) 121 #define KN03_SYS_ERRSYN ( KN03_SYS_ASIC + IOASIC_SLOT_10_START ) 122 #define KN03_SYS_CSR ( KN03_SYS_ASIC + IOASIC_SLOT_11_START ) 123 #define KN03_SYS_SCSI ( KN03_SYS_ASIC + IOASIC_SLOT_12_START ) 124 #define KN03_SYS_SCSI_DMA ( KN03_SYS_ASIC + IOASIC_SLOT_14_START ) 125 #define KN03_SYS_BOOT_ROM_START ( KN03_PHYS_TC_3_START + 0x400000 ) 126 #define KN03_SYS_BOOT_ROM_END ( KN03_PHYS_TC_3_START + 0x43ffff ) 127 128 /* 129 * Interrupts 130 */ 131 #define KN03_INT_FPA IP_LEV7 /* Floating Point coproc */ 132 #define KN03_INT_HALTB IP_LEV6 /* Halt button */ 133 #define KN03_INT_MEM IP_LEV5 /* Memory Errors */ 134 #define KN03_INT_RTC IP_LEV3 /* RTC clock */ 135 #define KN03_INT_ASIC IP_LEV2 /* All turbochannel */ 136 137 #define KN03_REG_SCSI_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCSI_DMAPTR ) 138 #define KN03_REG_SCSI_DMANPTR ( KN03_SYS_ASIC + IOASIC_SCSI_NEXTPTR ) 139 #define KN03_REG_LANCE_DMAPTR ( KN03_SYS_ASIC + IOASIC_LANCE_DMAPTR ) 140 #define KN03_REG_SCC_T1_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_T1_DMAPTR ) 141 #define KN03_REG_SCC_R1_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_R1_DMAPTR ) 142 #define KN03_REG_SCC_T2_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_T2_DMAPTR ) 143 #define KN03_REG_SCC_R2_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_R2_DMAPTR ) 144 #define KN03_REG_CSR ( KN03_SYS_ASIC + IOASIC_CSR ) 145 #define KN03_REG_INTR ( KN03_SYS_ASIC + IOASIC_INTR ) 146 #define KN03_REG_IMSK ( KN03_SYS_ASIC + IOASIC_IMSK ) 147 #define KN03_REG_CURADDR ( KN03_SYS_ASIC + IOASIC_CURADDR ) 148 149 #define KN03_REG_LANCE_DECODE ( KN03_SYS_ASIC + IOASIC_LANCE_DECODE ) 150 #define KN03_REG_SCSI_DECODE ( KN03_SYS_ASIC + IOASIC_SCSI_DECODE ) 151 #define KN03_REG_SCC0_DECODE ( KN03_SYS_ASIC + IOASIC_SCC0_DECODE ) 152 #define KN03_REG_SCC1_DECODE ( KN03_SYS_ASIC + IOASIC_SCC1_DECODE ) 153 # define KN03_LANCE_CONFIG 3 154 # define KN03_SCSI_CONFIG 14 155 # define KN03_SCC0_CONFIG (0x10|4) 156 # define KN03_SCC1_CONFIG (0x10|6) 157 158 #define KN03_REG_SCSI_SCR ( KN03_SYS_ASIC + IOASIC_SCSI_SCR ) 159 #define KN03_REG_SCSI_SDR0 ( KN03_SYS_ASIC + IOASIC_SCSI_SDR0 ) 160 #define KN03_REG_SCSI_SDR1 ( KN03_SYS_ASIC + IOASIC_SCSI_SDR1 ) 161 162 /* NOTES 163 164 Memory access priority is, from higher to lower: 165 - DRAM refresh 166 - IO DMA (IO Control ASIC) 167 - Slot 2 DMA 168 - Slot 1 DMA 169 - Slot 0 DMA 170 - Processor 171 172 */ 173 174 /* 175 * More system registers defines (IO Control ASIC) 176 */ 177 /* (re)defines for the system Status and Control register (SSR) */ 178 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ 179 #define KN03_CSR_LEDS 0x000000ff /* rw */ 180 #define KN03_CSR_BNK32M 0x00000400 /* rw Memory bank stride */ 181 #define KN03_CSR_CORRECT 0x00002000 /* rw ECC corrects single bit */ 182 #define KN03_CSR_ECCMD 0x0000c000 /* rw ECC logic mode */ 183 184 /* (re)defines for the System Interrupt and Mask Registers */ 185 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ 186 #define KN03_INTR_PBNO 0x00000001 /* ro */ 187 #define KN03_INTR_PBNC 0x00000002 /* ro */ 188 #define KN03_INTR_SCSI_FIFO 0x00000004 /* ro */ 189 #define KN03_INTR_PSWARN 0x00000010 /* ro */ 190 #define KN03_INTR_CLOCK 0x00000020 /* ro */ 191 #define KN03_INTR_SCC_0 0x00000040 /* ro */ 192 #define KN03_INTR_SCC_1 0x00000080 /* ro */ 193 #define KN03_INTR_LANCE 0x00000100 /* ro */ 194 #define KN03_INTR_SCSI 0x00000200 /* ro */ 195 #define KN03_INTR_NRMOD_JUMPER 0x00000400 /* ro */ 196 #define KN03_INTR_TC_0 0x00000800 /* ro */ 197 #define KN03_INTR_TC_1 0x00001000 /* ro */ 198 #define KN03_INTR_TC_2 0x00002000 /* ro */ 199 #define KN03_INTR_NVR_JUMPER 0x00004000 /* ro */ 200 #define KN03_INTR_PROD_JUMPER 0x00008000 /* ro */ 201 202 #define KN03_INTR_ASIC 0xff0f0004 203 #define KN03_IM0 0xff0f3bf0 /* all good ones enabled */ 204 205 /* 206 * Error Address Register Bit Definitions 207 */ 208 #define KN03_ERR_ADDRESS 0x07ffffff /* phys address */ 209 #define KN03_ERR_RESERVED 0x08000000 /* unused */ 210 #define KN03_ERR_ECCERR 0x10000000 /* ECC error */ 211 #define KN03_ERR_WRITE 0x20000000 /* read/write transaction */ 212 #define KN03_ERR_CPU 0x40000000 /* CPU or device initiator */ 213 #define KN03_ERR_VALID 0x80000000 /* Info is valid */ 214 215 /* ECC check/syndrome status register */ 216 #define KN03_ECC_SYNLO 0x0000007f /* syndrome, even bank */ 217 #define KN03_ECC_SNGLO 0x00000080 /* single bit err, " */ 218 #define KN03_ECC_CHKLO 0x00007f00 /* check bits, " " */ 219 #define KN03_ECC_VLDLO 0x00008000 /* info valid for " */ 220 #define KN03_ECC_SYNHI 0x007f0000 /* syndrome, odd bank */ 221 #define KN03_ECC_SNGHI 0x00800000 /* single bit err, " */ 222 #define KN03_ECC_CHKHI 0x7f000000 /* check bits, " " */ 223 #define KN03_ECC_VLDHI 0x80000000 /* info valid for " */ 224 225 #endif /* MIPS_KN03_H */ 226