1 /* $NetBSD: maxine.h,v 1.8 2000/02/29 04:41:57 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * The Mach Operating System project at Carnegie-Mellon University, 9 * Ralph Campbell and Rick Macklem. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)maxine.h 8.1 (Berkeley) 6/10/93 40 */ 41 42 /* 43 * Mach Operating System 44 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 45 * All Rights Reserved. 46 * 47 * Permission to use, copy, modify and distribute this software and 48 * its documentation is hereby granted, provided that both the copyright 49 * notice and this permission notice appear in all copies of the 50 * software, derivative works or modified versions, and any portions 51 * thereof, and that both notices appear in supporting documentation. 52 * 53 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 54 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 55 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 56 * 57 * Carnegie Mellon requests users of this software to return to 58 * 59 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 60 * School of Computer Science 61 * Carnegie Mellon University 62 * Pittsburgh PA 15213-3890 63 * 64 * any improvements or extensions that they make and grant Carnegie the 65 * rights to redistribute these changes. 66 */ 67 /* 68 * HISTORY 69 * Log: maxine.h,v 70 * Revision 2.3 92/04/01 15:14:52 rpd 71 * Defined pseudo slot for mappable timer. 72 * [92/03/11 02:37:41 af] 73 * 74 * Revision 2.2 92/03/02 18:34:28 rpd 75 * Created, from the DEC specs: 76 * "MAXine System Module Functional Specification" Revision 1.2 77 * Workstation Systems Engineering, Palo Alto, CA. July 15, 1991. 78 * [92/01/17 af] 79 * 80 */ 81 /* 82 * File: maxine.h 83 * Author: Alessandro Forin, Carnegie Mellon University 84 * Date: 1/92 85 * 86 * Definitions specific to the MAXine system module (54-21325-01) 87 * and compatible processors (KN02BA). 88 */ 89 90 #ifndef MIPS_XINE_H 91 #define MIPS_XINE_H 1 92 93 /* 94 * MAXine's Physical address space 95 */ 96 #define XINE_PHYS_MIN 0x00000000 /* 512 Meg */ 97 #define XINE_PHYS_MAX 0x1fffffff 98 99 /* 100 * Memory map 101 */ 102 #define XINE_PHYS_MEMORY_START 0x00000000 103 #define XINE_PHYS_MEMORY_END 0x027fffff /* 40 Meg in 2 slots 104 and baseboard */ 105 106 /* 107 * I/O map 108 */ 109 #define XINE_PHYS_CFB_START 0x08000000 /* Color Frame Buffer */ 110 #define XINE_PHYS_CFB_END 0x0bffffff /* 64 Meg */ 111 112 #define XINE_PHYS_MREGS_START 0x0c000000 /* Memory control registers */ 113 #define XINE_PHYS_MREGS_END 0x0dffffff /* 32 Meg */ 114 #define XINE_PHYS_CREGS_START 0x0e000000 /* CPU ASIC control regs */ 115 #define XINE_PHYS_CREGS_END 0x0fffffff /* 32 Meg */ 116 117 #define XINE_PHYS_TC_0_START 0x10000000 /* TURBOchannel, slot 0 */ 118 #define XINE_PHYS_TC_0_END 0x13ffffff /* 64 Meg, option0 */ 119 120 #define XINE_PHYS_TC_1_START 0x14000000 /* TURBOchannel, slot 1 */ 121 #define XINE_PHYS_TC_1_END 0x17ffffff /* 64 Meg, option1 */ 122 123 #define XINE_PHYS_TC_RESERVED 0x18000000 /* Unused slot 2 */ 124 /* 64 Meg */ 125 126 #define XINE_PHYS_TC_3_START 0x1c000000 /* TURBOchannel, slot 3 */ 127 #define XINE_PHYS_TC_3_END 0x1fffffff /* 64 Meg, system devices */ 128 129 #define XINE_PHYS_TC_START XINE_PHYS_TC_0_START 130 #define XINE_PHYS_TC_END XINE_PHYS_TC_3_END /* 256 Meg */ 131 132 #define XINE_TC_NSLOTS 4 133 #define XINE_TC_MIN 0 134 #define XINE_TC_MAX 1 /* only option slots */ 135 136 /* 137 * System module space 138 */ 139 #define XINE_SYS_ASIC (XINE_PHYS_TC_3_START + 0x0000000) 140 #define XINE_SYS_ROM_START (XINE_SYS_ASIC + IOASIC_SLOT_0_START) 141 #define XINE_SYS_ASIC_REGS (XINE_SYS_ASIC + IOASIC_SLOT_1_START) 142 #define XINE_SYS_ETHER_ADDRESS (XINE_SYS_ASIC + IOASIC_SLOT_2_START) 143 #define XINE_SYS_LANCE (XINE_SYS_ASIC + IOASIC_SLOT_3_START) 144 #define XINE_SYS_SCC_0 (XINE_SYS_ASIC + IOASIC_SLOT_4_START) 145 #define XINE_SYS_VDAC_HI (XINE_SYS_ASIC + IOASIC_SLOT_5_START) 146 #define XINE_SYS_VDAC_LO (XINE_SYS_ASIC + IOASIC_SLOT_7_START) 147 #define XINE_SYS_CLOCK (XINE_SYS_ASIC + IOASIC_SLOT_8_START) 148 #define XINE_SYS_ISDN (XINE_SYS_ASIC + IOASIC_SLOT_9_START) 149 #define XINE_SYS_DTOP (XINE_SYS_ASIC + IOASIC_SLOT_10_START) 150 #define XINE_SYS_FLOPPY (XINE_SYS_ASIC + IOASIC_SLOT_11_START) 151 #define XINE_SYS_SCSI (XINE_SYS_ASIC + IOASIC_SLOT_12_START) 152 #define XINE_SYS_FLOPPY_DMA (XINE_SYS_ASIC + IOASIC_SLOT_13_START) 153 #define XINE_SYS_SCSI_DMA (XINE_SYS_ASIC + IOASIC_SLOT_14_START) 154 #define XINE_SYS_BOOT_ROM_START (XINE_PHYS_TC_3_START + 0x3c00000) 155 #define XINE_SYS_BOOT_ROM_END (XINE_PHYS_TC_3_START + 0x3c40000) 156 157 /* 158 * Interrupts 159 */ 160 #define XINE_INT_FPA IP_LEV7 /* Floating Point coproc */ 161 #define XINE_INT_HALTB IP_LEV6 /* Halt keycode (DTOP) */ 162 #define XINE_INT_TC3 IP_LEV5 /* TC slot 3, system */ 163 #define XINE_INT_TIMEOUT IP_LEV4 /* Timeout on I/O write */ 164 #define XINE_INT_TOY IP_LEV3 /* Clock chip */ 165 #define XINE_INT_1_10_MS IP_LEV2 /* Periodic interrupt */ 166 167 /* 168 * System registers addresses (MREG and CREG space, and IO Control ASIC) 169 */ 170 #define XINE_REG_CMR 0x0c000000 /* Color mask register */ 171 #define XINE_REG_MER 0x0c400000 /* Memory error register */ 172 #define XINE_REG_MSR 0x0c800000 /* Memory size register */ 173 #define XINE_REG_FCTR 0x0ca00000 /* 1us free running counter */ 174 #define XINE_REG_FI 0x0cc00000 /* FI signal polarity (1!) */ 175 176 #define XINE_REG_CNFG 0x0e000000 /* Config mem timeouts */ 177 #define XINE_REG_AER 0x0e000004 /* Address error register */ 178 #define XINE_REG_TIMEOUT 0x0e00000c /* I/O write timeout reg */ 179 180 #define XINE_REG_SCSI_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCSI_DMAPTR ) 181 #define XINE_REG_SCSI_DMANPTR ( XINE_SYS_ASIC + IOASIC_SCSI_NEXTPTR ) 182 #define XINE_REG_LANCE_DMAPTR ( XINE_SYS_ASIC + IOASIC_LANCE_DMAPTR ) 183 #define XINE_REG_SCC_T1_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_T1_DMAPTR ) 184 #define XINE_REG_SCC_R1_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_R1_DMAPTR ) 185 #define XINE_REG_DTOP_T_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_T2_DMAPTR ) 186 #define XINE_REG_DTOP_R_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_R2_DMAPTR ) 187 #define XINE_FLOPPY_DMAPTR ( XINE_SYS_ASIC + IOASIC_FLOPPY_DMAPTR ) 188 #define XINE_ISDN_X_DMAPTR ( XINE_SYS_ASIC + IOASIC_ISDN_X_DMAPTR ) 189 #define XINE_ISDN_X_NEXTPTR ( XINE_SYS_ASIC + IOASIC_ISDN_X_NEXTPTR ) 190 #define XINE_ISDN_R_DMAPTR ( XINE_SYS_ASIC + IOASIC_ISDN_R_DMAPTR ) 191 #define XINE_ISDN_R_NEXTPTR ( XINE_SYS_ASIC + IOASIC_ISDN_R_NEXTPTR ) 192 #define XINE_REG_CSR ( XINE_SYS_ASIC + IOASIC_CSR ) 193 #define XINE_REG_INTR ( XINE_SYS_ASIC + IOASIC_INTR ) 194 #define XINE_REG_IMSK ( XINE_SYS_ASIC + IOASIC_IMSK ) 195 #define XINE_REG_CURADDR ( XINE_SYS_ASIC + IOASIC_CURADDR ) 196 #define XINE_ISDN_X_DATA ( XINE_SYS_ASIC + IOASIC_ISDN_X_DATA ) 197 #define XINE_ISDN_R_DATA ( XINE_SYS_ASIC + IOASIC_ISDN_R_DATA ) 198 199 #define XINE_REG_LANCE_DECODE ( XINE_SYS_ASIC + IOASIC_LANCE_DECODE ) 200 #define XINE_REG_SCSI_DECODE ( XINE_SYS_ASIC + IOASIC_SCSI_DECODE ) 201 #define XINE_REG_SCC0_DECODE ( XINE_SYS_ASIC + IOASIC_SCC0_DECODE ) 202 #define XINE_REG_DTOP_DECODE ( XINE_SYS_ASIC + IOASIC_SCC1_DECODE ) 203 #define XINE_REG_FLOPPY_DECODE ( XINE_SYS_ASIC + IOASIC_FLOPPY_DECODE ) 204 # define XINE_LANCE_CONFIG 3 205 # define XINE_SCSI_CONFIG 14 206 # define XINE_SCC0_CONFIG (0x10|4) 207 # define XINE_DTOP_CONFIG 10 208 # define XINE_FLOPPY_CONFIG 13 209 210 #define XINE_REG_SCSI_SCR ( XINE_SYS_ASIC + IOASIC_SCSI_SCR ) 211 #define XINE_REG_SCSI_SDR0 ( XINE_SYS_ASIC + IOASIC_SCSI_SDR0 ) 212 #define XINE_REG_SCSI_SDR1 ( XINE_SYS_ASIC + IOASIC_SCSI_SDR1 ) 213 214 /* 215 * System registers defines (MREG and CREG) 216 */ 217 /* Memory error register */ 218 #define XINE_MER_xxx 0xf7fe30ff /* undefined */ 219 #define XINE_MER_10_1_MS_IP 0x08000000 /* rw: Periodic interrupt */ 220 #define XINE_MER_PAGE_BRY 0x00010000 /* rw: Page boundary error */ 221 #define XINE_MER_TLEN 0x00008000 /* rw: Xfer length error */ 222 #define XINE_MER_PARDIS 0x00004000 /* rw: Dis parity err intr */ 223 #define XINE_MER_LASTBYTE 0x00000f00 /* rz: Last byte in error: */ 224 # define XINE_LASTB31 0x00000800 /* upper byte of word */ 225 # define XINE_LASTB23 0x00000400 /* .. through .. */ 226 # define XINE_LASTB15 0x00000200 /* .. the .. */ 227 # define XINE_LASTB07 0x00000100 /* .. lower byte */ 228 229 /* Memory size register */ 230 #define XINE_MSR_xxx 0xffffdfff /* undefined */ 231 #define XINE_MSR_10_1_MS_EN 0x04000000 /* rw: enable periodic intr */ 232 #define XINE_MSR_10_1_MS 0x02000000 /* rw: intr. freq. (0->1ms) */ 233 #define XINE_MSR_PFORCE 0x01e00000 /* rw: force parity errors */ 234 #define XINE_MSR_MABEN 0x00100000 /* rw: VRAM ignores SIZE */ 235 #define XINE_MSR_LAST_BANK 0x000e0000 /* rw: map baseboard mem */ 236 # define XINE_BANK_0 0x00020000 /* .. at bank 0, .. */ 237 # define XINE_BANK_1 0x00040000 /* .. at bank 1, .. */ 238 # define XINE_BANK_2 0x00080000 /* .. or at bank 2 */ 239 #define XINE_MSR_SIZE_16Mb 0x00002000 /* rw: using 16Mb mem banks */ 240 241 /* FI register */ 242 #define XINE_FI_VALUE 0x00001000 243 244 /* NOTES 245 246 Memory access priority is, from higher to lower: 247 - VRAM/DRAM refresh 248 - IO DMA (IO Control ASIC) 249 - Slot 0 DMA 250 - Processor 251 - Slot 1 DMA 252 253 Memory performance is (with 80ns mem cycles) 254 - single word read 5 cyc 10.0 Mb/s 255 - word write 3 cyc 16.7 Mb/s 256 - single byte write 3 cyc 4.2 Mb/s 257 - 64w DMA read 68 cyc 47.1 Mb/s 258 - 64w DMA write 66 cyc 48.5 Mb/s 259 - Refresh 5 cyc N/A 260 */ 261 262 /* Timeout config register */ 263 #define XINE_CNFG_VALUE 121 264 265 /* Address error register */ 266 #define XINE_AER_ADDR_MASK 0x1ffffffc /* ro: phys addr in error */ 267 268 /* Memory access timeout interrupt register */ 269 #define XINE_TIMEO_INTR 0x00000001 /* rc: intr pending */ 270 271 /* 272 * More system registers defines (IO Control ASIC) 273 */ 274 /* (re)defines for the system Status and Control register (SSR) */ 275 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ 276 #define XINE_CSR_DIAGDN 0x00008000 /* rw */ 277 #define XINE_CSR_ISDN_ENABLE 0x00001000 /* rw */ 278 #define XINE_CSR_SCC_ENABLE 0x00000800 /* rw */ 279 #define XINE_CSR_RTC_ENABLE 0x00000400 /* rw */ 280 #define XINE_CSR_SCSI_ENABLE 0x00000200 /* rw */ 281 #define XINE_CSR_LANCE_ENABLE 0x00000100 /* rw */ 282 #define XINE_CSR_FLOPPY_ENABLE 0x00000080 /* rw */ 283 #define XINE_CSR_VDAC_ENABLE 0x00000040 /* rw */ 284 #define XINE_CSR_DTOP_ENABLE 0x00000020 /* rw */ 285 #define XINE_CSR_LED 0x00000001 /* rw */ 286 287 /* (re)defines for the System Interrupt and Mask Registers */ 288 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ 289 #define XINE_INTR_xxxx 0x00002808 /* ro */ 290 #define XINE_INTR_FLOPPY 0x00008000 /* ro */ 291 #define XINE_INTR_NVR_JUMPER 0x00004000 /* ro */ 292 #define XINE_INTR_POWERUP 0x00002000 /* ro */ 293 #define XINE_INTR_TC_0 0x00001000 /* ro */ 294 #define XINE_INTR_ISDN 0x00000800 /* ro */ 295 #define XINE_INTR_NRMOD_JUMPER 0x00000400 /* ro */ 296 #define XINE_INTR_SCSI 0x00000200 /* ro */ 297 #define XINE_INTR_LANCE 0x00000100 /* ro */ 298 #define XINE_INTR_FLOPPY_HDS 0x00000080 /* ro */ 299 #define XINE_INTR_SCC_0 0x00000040 /* ro */ 300 #define XINE_INTR_TC_1 0x00000020 /* ro */ 301 #define XINE_INTR_FLOPPY_XDS 0x00000010 /* ro */ 302 #define XINE_INTR_VINT 0x00000008 /* ro */ 303 #define XINE_INTR_N_VINT 0x00000004 /* ro */ 304 #define XINE_INTR_DTOP_TX 0x00000002 /* ro */ 305 #define XINE_INTR_DTOP_RX 0x00000001 /* ro */ 306 #define XINE_INTR_ASIC 0xffff0000 307 #define XINE_INTR_DTOP 0x00000003 308 #define XINE_IM0 0xffff9b6b /* all good ones enabled */ 309 310 #endif /* MIPS_XINE_H */ 311