1 /* $NetBSD: fpu_div.c,v 1.1 2001/06/13 06:01:47 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_div.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * Perform an FPU divide (return x / y). 49 */ 50 51 #include <sys/types.h> 52 #if defined(DIAGNOSTIC)||defined(DEBUG) 53 #include <sys/systm.h> 54 #endif 55 56 #include <machine/reg.h> 57 #include <machine/fpu.h> 58 59 #include <powerpc/fpu/fpu_arith.h> 60 #include <powerpc/fpu/fpu_emu.h> 61 62 /* 63 * Division of normal numbers is done as follows: 64 * 65 * x and y are floating point numbers, i.e., in the form 1.bbbb * 2^e. 66 * If X and Y are the mantissas (1.bbbb's), the quotient is then: 67 * 68 * q = (X / Y) * 2^((x exponent) - (y exponent)) 69 * 70 * Since X and Y are both in [1.0,2.0), the quotient's mantissa (X / Y) 71 * will be in [0.5,2.0). Moreover, it will be less than 1.0 if and only 72 * if X < Y. In that case, it will have to be shifted left one bit to 73 * become a normal number, and the exponent decremented. Thus, the 74 * desired exponent is: 75 * 76 * left_shift = x->fp_mant < y->fp_mant; 77 * result_exp = x->fp_exp - y->fp_exp - left_shift; 78 * 79 * The quotient mantissa X/Y can then be computed one bit at a time 80 * using the following algorithm: 81 * 82 * Q = 0; -- Initial quotient. 83 * R = X; -- Initial remainder, 84 * if (left_shift) -- but fixed up in advance. 85 * R *= 2; 86 * for (bit = FP_NMANT; --bit >= 0; R *= 2) { 87 * if (R >= Y) { 88 * Q |= 1 << bit; 89 * R -= Y; 90 * } 91 * } 92 * 93 * The subtraction R -= Y always removes the uppermost bit from R (and 94 * can sometimes remove additional lower-order 1 bits); this proof is 95 * left to the reader. 96 * 97 * This loop correctly calculates the guard and round bits since they are 98 * included in the expanded internal representation. The sticky bit 99 * is to be set if and only if any other bits beyond guard and round 100 * would be set. From the above it is obvious that this is true if and 101 * only if the remainder R is nonzero when the loop terminates. 102 * 103 * Examining the loop above, we can see that the quotient Q is built 104 * one bit at a time ``from the top down''. This means that we can 105 * dispense with the multi-word arithmetic and just build it one word 106 * at a time, writing each result word when it is done. 107 * 108 * Furthermore, since X and Y are both in [1.0,2.0), we know that, 109 * initially, R >= Y. (Recall that, if X < Y, R is set to X * 2 and 110 * is therefore at in [2.0,4.0).) Thus Q is sure to have bit FP_NMANT-1 111 * set, and R can be set initially to either X - Y (when X >= Y) or 112 * 2X - Y (when X < Y). In addition, comparing R and Y is difficult, 113 * so we will simply calculate R - Y and see if that underflows. 114 * This leads to the following revised version of the algorithm: 115 * 116 * R = X; 117 * bit = FP_1; 118 * D = R - Y; 119 * if (D >= 0) { 120 * result_exp = x->fp_exp - y->fp_exp; 121 * R = D; 122 * q = bit; 123 * bit >>= 1; 124 * } else { 125 * result_exp = x->fp_exp - y->fp_exp - 1; 126 * q = 0; 127 * } 128 * R <<= 1; 129 * do { 130 * D = R - Y; 131 * if (D >= 0) { 132 * q |= bit; 133 * R = D; 134 * } 135 * R <<= 1; 136 * } while ((bit >>= 1) != 0); 137 * Q[0] = q; 138 * for (i = 1; i < 4; i++) { 139 * q = 0, bit = 1 << 31; 140 * do { 141 * D = R - Y; 142 * if (D >= 0) { 143 * q |= bit; 144 * R = D; 145 * } 146 * R <<= 1; 147 * } while ((bit >>= 1) != 0); 148 * Q[i] = q; 149 * } 150 * 151 * This can be refined just a bit further by moving the `R <<= 1' 152 * calculations to the front of the do-loops and eliding the first one. 153 * The process can be terminated immediately whenever R becomes 0, but 154 * this is relatively rare, and we do not bother. 155 */ 156 157 struct fpn * 158 fpu_div(struct fpemu *fe) 159 { 160 struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2; 161 u_int q, bit; 162 u_int r0, r1, r2, r3, d0, d1, d2, d3, y0, y1, y2, y3; 163 FPU_DECL_CARRY 164 165 /* 166 * Since divide is not commutative, we cannot just use ORDER. 167 * Check either operand for NaN first; if there is at least one, 168 * order the signalling one (if only one) onto the right, then 169 * return it. Otherwise we have the following cases: 170 * 171 * Inf / Inf = NaN, plus NV exception 172 * Inf / num = Inf [i.e., return x] 173 * Inf / 0 = Inf [i.e., return x] 174 * 0 / Inf = 0 [i.e., return x] 175 * 0 / num = 0 [i.e., return x] 176 * 0 / 0 = NaN, plus NV exception 177 * num / Inf = 0 178 * num / num = num (do the divide) 179 * num / 0 = Inf, plus DZ exception 180 */ 181 DPRINTF(FPE_REG, ("fpu_div:\n")); 182 DUMPFPN(FPE_REG, x); 183 DUMPFPN(FPE_REG, y); 184 DPRINTF(FPE_REG, ("=>\n")); 185 if (ISNAN(x) || ISNAN(y)) { 186 ORDER(x, y); 187 fe->fe_cx |= FPSCR_VXSNAN; 188 DUMPFPN(FPE_REG, y); 189 return (y); 190 } 191 /* 192 * Need to split the following out cause they generate different 193 * exceptions. 194 */ 195 if (ISINF(x)) { 196 if (x->fp_class == y->fp_class) { 197 fe->fe_cx |= FPSCR_VXIDI; 198 return (fpu_newnan(fe)); 199 } 200 DUMPFPN(FPE_REG, x); 201 return (x); 202 } 203 if (ISZERO(x)) { 204 fe->fe_cx |= FPSCR_ZX; 205 if (x->fp_class == y->fp_class) { 206 fe->fe_cx |= FPSCR_VXZDZ; 207 return (fpu_newnan(fe)); 208 } 209 DUMPFPN(FPE_REG, x); 210 return (x); 211 } 212 213 /* all results at this point use XOR of operand signs */ 214 x->fp_sign ^= y->fp_sign; 215 if (ISINF(y)) { 216 x->fp_class = FPC_ZERO; 217 DUMPFPN(FPE_REG, x); 218 return (x); 219 } 220 if (ISZERO(y)) { 221 fe->fe_cx = FPSCR_ZX; 222 x->fp_class = FPC_INF; 223 DUMPFPN(FPE_REG, x); 224 return (x); 225 } 226 227 /* 228 * Macros for the divide. See comments at top for algorithm. 229 * Note that we expand R, D, and Y here. 230 */ 231 232 #define SUBTRACT /* D = R - Y */ \ 233 FPU_SUBS(d3, r3, y3); FPU_SUBCS(d2, r2, y2); \ 234 FPU_SUBCS(d1, r1, y1); FPU_SUBC(d0, r0, y0) 235 236 #define NONNEGATIVE /* D >= 0 */ \ 237 ((int)d0 >= 0) 238 239 #ifdef FPU_SHL1_BY_ADD 240 #define SHL1 /* R <<= 1 */ \ 241 FPU_ADDS(r3, r3, r3); FPU_ADDCS(r2, r2, r2); \ 242 FPU_ADDCS(r1, r1, r1); FPU_ADDC(r0, r0, r0) 243 #else 244 #define SHL1 \ 245 r0 = (r0 << 1) | (r1 >> 31), r1 = (r1 << 1) | (r2 >> 31), \ 246 r2 = (r2 << 1) | (r3 >> 31), r3 <<= 1 247 #endif 248 249 #define LOOP /* do ... while (bit >>= 1) */ \ 250 do { \ 251 SHL1; \ 252 SUBTRACT; \ 253 if (NONNEGATIVE) { \ 254 q |= bit; \ 255 r0 = d0, r1 = d1, r2 = d2, r3 = d3; \ 256 } \ 257 } while ((bit >>= 1) != 0) 258 259 #define WORD(r, i) /* calculate r->fp_mant[i] */ \ 260 q = 0; \ 261 bit = 1 << 31; \ 262 LOOP; \ 263 (x)->fp_mant[i] = q 264 265 /* Setup. Note that we put our result in x. */ 266 r0 = x->fp_mant[0]; 267 r1 = x->fp_mant[1]; 268 r2 = x->fp_mant[2]; 269 r3 = x->fp_mant[3]; 270 y0 = y->fp_mant[0]; 271 y1 = y->fp_mant[1]; 272 y2 = y->fp_mant[2]; 273 y3 = y->fp_mant[3]; 274 275 bit = FP_1; 276 SUBTRACT; 277 if (NONNEGATIVE) { 278 x->fp_exp -= y->fp_exp; 279 r0 = d0, r1 = d1, r2 = d2, r3 = d3; 280 q = bit; 281 bit >>= 1; 282 } else { 283 x->fp_exp -= y->fp_exp + 1; 284 q = 0; 285 } 286 LOOP; 287 x->fp_mant[0] = q; 288 WORD(x, 1); 289 WORD(x, 2); 290 WORD(x, 3); 291 x->fp_sticky = r0 | r1 | r2 | r3; 292 293 DUMPFPN(FPE_REG, x); 294 return (x); 295 } 296