1 /* $NetBSD: emacreg.h,v 1.1 2002/08/13 04:57:48 simonb Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge and Eduardo Horvath for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _IBM4XX_EMACREG_H_ 39 #define _IBM4XX_EMACREG_H_ 40 41 /* Ethernet MAC Registers */ 42 #define EMAC_MR0 0x00 /* Mode Register 0 */ 43 #define MR0_RXI 0x80000000 /* Receive MAC Idle */ 44 #define MR0_TXI 0x40000000 /* Transmit MAC Idle */ 45 #define MR0_SRST 0x20000000 /* Soft Reset */ 46 #define MR0_TXE 0x10000000 /* Transmit MAC Enable */ 47 #define MR0_RXE 0x08000000 /* Receive MAC Enable */ 48 #define MR0_WKE 0x04000000 /* Wake-up Enable */ 49 50 #define EMAC_MR1 0x04 /* Mode Register 1 */ 51 #define MR1_FDE 0x80000000 /* Full-Duplex Enable */ 52 #define MR1_ILE 0x40000000 /* Internal Loop-back Enable */ 53 #define MR1_VLE 0x20000000 /* VLAN Enable */ 54 #define MR1_EIFC 0x10000000 /* Enable Integrated Flow Control */ 55 #define MR1_APP 0x08000000 /* Allow Pause Packet */ 56 #define MR1_IST 0x01000000 /* Ignore SQE Test */ 57 #define MR1_MF_MASK 0x00c00000 /* Medium Frequency mask */ 58 #define MR1_MF_10MBS 0x00000000 /* 10MB/sec */ 59 #define MR1_MF_100MBS 0x00400000 /* 100MB/sec */ 60 #define MR1_RFS_MASK 0x00300000 /* Receive FIFO size */ 61 #define MR1_RFS_512 0x00000000 /* 512 bytes */ 62 #define MR1_RFS_1KB 0x00100000 /* 1kByte */ 63 #define MR1_RFS_2KB 0x00200000 /* 2kByte */ 64 #define MR1_RFS_4KB 0x00300000 /* 4kByte */ 65 #define MR1_TFS_MASK 0x000c0000 /* Transmit FIFO size */ 66 #define MR1_TFS_1KB 0x00040000 /* 1kByte */ 67 #define MR1_TFS_2KB 0x00080000 /* 2kByte */ 68 #define MR1_TR0_MASK 0x00018000 /* Transmit Request 0 */ 69 #define MR1_TR0_SINGLE 0x00000000 /* Single Packet mode */ 70 #define MR1_TR0_MULTIPLE 0x00008000 /* Multiple Packet mode */ 71 #define MR1_TR0_DEPENDANT 0x00010000 /* Dependent Mode */ 72 #define MR1_TR1_MASK 0x00006000 /* Transmit Request 1 */ 73 #define MR1_TR1_SINGLE 0x00000000 /* Single Packet mode */ 74 #define MR1_TR1_MULTIPLE 0x00002000 /* Multiply Packet mode */ 75 #define MR1_TR1_DEPENDANT 0x00004000 /* Dependent Mode */ 76 77 #define EMAC_TMR0 0x08 /* Transmit Mode Register 0 */ 78 #define TMR0_GNP0 0x80000000 /* Get New Packet for Channel 0 */ 79 #define TMR0_GNP1 0x40000000 /* Get New Packet for Channel 1 */ 80 #define TMR0_GNPD 0x20000000 /* Get New Packet for Dependent mode */ 81 #define TMR0_FC_MASK 0x10000000 /* First Channel */ 82 #define TMR0_FC_CHAN0 0x00000000 /* Channel 0 */ 83 #define TMR0_FC_CHAN1 0x10000000 /* Channel 1 */ 84 85 #define EMAC_TMR1 0x0c /* Transmit Mode Register 1 */ 86 #define TMR1_TLR_MASK 0xf8000000 /* Transmit Low Request */ 87 #define TMR1_TLR_SHIFT 27 88 #define TMR1_TUR_MASK 0x00ff0000 /* Transmit Urgent Request */ 89 #define TMR1_TUR_SHIFT 16 90 91 #define EMAC_RMR 0x10 /* Receive Mode Register */ 92 #define RMR_SP 0x80000000 /* Strip Padding */ 93 #define RMR_SFCS 0x40000000 /* Strip FCS */ 94 #define RMR_RRP 0x20000000 /* Receive Runt Packets */ 95 #define RMR_RFP 0x10000000 /* Receive FCS Packets */ 96 #define RMR_ROP 0x08000000 /* Receive Oversize Packets */ 97 #define RMR_RPIR 0x04000000 /* Receive Packets with In Range Error */ 98 #define RMR_PPP 0x02000000 /* Propagate Pause Packet */ 99 #define RMR_PME 0x01000000 /* Promiscuous Mode Enable */ 100 #define RMR_PMME 0x00800000 /* Promiscuous Multicast Mode Enable */ 101 #define RMR_IAE 0x00400000 /* Individual Address Enable */ 102 #define RMR_MIAE 0x00200000 /* Multiple Individual Address Enable */ 103 #define RMR_BAE 0x00100000 /* Broadcast Address Enable */ 104 #define RMR_MAE 0x00080000 /* Multicast Address Enable */ 105 106 #define EMAC_ISR 0x14 /* Interrupt Status Register */ 107 #define ISR_OVR 0x02000000 /* Overrun Error */ 108 #define ISR_PP 0x01000000 /* Pause Packet */ 109 #define ISR_BP 0x00800000 /* Bad Packet */ 110 #define ISR_RP 0x00400000 /* Runt Packet */ 111 #define ISR_SE 0x00200000 /* Short Event */ 112 #define ISR_ALE 0x00100000 /* Alignment Error */ 113 #define ISR_BFCS 0x00080000 /* Bad FCS */ 114 #define ISR_PTLE 0x00040000 /* Packet Too Long Error */ 115 #define ISR_ORE 0x00020000 /* Out of Range Error */ 116 #define ISR_IRE 0x00010000 /* In Range Error */ 117 #define ISR_DBDM 0x00000200 /* Dead Bit Dependent Mode */ 118 #define ISR_DB0 0x00000100 /* Dead Bit 0 */ 119 #define ISR_SE0 0x00000080 /* SQE Error 0 */ 120 #define ISR_TE0 0x00000040 /* Transmit Error 0 */ 121 #define ISR_DB1 0x00000020 /* Dead Bit 1 */ 122 #define ISR_SE1 0x00000010 /* SQE Error 1 */ 123 #define ISR_TE1 0x00000008 /* Transmit Error 1 */ 124 #define ISR_MOS 0x00000002 /* MMA Operation Succeeded */ 125 #define ISR_MOF 0x00000001 /* MMA Operation Failed */ 126 127 #define EMAC_ISER 0x18 /* Interrupt Status Enable Register */ 128 #define ISER_OVR ISR_OVR 129 #define ISER_PP ISR_PP 130 #define ISER_BP ISR_BP 131 #define ISER_RP ISR_RP 132 #define ISER_SE ISR_SE 133 #define ISER_ALE ISR_ALE 134 #define ISER_BFCS ISR_BFCS 135 #define ISER_PTLE ISR_PTLE 136 #define ISER_ORE ISR_ORE 137 #define ISER_IRE ISR_IRE 138 #define ISER_DBDM ISR_DBDM 139 #define ISER_DB0 ISR_DB0 140 #define ISER_SE0 ISR_SE0 141 #define ISER_TE0 ISR_TE0 142 #define ISER_DB1 ISR_DB1 143 #define ISER_SE1 ISR_SE1 144 #define ISER_TE1 ISR_TE1 145 #define ISER_MOS ISR_MOS 146 #define ISER_MOF ISR_MOF 147 148 #define EMAC_IAHR 0x1c /* Individual Address High Register */ 149 #define EMAC_IALR 0x20 /* Individual Address Low Register */ 150 #define EMAC_VTPID 0x24 /* VLAN TPID Register */ 151 #define EMAC_VTCI 0x28 /* VLAN TCI Register */ 152 #define EMAC_PTR 0x2c /* Pause Timer Register */ 153 #define EMAC_IAHT1 0x30 /* Individual Address Hash Table 1 */ 154 #define EMAC_IAHT2 0x34 /* Individual Address Hash Table 2 */ 155 #define EMAC_IAHT3 0x38 /* Individual Address Hash Table 3 */ 156 #define EMAC_IAHT4 0x3c /* Individual Address Hash Table 4 */ 157 #define EMAC_GAHT1 0x40 /* Group Address Hash Table 1 */ 158 #define EMAC_GAHT2 0x44 /* Group Address Hash Table 2 */ 159 #define EMAC_GAHT3 0x48 /* Group Address Hash Table 3 */ 160 #define EMAC_GAHT4 0x4c /* Group Address Hash Table 4 */ 161 #define EMAC_LSAH 0x50 /* Last Source Address High */ 162 #define EMAC_LSAL 0x54 /* Last Source Address Low */ 163 #define EMAC_IPGVR 0x58 /* Inter-Packet Gap Value Register */ 164 165 #define EMAC_STACR 0x5c /* STA Control Register */ 166 #define STACR_PHYD 0xffff0000 /* PHY data mask */ 167 #define STACR_PHYDSHIFT 16 168 #define STACR_OC 0x00008000 /* operation complete */ 169 #define STACR_PHYE 0x00004000 /* PHY error */ 170 #define STACR_WRITE 0x00002000 /* STA command - write */ 171 #define STACR_READ 0x00001000 /* STA command - read */ 172 #define STACR_OPBC_MASK 0x00000c00 /* OPB bus clock freq mask */ 173 #define STACR_OPBC_50MHZ 0x00000000 /* OPB bus clock freq - 50MHz */ 174 #define STACR_OPBC_66MHZ 0x00000400 /* OPB bus clock freq - 66MHz */ 175 #define STACR_OPBC_83MHZ 0x00000800 /* OPB bus clock freq - 83MHz */ 176 #define STACR_OPBC_100MHZ 0x00000c00 /* OPB bus clock freq - 100MHz */ 177 #define STACR_PCDA 0x000003e0 /* PHY cmd dest address mask */ 178 #define STACR_PCDASHIFT 5 179 #define STACR_PRA 0x0000001f /* PHY register address mask */ 180 #define STACR_PRASHIFT 0 181 182 #define EMAC_TRTR 0x60 /* Transmit Request Threshold Register */ 183 #define TRTR_64 0x00000000 /* 64 bytes */ 184 #define TRTR_128 0x08000000 /* 128 bytes */ 185 #define TRTR_192 0x10000000 /* 192 bytes */ 186 #define TRTR_256 0x18000000 /* 256 bytes */ 187 /* ... and so on +64 until ... */ 188 #define TRTR_2048 0xf8000000 /* 2048 bytes */ 189 190 #define EMAC_RWMR 0x64 /* Receive Low/High Water Mark Register */ 191 #define RWMR_RLWM_MASK 0xff800000 /* Receive Low Water Mark */ 192 #define RWMR_RLWM_SHIFT 23 193 #define RWMR_RHWM_MASK 0x0000ff80 /* Receive High Water Mark */ 194 #define RWMR_RHWM_SHIFT 7 195 196 #define EMAC_OCTX 0x68 /* Number of Octets Transmitted */ 197 #define EMAC_OCRX 0x6c /* Number of Octets Received */ 198 #endif /* _IBM4XX_EMACREG_H_ */ 199