1 /* $NetBSD: e500reg.h,v 1.2 2011/01/18 01:02:54 matt Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 #ifdef _LOCORE 40 #define __PPCBIT(n) (1 << (31 - (n))) 41 #define __PPCBITS(m, n) (((1 << ((n) - (m) + 1)) - 1) << (31 - (m))) 42 #else 43 #define __PPCBIT(n) __BIT(31-(n)) 44 #define __PPCBITS(m,n) __BITS(31-(n),31-(m)) 45 #endif 46 47 #define GUR_SIZE 0x100000 48 49 #define DDRC1_BASE 0x02000 50 #define DDRC2_BASE 0x06000 51 #define DDRC_SIZE 0x01000 52 53 #ifdef DDRC_PRIVATE 54 #define CS_BNDS(n) (0x000 + 0x008 * (n)) 55 #define BNDS_SA __PPCBITS(4,15) 56 #define BNDS_SA_GET(n) (((n) & BNDS_SA) << 8) 57 #define BNDS_EA __PPCBITS(20,31) 58 #define BNDS_EA_GET(n) (((n) & BNDS_EA) << 24) 59 #define BNDS_SIZE_GET(n) \ 60 ((((((n) & BNDS_EA) + __LOWEST_SET_BIT(BNDS_EA)) << 16) - (((n) & BNDS_SA))) << 8) 61 #define CS_CONFIG(n) (0x080 + 0x004 * (n)) 62 #define CS_CONFIG_EN __PPCBIT(0) 63 #endif /* DDRC_PRIVATE */ 64 65 #define GPIO_BASE 0x0fc00 66 #define GPIO_SIZE 0x00020 67 68 #ifdef GPIO_PRIVATE 69 70 #define GPDIR 0x00 /* GPIO direction register */ 71 #define GPODR 0x04 /* GPIO open drain register */ 72 #define GPDAT 0x08 /* GPIO data register */ 73 #define GPIER 0x0C /* GPIO interrupt event register */ 74 #define GPIMR 0x10 /* GPIO interrupt mask register */ 75 #define GPICR 0x14 /* GPIO external interrupt control register */ 76 77 #endif /* GPIO_PRIVATE */ 78 79 #define PCIE1_BASE 0x0a000 80 #define PCIE2_MPC8572_BASE 0x09000 81 #define PCIE3_MPC8572_BASE 0x08000 82 #define PCIX1_MPC8548_BASE 0x08000 83 #define PCIX2_MPC8548_BASE 0x09000 84 #define PCIE2_MPC8544_BASE 0x09000 /* MPC8536 too */ 85 #define PCIE3_MPC8544_BASE 0x0b000 /* MPC8536 too */ 86 #define PCIX1_MPC8544_BASE 0x08000 /* MPC8536 too */ 87 #define PCI_SIZE 0x01000 88 89 #ifdef PCI_PRIVATE 90 91 /* PCI Express Configuration Access Registers */ 92 #define PEX_CONFIG_ADDR 0x000 /* PCI Express configuration address register */ 93 #define PCI_CONFIG_ADDR PEX_CONFIG_ADDR 94 #define PEX_CONFIG_ADDR_EN __PPCBIT(0) 95 #define PEX_CONFIG_ADDR_TAG(b,d,f,r) (((b) << 16) | ((d) << 11) | ((f) << 8) | (r)) 96 #define PEX_CONFIG_DATA 0x004 /* PCI Express configuration data register */ 97 #define PCI_CONFIG_DATA PEX_CONFIG_DATA 98 #define PCI_INT_ACK 0x008 /* PCI Interrupt Acknowledge */ 99 #define PEX_OTB_CPL_TOR 0x00C /* PCI Express outbound completion timeout register */ 100 #define PEX_CONF_RTY_TOR 0x010 /* PCI Express configuration retry timeout register */ 101 #define PEX_CONFIG 0x014 /* PCI Express configuration register */ 102 103 /* PCI Express Power Management Event & Message Registers */ 104 #define PEX_PME_MES_DR 0x020 /* PCI Express PME & message detect register */ 105 #define PEX_PME_MES_DISR 0x024 /* PCI Express PME & message disable register */ 106 #define PEX_PME_MES_IER 0x028 /* PCI Express PME & message interrupt enable register */ 107 #define PEX_PMCR 0x02C /* PCI Express power management command register */ 108 109 /* PCI Express IP Block Revision Registers */ 110 #define PEX_IP_BLK_REV1 0xBF8 /* IP block revision register 1 */ 111 #define PEX_IP_BLK_REV2 0xBFC /* IP block revision register 2 */ 112 113 /* PCI Express / PCI-X ATMU Registers */ 114 #define PEXOWAR_EN __PPCBIT(0) /* enable window */ 115 #define PEXOWAR_ROE __PPCBIT(3) /* relaxed ordering enable */ 116 #define PEXOWAR_NS __PPCBIT(4) /* no snoop enable */ 117 #define PEXOWAR_TC __PPCBITS(8,10) /* traffic class PCIEX only */ 118 #define PEXOWAR_TC0 __SHIFTIN(0, PEXOWAR_TC) 119 #define PEXOWAR_TC1 __SHIFTIN(1, PEXOWAR_TC) 120 #define PEXOWAR_TC2 __SHIFTIN(2, PEXOWAR_TC) 121 #define PEXOWAR_TC3 __SHIFTIN(3, PEXOWAR_TC) 122 #define PEXOWAR_TC4 __SHIFTIN(4, PEXOWAR_TC) 123 #define PEXOWAR_TC5 __SHIFTIN(5, PEXOWAR_TC) 124 #define PEXOWAR_TC6 __SHIFTIN(6, PEXOWAR_TC) 125 #define PEXOWAR_TC7 __SHIFTIN(7, PEXOWAR_TC) 126 #define PEXOWAR_RTT __PPCBITS(12,15) /* read transaction type */ 127 #define PEXOWAR_RTT_CONF __SHIFTIN(2, PEXOWAR_RTT) /* PCIEX only */ 128 #define PEXOWAR_RTT_MEM __SHIFTIN(4, PEXOWAR_RTT) 129 #define PEXOWAR_RTT_IO __SHIFTIN(8, PEXOWAR_RTT) 130 #define PEXOWAR_WTT __PPCBITS(16,19) /* write transaction type */ 131 #define PEXOWAR_WTT_CONF __SHIFTIN(2, PEXOWAR_WTT) /* PCIEX only */ 132 #define PEXOWAR_WTT_MEM __SHIFTIN(4, PEXOWAR_WTT) 133 #define PEXOWAR_WTT_IO __SHIFTIN(8, PEXOWAR_WTT) 134 #define PEXOWAR_OWS __PPCBITS(26,31) /* encoded as 2^(N+1) bytes */ 135 136 /* PCI Express / PCI-X ATMU Registers */ 137 #define PEXIWAR_EN __PPCBIT(0) /* enable window */ 138 #define PEXIWAR_PF __PPCBIT(3) /* prefetchable */ 139 #define PEXIWAR_TRGT __PPCBITS(8,11) /* traffic class PCIEX only */ 140 #define PEXIWAR_TRGT_PCI1 __SHIFTIN(0, PEXIWAR_TRGT) 141 #define PEXIWAR_TRGT_PCI2 __SHIFTIN(1, PEXIWAR_TRGT) 142 #define PEXIWAR_TRGT_PCIEX __SHIFTIN(2, PEXIWAR_TRGT) 143 #define PEXIWAR_TRGT_SRIO __SHIFTIN(12, PEXIWAR_TRGT) 144 #define PEXIWAR_TRGT_LOCALMEM __SHIFTIN(15, PEXIWAR_TRGT) 145 #define PEXIWAR_RTT __PPCBITS(12,15) /* read transaction type */ 146 #define PEXIWAR_RTT_MEM __SHIFTIN(4, PEXIWAR_RTT) 147 #define PEXIWAR_RTT_MEM_NOSNOOP __SHIFTIN(4, PEXIWAR_RTT) 148 #define PEXIWAR_RTT_MEM_SNOOP __SHIFTIN(5, PEXIWAR_RTT) 149 #define PEXIWAR_RTT_MEM_ULCKL2 __SHIFTIN(7, PEXIWAR_RTT) 150 #define PEXIWAR_WTT __PPCBITS(16,19) /* write transaction type */ 151 #define PEXIWAR_WTT_MEM_NOSNOOP __SHIFTIN(4, PEXIWAR_WTT) 152 #define PEXIWAR_WTT_MEM_SNOOP __SHIFTIN(5, PEXIWAR_WTT) 153 #define PEXIWAR_WTT_MEM_ALLOL2 __SHIFTIN(6, PEXIWAR_WTT) 154 #define PEXIWAR_WTT_MEM_ALCKL2 __SHIFTIN(7, PEXIWAR_WTT) 155 #define PEXIWAR_IWS __PPCBITS(26,31) /* encoded as 2^(N+1) bytes */ 156 #define PEXIWAR_IWS_GET(n) __SHIFTOUT((n), PEXIWAR_IWS) 157 158 /* Outbound Window 0 (Default) */ 159 #define PEXOTAR0 0xC00 /* PCI Express outbound translation address register 0 (default) */ 160 #define PEXOTEAR0 0xC04 /* PCI Express outbound translation extended address register 0 (default) */ 161 #define PEXOWAR0 0xC10 /* PCI Express outbound window attributes register 0 (default) */ 162 163 /* Outbound Window 1 */ 164 #define PEXOTAR1 0xC20 /* PCI Express outbound translation address register 1 */ 165 #define PEXOTEAR1 0xC24 /* PCI Express outbound translation extended address register 1 */ 166 #define PEXOWBAR1 0xC28 /* PCI Express outbound window base address register 1 */ 167 #define PEXOWAR1 0xC30 /* PCI Express outbound window attributes register 1 */ 168 169 /* Outbound Window 2 */ 170 #define PEXOTAR2 0xC40 /* PCI Express outbound translation address register 2 */ 171 #define PEXOTEAR2 0xC44 /* PCI Express outbound translation extended address register 2 */ 172 #define PEXOWBAR2 0xC48 /* PCI Express outbound window base address register 2 */ 173 #define PEXOWAR2 0xC50 /* PCI Express outbound window attributes register 2 */ 174 175 /* Outbound Window 3 */ 176 #define PEXOTAR3 0xC60 /* PCI Express outbound translation address register 3 */ 177 #define PEXOTEAR3 0xC64 /* PCI Express outbound translation extended address register 3 */ 178 #define PEXOWBAR3 0xC68 /* PCI Express outbound window base address register 3 */ 179 #define PEXOWAR3 0xC70 /* PCI Express outbound window attributes register 3 */ 180 181 /* Outbound Window 4 */ 182 #define PEXOTAR4 0xC80 /* PCI Express outbound translation address register 4 */ 183 #define PEXOTEAR4 0xC84 /* PCI Express outbound translation extended address register 4 */ 184 #define PEXOWBAR4 0xC88 /* PCI Express outbound window base address register 4 */ 185 #define PEXOWAR4 0xC90 /* PCI Express outbound window attributes register 4 */ 186 187 /* Inbound Window 3 */ 188 #define PEXITAR3 0xDA0 /* PCI Express inbound translation address register 3 */ 189 #define PEXIWBAR3 0xDA8 /* PCI Express inbound window base address register 3 */ 190 #define PEXIWBEAR3 0xDAC /* PCI Express inbound window base extended address register 3 */ 191 #define PEXIWAR3 0xDB0 /* PCI Express inbound window attributes register 3 */ 192 193 /* Inbound Window 2 */ 194 #define PEXITAR2 0xDC0 /* PCI Express inbound translation address register 2 */ 195 #define PEXIWBAR2 0xDC8 /* PCI Express inbound window base address register 2 */ 196 #define PEXIWBEAR2 0xDCC /* PCI Express inbound window base extended address register 2 */ 197 #define PEXIWAR2 0xDD0 /* PCI Express inbound window attributes register 2 */ 198 199 /* Inbound Window 1 */ 200 #define PEXITAR1 0xDE0 /* PCI Express inbound translation address register 1 */ 201 #define PEXIWBAR1 0xDE8 /* PCI Express inbound window base address register 1 */ 202 #define PEXIWAR1 0xDF0 /* PCI Express inbound window attributes register 1 */ 203 204 /* PCI Express Error Management Registers */ 205 #define PEX_ERR_DR 0xE00 /* PCI Express error detect register */ 206 #define PEXERRDR_ICCA __PPCBIT(14) 207 #define PEX_ERR_EN 0xE08 /* PCI Express error interrupt enable register */ 208 #define PEX_ERR_DISR 0xE10 /* PCI Express error disable register */ 209 #define PEX_ERR_CAP_STAT 0xE20 /* PCI Express error capture status register */ 210 #define PEX_ERR_CAP_R0 0xE28 /* PCI Express error capture register 0 */ 211 #define PEX_ERR_CAP_R1 0xE2C /* PCI Express error capture register 1 */ 212 #define PEX_ERR_CAP_R2 0xE30 /* PCI Express error capture register 2 */ 213 #define PEX_ERR_CAP_R3 0xE34 /* PCI Express error capture register 3 */ 214 215 /* PCI Express Private Configuration Space */ 216 217 #define PEX_LTSSM 0x404 218 #define LTSSM_L0 16 219 220 #define PCI_PBFR 0x44 /* Bus Function Register */ 221 #define PBFR_PAH __BIT(0) 222 223 #endif /* PCI_PRIVATE */ 224 225 #define OPENPIC_BASE 0x40000 226 #define OPENPIC_SIZE 0x40000 227 228 #define L2CACHE_BASE 0x20000 229 #define L2CACHE_SIZE 0x01000 230 231 #ifdef L2CACHE_PRIVATE 232 #define L2CTL 0x000 233 #define L2CTL_L2E __PPCBIT(0) 234 #define L2CTL_L2I __PPCBIT(1) 235 #define L2CTL_L2SIZ __PPCBITS(2,3) 236 #define L2CTL_L2SIZ_GET(x) (1 << (17 + __SHIFTOUT((x), L2CTL_L2SIZ))) 237 #define L2CTL_L2DO __PPCBIT(9) 238 #define L2CTL_L2IO __PPCBIT(10) 239 #define L2CTL_L2INTDIS __PPCBIT(12) 240 #define L2CTL_L2SRAM __PPCBITS(13,15) 241 #define L2CTL_L2LO __PPCBIT(18) 242 #define L2CTL_L2SLC __PPCBIT(19) 243 #define L2CTL_L2LFR __PPCBIT(21) 244 #define L2CTL_L2LFRID __PPCBITS(22,23) 245 #define L2CTL_L2STASHDIS __PPCBIT(28) 246 #define L2CTL_L2STASH __PPCBITS(30,31) 247 248 #endif /* L2CACHE_PRIVATE */ 249 250 #define I2C1_BASE 0x3000 251 #define I2C2_BASE 0x3100 252 #define I2C_SIZE 0x0100 253 254 #ifdef I2C_PRIVATE 255 #define I2CADR 0x000 /* i2c address register */ 256 #define I2CFDR 0x004 /* i2c frequency divider register */ 257 #define I2CCR 0x008 /* i2c control register */ 258 #define I2CSR 0x00c /* i2c status register */ 259 #define I2CDR 0x010 /* i2c data register */ 260 #define I2CDFSSR 0x014 /* i2c address register */ 261 #endif /* I2C_PRIVATE */ 262 263 #define DUART1_BASE 0x4500 264 #define DUART2_BASE 0x4600 265 #define DUART_SIZE 0x0100 266 267 #define SPI_BASE 0x7000 /* MPC8536 */ 268 #define SPI_SIZE 0x1000 269 270 #define SATA1_BASE 0x18000 /* MPC8536 */ 271 #define SATA2_BASE 0x19000 /* MPC8536 */ 272 #define SATA_SIZE 0x01000 273 274 #define USB1_BASE 0x22100 /* MPC8536 */ 275 #define USB2_BASE 0x23100 /* MPC8536 */ 276 #define USB3_BASE 0x2b100 /* MPC8536 */ 277 #define USB_SIZE 0x00f00 278 279 #define ETSEC1_BASE 0x24000 280 #define ETSEC2_BASE 0x25000 281 #define ETSEC3_BASE 0x26000 282 #define ETSEC4_BASE 0x27000 283 #define ETSEC_SIZE 0x01000 284 285 #define ESDHC_BASE 0x2e000 286 #define ESDHC_SIZE 0x01000 287 288 #define GLOBAL_BASE 0xe0000 289 #define GLOBAL_SIZE 0x01000 290 291 #ifdef GLOBAL_PRIVATE 292 293 /* Power-On Reset Configuration Values */ 294 #define PORPLLSR 0x000 /* POR PLL ratio status register */ 295 #define E500_RATIO __PPCBITS(10,15) 296 #define E500_RATIO_GET(n) __SHIFTOUT(n, E500_RATIO) 297 #define PCI1_CLK_SEL __PPCBIT(16) 298 #define PCI2_CLK_SEL __PPCBIT(17) 299 #define PLAT_RATIO __PPCBITS(26,30) 300 #define PLAT_RATIO_GET(n) __SHIFTOUT(n, PLAT_RATIO) 301 #define PORBMSR 0x004 /* POR boot mode status register */ 302 #define PORBMSR_HA __PPCBITS(13,15) 303 #define PORBMSR_HA_GET(n) __SHIFTOUT(m, PORBMSR_HA) 304 #define PORBMSR_HA_PEXSRIO_AGENT 0 /* PCI Express & SRIO agent mode */ 305 #define PORBMSR_HA_SRIO_AGENT 1 /* SRIO agent mode */ 306 #define PORBMSR_HA_PEX_AGENT 2 /* PCI Express agent mode */ 307 #define PORBMSR_HA_PEXPCI_AGENT2 3 /* PCI[-X] & PCI Express agent mode */ 308 #define PORBMSR_HA_PCISRIO_AGENT2 4 /* PCI[-X] & SRIO mode */ 309 #define PORBMSR_HA_SRIO_AGENT2 5 /* SRIO agent mode */ 310 #define PORBMSR_HA_PCI_AGENT2 6 /* PCI[-X] agent mode */ 311 #define PORBMSR_HA_HOST 7 /* Host mode */ 312 #define PORIMPSCR 0x008 /* POR I/O impedance status and control register */ 313 #define PORDEVSR 0x00C /* POR I/O device status register */ 314 #define PORDEVSR_ECW1 __PPCBIT(0) 315 #define PORDEVSR_ECW2 __PPCBIT(1) 316 #define PORDEVSR_SGMII1_DIS1 __PPCBIT(2) 317 #define PORDEVSR_SGMII1_DIS2 __PPCBIT(3) 318 #define PORDEVSR_SGMII1_DIS3 __PPCBIT(4) 319 #define PORDEVSR_SGMII1_DIS4 __PPCBIT(5) 320 #define PORDEVSR_ECP1 __PPCBITS(6,7) 321 #define PORDEVSR_PCI1 __PPCBIT(8) 322 #define PCI1_PCIX 0 323 #define PCI1_PCI1 1 324 #define PORDEVSR_IOSEL __PPCBITS(9,12) 325 #define IOSEL_MPC8536_OFF 0x01 326 #define IOSEL_MPC8536_PCIE1_X4 0x02 327 #define IOSEL_MPC8536_PCIE1_X8 0x03 328 #define IOSEL_MPC8536_PCIE12_X4 0x05 329 #define IOSEL_MPC8536_PCIE1_X4_PCI23_X2 0x07 330 #define IOSEL_MPC8544_OFF 0x00 331 #define IOSEL_MPC8544_SGMII_ON 0x01 332 #define IOSEL_MPC8544_PCIE1_ON 0x02 333 #define IOSEL_MPC8544_PCIE1_SGMII_ON 0x03 334 #define IOSEL_MPC8544_PCIE12_ON 0x04 335 #define IOSEL_MPC8544_PCIE12_SGMII_ON 0x05 336 #define IOSEL_MPC8544_PCIE123_ON 0x06 337 #define IOSEL_MPC8544_PCIE123_SGMII_ON 0x07 338 #define IOSEL_MPC8548_SRIO2500_PCIE1_X4 3 339 #define IOSEL_MPC8548_SRIO1250_PCIE1_X4 4 340 #define IOSEL_MPC8548_SRIO3125 5 341 #define IOSEL_MPC8548_SRIO1250 6 342 #define IOSEL_MPC8548_PCIE1_X8 7 343 #define IOSEL_MPC8572_PCIE1_X4 2 344 #define IOSEL_MPC8572_PCIE12_X4 3 345 #define IOSEL_MPC8572_SRIO2500 6 346 #define IOSEL_MPC8572_PCIE1_X4_23_X2 7 347 #define IOSEL_MPC8572_SRIO2500_PCIE1_X4 11 348 #define IOSEL_MPC8572_SRIO1250_PCIE1_X4 12 349 #define IOSEL_MPC8572_SRIO3125 13 350 #define IOSEL_MPC8572_SRIO1250 14 351 #define IOSEL_MPC8572_PCIE1_X8 15 352 #define PORDEVSR_PCI2_ARB __PPCBIT(13) 353 #define PORDEVSR_PCI1_ARB __PPCBIT(14) 354 #define PORDEVSR_PCI32 __PPCBIT(15) 355 #define PCI32_FALSE 0 356 #define PCI32_TRUE 1 357 #define PORDEVSR_PCI1_SPD __PPCBIT(16) 358 #define PORDEVSR_PCI2_SPD __PPCBIT(17) 359 #define PORDEVSR_SYS_SPD __PPCBIT(17) /* MPC8536 */ 360 #define PORDEVSR_CORE_SPD __PPCBIT(18) /* MPC8536 */ 361 #define PORDEVSR_ECP2 __PPCBITS(18,19) 362 #define PORDEVSR_ECP3 __PPCBITS(20,21) 363 #define PORDEVSR_ECP4 __PPCBITS(22,23) 364 #define PORDEVSR_FEC_DIS __PPCBIT(24) 365 #define PORDEVSR_RTPE __PPCBIT(25) 366 #define PORDEVSR_RIO_CTLS __PPCBIT(28) 367 #define PORDEVSR_DEV_ID __PPCBITs(29,31) 368 #define PORDBGMSR 0x010 /* POR debug mode status register */ 369 #define PORDEVSR2 0x014 /* POR I/O device status register 2 */ 370 #define GPPORCR 0x020 /* General-purpose POR configuration register */ 371 372 /* Signal Multiplexing and GPIO Controls */ 373 #define GPIOCR 0x030 /* GPIO control register */ 374 #define GPIOCR_TX2 __PPCBIT(6) /* Enable TSEC2_TX[7:0] as GP output */ 375 #define GPIOCR_RX2 __PPCBIT(7) /* Enable TSEC2_RX[7:0] as GP input */ 376 #define GPIOCR_PCIOUT __PPCBIT(14) /* Enable PCI2_AD[15:8] as GP output */ 377 #define GPIOCR_PCIIN __PPCBIT(15) /* Enable PCI2_AD[7:0] as GP input */ 378 #define GPIOCR_GPOUT __PPCBIT(22) /* Enable GPOUT[24:31] as GP output */ 379 #define GPOUTDR 0x040 /* General-purpose output data register */ 380 #define GPOUTDR_TX2 0x040 /* General-purpose output data register */ 381 #define GPOUTDR_PCI 0x041 /* General-purpose output data register */ 382 #define GPOUTDR_GPOUT 0x043 /* General-purpose output data register */ 383 #define GPINDR 0x050 /* General-purpose input data register */ 384 #define GPINDR_RX2 0x059 385 #define GPINDR_PCI 0x051 386 387 #define PMUXCR 0x060 /* Alternate function signal multiplex control */ 388 #define PMUXCR_SD_DATA __PPCBIT(0) 389 #define PMUXCR_SDHC_CD __PPCBIT(1) 390 #define PMUXCR_SDHC_WP __PPCBIT(2) 391 #define PMUXCR_PCI_REQGNT3 __PPCBIT(3) 392 #define PMUXCR_PCI_REQGNT4 __PPCBIT(4) 393 #define PMUXCR_USB1 __PPCBIT(5) 394 #define PMUXCR_USB2 __PPCBIT(6) 395 #define PMUXCR_DMA0 __PPCBIT(14) 396 #define PMUXCR_DMA2 __PPCBIT(15) 397 #define PMUXCR_DMA1 __PPCBIT(30) 398 #define PMUXCR_DMA3 __PPCBIT(31) 399 400 /* Device Disables */ 401 #define DEVDISR 0x070 /* Device disable control */ 402 #define DEVDISR_PCI1 __PPCBIT(0) 403 #define DEVDISR_PCI2 __PPCBIT(1) 404 #define DEVDISR_PCIE __PPCBIT(2) 405 #define DEVDISR_LBC __PPCBIT(4) 406 #define DEVDISR_PCIE2 __PPCBIT(5) 407 #define DEVDISR_PCIE3 __PPCBIT(6) 408 #define DEVDISR_SEC __PPCBIT(7) 409 #define DEVDISR_PME __PPCBIT(8) 410 #define DEVDISR_USB1 __PPCBIT(8) /* MPC8536 */ 411 #define DEVDISR_TLU1 __PPCBIT(9) 412 #define DEVDISR_USB2 __PPCBIT(9) /* MPC8536 */ 413 #define DEVDISR_TLU2 __PPCBIT(10) 414 #define DEVDISR_USB3 __PPCBIT(10) /* MPC8536 */ 415 #define DEVDISR_L2 __PPCBIT(11) /* MPC8536 */ 416 #define DEVDISR_SRIO __PPCBIT(12) 417 #define DEVDISR_ESDHC __PPCBIT(12) /* MPC8536 */ 418 #define DEVDISR_RMSG __PPCBIT(13) 419 #define DEVDISR_SATA1 __PPCBIT(13) /* MPC8536 */ 420 #define DEVDISR_DDR2 __PPCBIT(14) 421 #define DEVDISR_DDR __PPCBIT(15) 422 #define DEVDISR_SPI __PPCBIT(15) /* MPC8536 */ 423 #define DEVDISR_E500 __PPCBIT(16) 424 #define DEVDISR_TB __PPCBIT(17) 425 #define DEVDISR_E500_1 __PPCBIT(18) 426 #define DEVDISR_TB_1 __PPCBIT(19) 427 #define DEVDISR_SATA2 __PPCBIT(20) /* MPC8536 */ 428 #define DEVDISR_DMA __PPCBIT(21) 429 #define DEVDISR_DMA2 __PPCBIT(22) 430 #define DEVDISR_SRDS2 __PPCBIT(22) /* MPC8536 */ 431 #define DEVDISR_TSEC1 __PPCBIT(24) 432 #define DEVDISR_TSEC2 __PPCBIT(25) 433 #define DEVDISR_TSEC3 __PPCBIT(26) 434 #define DEVDISR_TSEC4 __PPCBIT(27) 435 #define DEVDISR_FEC __PPCBIT(28) 436 #define DEVDISR_I2C __PPCBIT(29) 437 #define DEVDISR_DUART __PPCBIT(30) 438 #define DEVDISR_SRDS1 __PPCBIT(31) /* MPC8536 */ 439 440 /* Power Management Registers */ 441 #define POWMGTCSR 0x080 /* Power management status and control register */ 442 443 /* Interrupt and Reset Status and Control */ 444 #define MCPSUMR 0x090 /* Machine check summary register */ 445 #define RSTRSCR 0x094 /* Reset request status and control register */ 446 447 /* Version Registers */ 448 #define PVR 0x0A0 /* Processor version register */ 449 #define SVR 0x0A4 /* System version register */ 450 451 /* Status Registers */ 452 #define RSTCR 0x0B0 /* Reset control register */ 453 #define HRESET_REQ __PPCBIT(30) /* hardware reset request */ 454 #define LBCVSELCR 0x0C0 /* LBC voltage select control register */ 455 #define DDRCSR 0xB20 /* DDR calibration status register */ 456 #define DDRCDR 0xB24 /* DDR control driver register */ 457 #define DDRCLKDR 0xB28 /* DDR clock disable register */ 458 459 /* Debug Control */ 460 #define CLKOCR 0xE00 /* Clock out control register */ 461 #define SRDSCR0 0xF04 /* LSerDes control register 0 */ 462 #define SRDSCR1 0xF08 /* LSerDes control register 1 */ 463 #define TSEC12IOOVCR 0xF28 /* eTSEC 1 & 2 overdrive control register */ 464 #define TSEC34IOOVCR 0xF2C /* eTSEC 3 & 4 overdrive control register */ 465 #endif /* GLOBAL_PRIVATE */ 466 467 #define LBC_BASE 0x5000 468 #define LBC_SIZE 0x0fff 469 470 #ifdef LBC_PRIVATE 471 472 #define BR_BA __PPCBITS(0,16) 473 #define BR_XBA __PPCBITS(17,18) 474 #define BR_PS __PPCBITS(19,20) 475 #define BR_PS_8BIT __SHIFTIN(1,BR_PS) 476 #define BR_PS_16BIT __SHIFTIN(2,BR_PS) 477 #define BR_PS_32BIT __SHIFTIN(3,BR_PS) 478 #define BR_DECC __PPCBITS(21,22) 479 #define BR_DECC_NONE __SHIFTIN(0,BR_DECC) 480 #define BR_DECC_PARITY __SHIFTIN(1,BR_DECC) 481 #define BR_DECC_RMWPAR __SHIFTIN(2,BR_DECC) 482 #define BR_WP __PPCBIT(23) 483 #define BR_MSEL __PPCBITS(24,26) 484 #define BR_MSEL_GPCM __SHIFTIN(0,BR_MSEL) 485 #define BR_MSEL_FCM __SHIFTIN(1,BR_MSEL) 486 #define BR_MSEL_SDRAM __SHIFTIN(3,BR_MSEL) 487 #define BR_MSEL_UPMA __SHIFTIN(4,BR_MSEL) 488 #define BR_MSEL_UPMB __SHIFTIN(5,BR_MSEL) 489 #define BR_MSEL_UPMC __SHIFTIN(6,BR_MSEL) 490 #define BR_ATOM __PPCBITS(28,29) 491 #define BR_ATOM_NONE __SHIFTIN(0,BR_ATOM) 492 #define BR_ATOM_RAWA __SHIFTIN(1,BR_ATOM) 493 #define BR_ATOM_WARA __SHIFTIN(2,BR_ATOM) 494 #define BR_V __PPCBIT(31) 495 496 #define OR_AM __PPCBITS(0,16) 497 #define OR_XAM __PPCBITS(17,18) 498 #define OR_BCTLD __PPCBIT(19) 499 #define OR_CSNT __PPCBIT(20) 500 #define OR_ACS __PPCBITS(21,22) 501 #define OR_XACS __PPCBIT(23) 502 #define OR_SCY __PPCBITS(24,27) 503 #define OR_SETA __PPCBIT(28) 504 #define OR_TRLX __PPCBIT(29) 505 #define OR_EHTR __PPCBIT(30) 506 #define OR_EAD __PPCBIT(31) 507 508 #define BRn(n) (BR0 + 8*(n)) 509 #define ORn(n) (OR0 + 8*(n)) 510 #define BR0 0x000 /* Base register 0 */ 511 #define OR0 0x004 /* Options register 0 */ 512 #define BR1 0x008 /* Base register 1 */ 513 #define OR1 0x00C /* Options register 1 */ 514 #define BR2 0x010 /* Base register 2 */ 515 #define OR2 0x014 /* Options register 2 */ 516 #define BR3 0x018 /* Base register 3 */ 517 #define OR3 0x01C /* Options register 3 */ 518 #define BR4 0x020 /* Base register 4 */ 519 #define OR4 0x024 /* Options register 4 */ 520 #define BR5 0x028 /* Base register 5 */ 521 #define OR5 0x02C /* Options register 5 */ 522 #define BR6 0x030 /* Base register 6 */ 523 #define OR6 0x034 /* Options register 6 */ 524 #define BR7 0x038 /* Base register 7 */ 525 #define OR7 0x03C /* Options register 7 */ 526 #define MAR 0x068 /* UPM address register */ 527 #define MAMR 0x070 /* UPMA mode register */ 528 #define MBMR 0x074 /* UPMB mode register */ 529 #define MCMR 0x078 /* UPMC mode register */ 530 #define MRTPR 0x084 /* Memory refresh timer prescaler register */ 531 #define MDR 0x088 /* UPM data register */ 532 #define LSDMR 0x094 /* SDRAM mode register */ 533 #define LURT 0x0A0 /* UPM refresh timer */ 534 #define LSRT 0x0A4 /* SDRAM refresh timer */ 535 #define LTESR 0x0B0 /* Transfer error status register */ 536 #define LTEDR 0x0B4 /* Transfer error disable register */ 537 #define LTEIR 0x0B8 /* Transfer error interrupt register */ 538 #define LTEATR 0x0BC /* Transfer error attributes register */ 539 #define LTEAR 0x0C0 /* Transfer error address register */ 540 #define LBCR 0x0D0 /* Configuration register */ 541 #define LCRR 0x0D4 /* Clock ratio register */ 542 543 #define MXMR_RFEN __PPCBIT(1) /* Refresh enable */ 544 #define MXMR_OP __PPCBITS(2,3) /* Command opcode */ 545 #define MXMR_OP_NORMAL __SHIFTIN(0, MXMR_OP) /* Normal Operation */ 546 #define MXMR_OP_WRITE __SHIFTIN(1, MXMR_OP) /* Write to UPM memory */ 547 #define MXMR_OP_READ __SHIFTIN(2, MXMR_OP) /* Read from UPM memory */ 548 #define MXMR_OP_RUN __SHIFTIN(3, MXMR_OP) /* Run Pattern */ 549 #define MXMR_UWPL __PPCBIT(3) /* LUPWAIT is active low */ 550 #define MXMR_AM __PPCBITS(5,7) /* Address multiplex size */ 551 #define MXMR_DS __PPCBITS(8,9) /* Disable timer period */ 552 #define MXMR_DS_1CYCLE __SHIFTIN(0,MXMR_DS) 553 #define MXMR_DS_2CYCLE __SHIFTIN(1,MXMR_DS) 554 #define MXMR_DS_3CYCLE __SHIFTIN(2,MXMR_DS) 555 #define MXMR_DS_4CYCLE __SHIFTIN(3,MXMR_DS) 556 #define MXMR_G0CL __PPCBITS(10,12) /* General line 0 control */ 557 #define MXMR_G0CL_A12 __SHIFTIN(0,MXMR_G0CL) 558 #define MXMR_G0CL_A11 __SHIFTIN(1,MXMR_G0CL) 559 #define MXMR_G0CL_A10 __SHIFTIN(2,MXMR_G0CL) 560 #define MXMR_G0CL_A9 __SHIFTIN(3,MXMR_G0CL) 561 #define MXMR_G0CL_A8 __SHIFTIN(4,MXMR_G0CL) 562 #define MXMR_G0CL_A7 __SHIFTIN(5,MXMR_G0CL) 563 #define MXMR_G0CL_A6 __SHIFTIN(6,MXMR_G0CL) 564 #define MXMR_G0CL_A5 __SHIFTIN(7,MXMR_G0CL) 565 #define MXMR_GPL4 __PPCBIT(13) /* LGPL4 output line disable */ 566 #define MXMR_RLF __PPCBITS(14,17) /* Read loop field */ 567 #define MXMR_WLF __PPCBITS(18,21) /* Write loop field */ 568 #define MXMR_TLF __PPCBITS(22,25) /* Refresh loop field */ 569 #define MXMR_MAS __PPCBITS(26,31) /* Machine Address */ 570 571 #define MRTPR_PTP __PPCBITS(0,7) /* Refresh timers prescaler */ 572 573 #endif /* LBC_PRIVATE */ 574