1 /* $NetBSD: dcr4xx.h,v 1.2 2010/11/06 16:32:08 uebayasi Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _DCR405GP_H_ 39 #define _DCR405GP_H_ 40 41 /* Device Control Register declarations */ 42 43 /* DCRs used for indirect access */ 44 #define DCR_CPR0_CFGADDR 0x00c /* Clocking Configuration Address Register */ 45 #define DCR_CPR0_CFGDATA 0x00d /* Clocking Configuration Data Register */ 46 #define DCR_SDR0_CFGADDR 0x00e /* System DCR Configuration Address Register */ 47 #define DCR_SDR0_CFGDATA 0x00f /* System DCR Configuration Data Register */ 48 #define DCR_SDRAM0_CFGADDR 0x010 /* Memory Controller Address Register */ 49 #define DCR_SDRAM0_CFGDATA 0x011 /* Memory Controller Data Register */ 50 #define DCR_EBC0_CFGADDR 0x012 /* Peripheral Controller Address Register */ 51 #define DCR_EBC0_CFGDATA 0x013 /* Peripheral Controller Data Register */ 52 #define DCR_DCP0_CFGADDR 0x014 /* Decompression Controller Address Register */ 53 #define DCR_DCP0_CFGDATA 0x015 /* Decompression Controller Data Register */ 54 55 /* On-Chip memory */ 56 #define DCR_OCM0_ISARC 0x018 /* OCM Instruction-Side Address Range Compare Register */ 57 #define DCR_OCM0_ISCNTL 0x019 /* OCM Instruction-Side Control Register */ 58 #define DCR_OCM0_DSARC 0x01a /* OCM Data-Side Address Range Compare Register */ 59 #define DCR_OCM0_DSCNTL 0x01b /* OCM Data-Side Control Register */ 60 61 /* On-Chip busses */ 62 #define DCR_PLB0_BESR 0x084 /* PLB Bus Error Status Register */ 63 #define DCR_PLB0_BEAR 0x086 /* PLB Bus Error Address Register */ 64 #define DCR_PLB0_ACR 0x087 /* PLB Arbiter Control Register */ 65 #define DCR_POB0_BESR0 0x0a0 /* PLB to OPB Bus Error Status Register 0 */ 66 #define DCR_POB0_BEAR 0x0a2 /* PLB to OPB Bus Error Address Register */ 67 #define DCR_POB0_BESR1 0x0a4 /* PLB to OPB Bus Error Status Register 1 */ 68 69 /* Clocking, Power management and Chip Control */ 70 #define DCR_CPC0_PLLMR 0x0b0 /* PLL Mode Register */ 71 #define CPC0_PLLMR_CBDV(pllmr) ((((pllmr) & 0x00060000) >> 17) + 1) 72 #define CPC0_PLLMR_OPDV(pllmr) ((((pllmr) & 0x00018000) >> 15) + 1) 73 #define DCR_CPC0_CR0 0x0b1 /* Chip Control Register 0 */ 74 #define DCR_CPC0_CR1 0x0b2 /* Chip Control Register 1 */ 75 #define CPC0_CR1_CETE 0x00800000 /* CPU External Timer Enable */ 76 #define DCR_CPC0_PSR 0x0b4 /* Chip Pin Strapping Register */ 77 #define DCR_CPC0_JTAGID 0x0b5 /* JTAG ID Register */ 78 #define DCR_CPC0_SR 0x0b8 /* CPM Status Register */ 79 #define DCR_CPC0_ER 0x0b9 /* CPM Enable Register */ 80 #define DCR_CPC0_FR 0x0ba /* CPM Force Register */ 81 82 /* Universal Interrupt Controllers */ 83 #define DCR_UIC0_BASE 0x0c0 /* UIC0 Registers Base */ 84 #define DCR_UIC1_BASE 0x0d0 /* UIC1 Registers Base */ 85 #define DCR_UIC2_BASE 0x0e0 /* UIC2 Registers Base */ 86 #define DCR_UIC3_BASE 0x0f0 /* UIC3 Registers Base */ 87 #define DCR_UICB_BASE 0x200 /* UICB Registers Base */ 88 #define DCR_UIC2_BASE_440GX 0x210 /* UIC2 Registers Base (440GX only) */ 89 90 #define DCR_UIC_SR 0x000 /* UIC Status Register */ 91 #define DCR_UIC_ER 0x002 /* UIC Enable Register */ 92 #define DCR_UIC_CR 0x003 /* UIC Critical Register */ 93 #define DCR_UIC_PR 0x004 /* UIC Polarity Register */ 94 #define DCR_UIC_TR 0x005 /* UIC Triggering Register */ 95 #define DCR_UIC_MSR 0x006 /* UIC Masked Status Register */ 96 #define DCR_UIC_VR 0x007 /* UIC Vector Register */ 97 #define DCR_UIC_VCR 0x008 /* UIC Vector Configuration Register */ 98 99 /* Direct Memory Access */ 100 #define DCR_DMA0_CR0 0x100 /* DMA Channel Control Register 0 */ 101 #define DCR_DMA0_CT0 0x101 /* DMA Count Register 0 */ 102 #define DCR_DMA0_DA0 0x102 /* DMA Destination Address Register 0 */ 103 #define DCR_DMA0_SA0 0x103 /* DMA Source Address Register 0 */ 104 #define DCR_DMA0_SG0 0x104 /* DMA Scatter/Gather Descriptor Address Register 0 */ 105 106 #define DCR_DMA0_CR1 0x108 /* DMA Channel Control Register 1 */ 107 #define DCR_DMA0_CT1 0x109 /* DMA Count Register 1 */ 108 #define DCR_DMA0_DA1 0x10a /* DMA Destination Address Register 1 */ 109 #define DCR_DMA0_SA1 0x10b /* DMA Source Address Register 1 */ 110 #define DCR_DMA0_SG1 0x10c /* DMA Scatter/Gather Descriptor Address Register 1 */ 111 112 #define DCR_DMA0_CR2 0x110 /* DMA Channel Control Register 2 */ 113 #define DCR_DMA0_CT2 0x111 /* DMA Count Register 2 */ 114 #define DCR_DMA0_DA2 0x112 /* DMA Destination Address Register 2 */ 115 #define DCR_DMA0_SA2 0x113 /* DMA Source Address Register 2 */ 116 #define DCR_DMA0_SG2 0x114 /* DMA Scatter/Gather Descriptor Address Register 2 */ 117 118 #define DCR_DMA0_CR3 0x118 /* DMA Channel Control Register 3 */ 119 #define DCR_DMA0_CT3 0x119 /* DMA Count Register 3 */ 120 #define DCR_DMA0_DA3 0x11a /* DMA Destination Address Register 3 */ 121 #define DCR_DMA0_SA3 0x11b /* DMA Source Address Register 3 */ 122 #define DCR_DMA0_SG3 0x11c /* DMA Scatter/Gather Descriptor Address Register 3 */ 123 124 #define DCR_DMA0_SR 0x120 /* DMA Status Register */ 125 #define DCR_DMA0_SGC 0x123 /* DMA Scatter/Gather Control Register */ 126 #define DCR_DMA0_SLP 0x125 /* DMA Sleep Mode Register */ 127 #define DCR_DMA0_POL 0x126 /* DMA Polarity Configuration Register */ 128 129 /* Memory Access Layer */ 130 #define DCR_MAL0_CFG 0x180 /* MAL Configuration Register */ 131 #define MAL0_CFG_SR 0x80000000 /* Software Reset */ 132 #define MAL0_CFG_PLBP_MASK 0x00c00000 /* PLB priority mask */ 133 #define MAL0_CFG_PLBP_0 0x00000000 /* PLB priority 0 */ 134 #define MAL0_CFG_PLBP_1 0x00400000 /* PLB priority 1 */ 135 #define MAL0_CFG_PLBP_2 0x00800000 /* PLB priority 2 */ 136 #define MAL0_CFG_PLBP_3 0x00c00000 /* PLB priority 3 */ 137 #define MAL0_CFG_GA 0x00200000 /* Guarded Active */ 138 #define MAL0_CFG_OA 0x00100000 /* Ordered Active */ 139 #define MAL0_CFG_PLBLE 0x00080000 /* PLB Lock Error */ 140 #define MAL0_CFG_PLBLT 0x00078000 /* PLB Latency Timer */ 141 #define MAL0_CFG_PLBLTSHIFT 15 /* PLB Latency Timer shift */ 142 #define MAL0_CFG_PLBB 0x00004000 /* PLB Burst */ 143 #define MAL0_CFG_OPBBL 0x00000080 /* OPB Bus Lock */ 144 #define MAL0_CFG_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ 145 #define MAL0_CFG_LEA 0x00000002 /* Locked Error Active */ 146 #define MAL0_CFG_SD 0x00000001 /* MAL Scroll Descriptor */ 147 148 #define MAL0_CFG_RPP_MASK 0x00c00000 /* Read priority mask */ 149 #define MAL0_CFG_RPP_0 0x00000000 /* Lowest */ 150 #define MAL0_CFG_RPP_1 0x00400000 151 #define MAL0_CFG_RPP_2 0x00800000 152 #define MAL0_CFG_RPP_3 0x00c00000 /* Highest */ 153 #define MAL0_CFG_RMBS_MASK 0x00300000 /* Read Max Burst Size */ 154 #define MAL0_CFG_RMBS_4 0x00000000 /* Max burst size of 4 */ 155 #define MAL0_CFG_RMBS_8 0x00100000 /* Max burst size of 8 */ 156 #define MAL0_CFG_RMBS_16 0x00200000 /* Max burst size of 16 */ 157 #define MAL0_CFG_RMBS_32 0x00300000 /* Max burst size of 32 */ 158 #define MAL0_CFG_WPP_MASK 0x000c0000 /* Write PLB Priority */ 159 #define MAL0_CFG_WPP_0 0x00000000 /* Lowest */ 160 #define MAL0_CFG_WPP_1 0x00040000 161 #define MAL0_CFG_WPP_2 0x00080000 162 #define MAL0_CFG_WPP_3 0x000c0000 /* Highest */ 163 #define MAL0_CFG_WMBS_MASK 0x00030000 /* Write Max Burst Size */ 164 #define MAL0_CFG_WMBS_4 0x00000000 /* Max burst size of 4 */ 165 #define MAL0_CFG_WMBS_8 0x00010000 /* Max burst size of 8 */ 166 #define MAL0_CFG_WMBS_16 0x00020000 /* Max burst size of 16 */ 167 #define MAL0_CFG_WMBS_32 0x00030000 /* Max burst size of 32 */ 168 #define MAL0_CFG_PLBLE__EX 0x00008000 /* PLB Lock Error */ 169 170 #define DCR_MAL0_ESR 0x181 /* Error Status Register */ 171 #define MAL0_ESR_EVB 0x80000000 /* Error Valid Bit */ 172 #define MAL0_ESR_CID_RX 0x40000000 /* Receive Channel */ 173 #define MAL0_ESR_CID_MASK 0x3e000000 /* Channel ID */ 174 #define MAL0_ESR_CID_SHIFT 25 175 #define MAL0_ESR_PTE 0x00800000 /* PLB Timeout Error */ 176 #define MAL0_ESR_PRE 0x00400000 /* PLB Read Error */ 177 #define MAL0_ESR_PWE 0x00200000 /* PLB Write Error */ 178 #define MAL0_ESR_DE 0x00100000 /* Descriptor Error */ 179 #define MAL0_ESR_ONE 0x00080000 /* OPB Non-fullword Error */ 180 #define MAL0_ESR_OTE 0x00040000 /* OPB Timeout Error */ 181 #define MAL0_ESR_OSE 0x00020000 /* OPB Slave Error */ 182 #define MAL0_ESR_PEIN 0x00010000 /* PLB Bus Error Indication */ 183 #define MAL0_ESR_PTEI 0x00000080 /* PLB Timeout Error Interrupt */ 184 #define MAL0_ESR_PREI 0x00000040 /* PLB Read Error Interrupt */ 185 #define MAL0_ESR_PWEI 0x00000020 /* PLB Write Error Interrupt */ 186 #define MAL0_ESR_DEI 0x00000010 /* Descriptor Error Interrupt */ 187 #define MAL0_ESR_ONEI 0x00000008 /* OPB Non-fullword Error Interrupt */ 188 #define MAL0_ESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ 189 #define MAL0_ESR_OSEI 0x00000002 /* OPB Slave Error Interrupt */ 190 #define MAL0_ESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ 191 #define DCR_MAL0_IER 0x182 /* Interrupt Enable Register */ 192 #define MAL0_IER_PT 0x00000080 /* PLB Timeout Interrupt */ 193 #define MAL0_IER_PRE 0x00000040 /* PLB Read Interrupt */ 194 #define MAL0_IER_PWE 0x00000020 /* PLB Write Interrupt */ 195 #define MAL0_IER_DE 0x00000010 /* Descriptor Error Interrupt */ 196 #define MAL0_IER_NWE 0x00000008 /* Non-Word Transfer Error Interrupt */ 197 #define MAL0_IER_TO 0x00000004 /* Time Out Error Interrupt */ 198 #define MAL0_IER_OPB 0x00000002 /* OPB Error Interrupt */ 199 #define MAL0_IER_PLB 0x00000001 /* PLB Error Interrupt */ 200 #define DCR_MALDBR 0x183 /* MAL Debug register */ 201 #define DCR_MAL0_TXCASR 0x184 /* Tx Channel Active Register (Set) */ 202 #define DCR_MAL0_TXCARR 0x185 /* Tx Channel Active Register (Reset) */ 203 #define DCR_MAL0_TXEOBISR 0x186 /* Tx End of Buffer Interrupt Status Register */ 204 #define DCR_MAL0_TXDEIR 0x187 /* Tx Descriptor Error Interrupt Register */ 205 #define DCR_MAL0_RXCASR 0x190 /* Rx Channel Active Register (Set) */ 206 #define DCR_MAL0_RXCARR 0x191 /* Rx Channel Active Register (Reset) */ 207 #define DCR_MAL0_RXEOBISR 0x192 /* Rx End of Buffer Interrupt Status Register */ 208 #define DCR_MAL0_RXDEIR 0x193 /* Rx Descriptor Error Interrupt Register */ 209 #define MAL0__XCAR_CHAN(c) (0x80000000 >> (c)) 210 #define DCR_MAL0_TXCTP0R 0x1a0 /* Channel Tx 0 Channel Table Pointer Register */ 211 #define DCR_MAL0_TXCTP1R 0x1a1 /* Channel Tx 1 Channel Table Pointer Register */ 212 #define DCR_MAL0_TXCTP2R 0x1a2 /* Channel Tx 2 Channel Table Pointer Register */ 213 #define DCR_MAL0_TXCTP3R 0x1a3 /* Channel Tx 3 Channel Table Pointer Register */ 214 #define DCR_MAL0_RXCTP0R 0x1c0 /* Channel Rx 0 Channel Table Pointer Register */ 215 #define DCR_MAL0_RXCTP1R 0x1c1 /* Channel Rx 1 Channel Table Pointer Register */ 216 #define DCR_MAL0_RXCTP2R 0x1c2 /* Channel Rx 2 Channel Table Pointer Register */ 217 #define DCR_MAL0_RXCTP3R 0x1c3 /* Channel Rx 3 Channel Table Pointer Register */ 218 #define DCR_MAL0_RCBS0 0x1e0 /* Channel Rx 0 Channel Buffer Size Register */ 219 #define DCR_MAL0_RCBS1 0x1e1 /* Channel Rx 1 Channel Buffer Size Register */ 220 #define DCR_MAL0_RCBS2 0x1e2 /* Channel Rx 2 Channel Buffer Size Register */ 221 #define DCR_MAL0_RCBS3 0x1e3 /* Channel Rx 3 Channel Buffer Size Register */ 222 223 224 /* Indirectly accessed Clocking Controller DCRs */ 225 226 #define DCR_CPR0_CLKUPD 0x020 /* Clocking Update Register */ 227 #define DCR_CPR0_PLLC 0x040 /* SYS_PLL Control Register */ 228 #define DCR_CPR0_PLLD 0x060 /* SYS_PLL Divider Register */ 229 #define DCR_CPR0_CPUD 0x080 /* CPU Clock Divider Register */ 230 #define DCR_CPR0_PLBD 0x0a0 /* PLB Clock Divider Register */ 231 #define CPR0_PLBDV0(x) \ 232 ((((x) & 0x07000000) >> 24) == 0 ? 8 : (((x) & 0x07000000) >> 24)) 233 #define DCR_CPR0_OPBD 0x0c0 /* OPB Clock Divider Register */ 234 #define CPR0_OPBDV0(x) \ 235 ((((x) & 0x03000000) >> 24) == 0 ? 4 : (((x) & 0x03000000) >> 24)) 236 #define DCR_CPR0_PERD 0x0e0 /* Peripheral Clock Divider Register */ 237 #define DCR_CPR0_AHBD 0x100 /* AHB Clock Divider Register */ 238 #define DCR_CPR0_ICFG 0x140 /* Initial Configuration Register */ 239 240 /* Indirectly accessed Clocking Controller DCRs */ 241 242 #define DCR_SDR0_MFR 0x4300 /* Miscellaneous Function Register */ 243 #define SDR0_MFR_ECS(n) (1 << (27 - (n))) /* Ethernet n Clock Selection */ 244 #define SDR0_MFR_ETXFL(n) (1 << (15 - ((n) << 2))) /* Force Parity Error EMACn Tx FIFO Bits 0:63 */ 245 #define SDR0_MFR_ETXFH(n) (1 << (14 - ((n) << 2))) /* Force Parity Error EMACn Tx FIFO Bits 64:127 */ 246 #define SDR0_MFR_ERXFL(n) (1 << (13 - ((n) << 2))) /* Force Parity Error EMACn Rx FIFO Bits 0:63 */ 247 #define SDR0_MFR_ERXFH(n) (1 << (12 - ((n) << 2))) /* Force Parity Error EMACn Rx FIFO Bits 64:127 */ 248 249 /* Indirectly accessed SDRAM Controller DCRs */ 250 251 #define DCR_SDRAM0_BESR0 0x00 252 #define DCR_SDRAM0_BESR1 0x08 253 #define DCR_SDRAM0_BEAR 0x10 254 #define DCR_SDRAM0_CFG 0x20 255 #define DCR_SDRAM0_STATUS 0x24 256 #define DCR_SDRAM0_RTR 0x30 257 #define DCR_SDRAM0_PMIT 0x34 258 #define DCR_SDRAM0_B0CR 0x40 259 #define DCR_SDRAM0_B1CR 0x44 260 #define DCR_SDRAM0_B2CR 0x48 261 #define DCR_SDRAM0_B3CR 0x4c 262 #define DCR_SDRAM0_TR 0x80 263 #define DCR_SDRAM0_ECCCFG 0x94 264 #define DCR_SDRAM0_ECCESR 0x98 265 #define SDRAM0_ECCESR_BLCE 0xf0000000 266 #define SDRAM0_ECCESR_CBE 0x00c00000 267 #define SDRAM0_ECCESR_CE 0x00200000 268 #define SDRAM0_ECCESR_UE 0x00100000 269 #define SDRAM0_ECCESR_BKE 0x0000f000 270 271 #define SDRAM0_ECCESR_BLCEN(n) (0x80000000 >> (n)) 272 #define SDRAM0_ECCESR_BKEN(n) (0x00008000 >> (n)) 273 #define SDRAM0_ECCESR_CBEN(n) (0x00800000 >> (n)) 274 275 /* Indirectly accessed External Bus Controller (EBC) DCRs */ 276 277 #define DCR_EBC0_B0CR 0x00 278 #define DCR_EBC0_B1CR 0x01 279 #define DCR_EBC0_B2CR 0x02 280 #define DCR_EBC0_B3CR 0x03 281 #define DCR_EBC0_B4CR 0x04 282 #define DCR_EBC0_B5CR 0x05 283 #define DCR_EBC0_B6CR 0x06 284 #define DCR_EBC0_B7CR 0x07 285 #define DCR_EBC0_B0AP 0x10 286 #define DCR_EBC0_B1AP 0x11 287 #define DCR_EBC0_B2AP 0x12 288 #define DCR_EBC0_B3AP 0x13 289 #define DCR_EBC0_B4AP 0x14 290 #define DCR_EBC0_B5AP 0x15 291 #define DCR_EBC0_B6AP 0x16 292 #define DCR_EBC0_B7AP 0x17 293 #define DCR_EBC0_BEAR 0x20 294 #define DCR_EBC0_BESR0 0x21 295 #define DCR_EBC0_BESR1 0x22 296 #define DCR_EBC0_CFG 0x23 297 298 /* Indirectly accessed Decompression Controller DCRs */ 299 300 #define DCR_DCP0_ITOR0 0x00 301 #define DCR_DCP0_ITOR1 0x01 302 #define DCR_DCP0_ITOR2 0x02 303 #define DCR_DCP0_ITOR3 0x03 304 #define DCR_DCP0_ADDR0 0x04 305 #define DCR_DCP0_ADDR1 0x05 306 #define DCR_DCP0_CFG 0x40 307 #define DCR_DCP0_ID 0x41 308 #define DCR_DCP0_VER 0x42 309 #define DCR_DCP0_PLBBEAR 0x50 310 #define DCR_DCP0_MEMBEAR 0x51 311 #define DCR_DCP0_ESR 0x52 312 #define DCR_DCP0_RAM0 0x400 313 314 #endif /* _DCR405GP_H_ */ 315