xref: /netbsd/sys/arch/powerpc/include/openpicreg.h (revision bf9ec67e)
1 /*	$NetBSD: openpicreg.h,v 1.3 2001/08/30 03:08:52 briggs Exp $	*/
2 
3 /*-
4  * Copyright (c) 2000 Tsubai Masanari.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. The name of the author may not be used to endorse or promote products
15  *    derived from this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 /*
30  * GLOBAL/TIMER register (IDU base + 0x1000)
31  */
32 
33 /* feature reporting reg 0 */
34 #define OPENPIC_FEATURE			0x1000
35 
36 /* global config reg 0 */
37 #define OPENPIC_CONFIG			0x1020
38 #define  OPENPIC_CONFIG_RESET			0x80000000
39 #define  OPENPIC_CONFIG_8259_PASSTHRU_DISABLE	0x20000000
40 
41 /* interrupt configuration mode (direct or serial) */
42 #define OPENPIC_ICR			0x1030
43 #define  OPENPIC_ICR_SERIAL_MODE	(1 << 27)
44 #define  OPENPIC_ICR_SERIAL_RATIO_MASK	(0x7 << 28)
45 #define  OPENPIC_ICR_SERIAL_RATIO_SHIFT	28
46 
47 /* vendor ID */
48 #define OPENPIC_VENDOR_ID		0x1080
49 
50 /* processor initialization reg */
51 #define OPENPIC_PROC_INIT		0x1090
52 
53 /* IPI vector/priority reg */
54 #define OPENPIC_IPI_VECTOR(ipi)		(0x10a0 + (ipi) * 0x10)
55 
56 /* spurious intr. vector */
57 #define OPENPIC_SPURIOUS_VECTOR		0x10e0
58 
59 
60 /*
61  * INTERRUPT SOURCE register (IDU base + 0x10000)
62  */
63 
64 /* interrupt vector/priority reg */
65 #ifndef OPENPIC_SRC_VECTOR
66 #define OPENPIC_SRC_VECTOR(irq)		(0x10000 + (irq) * 0x20)
67 #endif
68 #define  OPENPIC_SENSE_LEVEL			0x00400000
69 #define  OPENPIC_SENSE_EDGE			0x00000000
70 #define  OPENPIC_POLARITY_POSITIVE		0x00800000
71 #define  OPENPIC_POLARITY_NEGATIVE		0x00000000
72 #define  OPENPIC_IMASK				0x80000000
73 #define  OPENPIC_ACTIVITY			0x40000000
74 #define  OPENPIC_PRIORITY_MASK			0x000f0000
75 #define  OPENPIC_PRIORITY_SHIFT			16
76 #define  OPENPIC_VECTOR_MASK			0x000000ff
77 
78 /* interrupt destination cpu */
79 #ifndef OPENPIC_IDEST
80 #define OPENPIC_IDEST(irq)		(0x10010 + (irq) * 0x20)
81 #endif
82 
83 /*
84  * PROCESSOR register (IDU base + 0x20000)
85  */
86 
87 /* IPI command reg */
88 #define OPENPIC_IPI(cpu, ipi)		(0x20040 + (cpu) * 0x1000 + (ipi))
89 
90 /* current task priority reg */
91 #define OPENPIC_CPU_PRIORITY(cpu)	(0x20080 + (cpu) * 0x1000)
92 #define  OPENPIC_CPU_PRIORITY_MASK		0x0000000f
93 
94 /* interrupt acknowledge reg */
95 #define OPENPIC_IACK(cpu)		(0x200a0 + (cpu) * 0x1000)
96 
97 /* end of interrupt reg */
98 #define OPENPIC_EOI(cpu)		(0x200b0 + (cpu) * 0x1000)
99