1 /* $NetBSD: spr.h,v 1.45 2010/02/25 23:30:04 matt Exp $ */ 2 3 #ifndef _POWERPC_SPR_H_ 4 #define _POWERPC_SPR_H_ 5 6 #ifndef _LOCORE 7 #define mtspr(reg, val) \ 8 __asm volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 9 #ifdef __GNUC__ 10 #define mfspr(reg) \ 11 ( { register_t val; \ 12 __asm volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 13 val; } ) 14 #endif 15 #endif /* _LOCORE */ 16 17 /* 18 * Special Purpose Register declarations. 19 * 20 * The first column in the comments indicates which PowerPC architectures the 21 * SPR is valid on - E for BookE series, 4 for 4xx series, 22 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx (but not 85xx) series. 23 */ 24 25 #define SPR_XER 0x001 /* E468 Fixed Point Exception Register */ 26 #define SPR_LR 0x008 /* E468 Link Register */ 27 #define SPR_CTR 0x009 /* E468 Count Register */ 28 #define SPR_DEC 0x016 /* E468 DECrementer register */ 29 #define SPR_SRR0 0x01a /* E468 Save/Restore Register 0 */ 30 #define SPR_SRR1 0x01b /* E468 Save/Restore Register 1 */ 31 #define SPR_SPRG0 0x110 /* E468 SPR General 0 */ 32 #define SPR_SPRG1 0x111 /* E468 SPR General 1 */ 33 #define SPR_SPRG2 0x112 /* E468 SPR General 2 */ 34 #define SPR_SPRG3 0x113 /* E468 SPR General 3 */ 35 #define SPR_SPRG4 0x114 /* E4.. SPR General 4 */ 36 #define SPR_SPRG5 0x115 /* E4.. SPR General 5 */ 37 #define SPR_SPRG6 0x116 /* E4.. SPR General 6 */ 38 #define SPR_SPRG7 0x117 /* E4.. SPR General 7 */ 39 #define SPR_TBL 0x11c /* E468 Time Base Lower */ 40 #define SPR_TBU 0x11d /* E468 Time Base Upper */ 41 #define SPR_PVR 0x11f /* E468 Processor Version Register */ 42 43 /* Time Base Register declarations */ 44 #define TBR_TBL 0x10c /* E468 Time Base Lower */ 45 #define TBR_TBU 0x10d /* E468 Time Base Upper */ 46 47 #endif /* !_POWERPC_SPR_H_ */ 48