1 /* $NetBSD: db_disasm.c,v 1.13 2002/11/25 02:06:16 thorpej Exp $ */ 2 /* $OpenBSD: db_disasm.c,v 1.2 1996/12/28 06:21:48 rahnds Exp $ */ 3 4 #include <sys/param.h> 5 #include <sys/proc.h> 6 #include <sys/systm.h> 7 8 #include <machine/db_machdep.h> 9 10 #include <ddb/db_access.h> 11 #include <ddb/db_sym.h> 12 #include <ddb/db_variables.h> 13 #include <ddb/db_interface.h> 14 #include <ddb/db_output.h> 15 16 enum function_mask { 17 Op_A = 0x00000001, 18 Op_B = 0x00000002, 19 Op_BI = 0x00000004, 20 Op_BO = 0x00000008, 21 Op_CRM = 0x00000010, 22 Op_D = 0x00000020, /* yes, Op_S and Op_D are the same */ 23 Op_S = 0x00000020, 24 Op_FM = 0x00000040, 25 Op_IMM = 0x00000080, 26 Op_LK = 0x00000100, 27 Op_Rc = 0x00000200, 28 Op_AA = Op_LK | Op_Rc, /* kludge (reduce Op_s) */ 29 Op_LKM = Op_AA, 30 Op_RcM = Op_AA, 31 Op_OE = 0x00000400, 32 Op_SR = 0x00000800, 33 Op_TO = 0x00001000, 34 Op_sign = 0x00002000, 35 Op_const = 0x00004000, 36 Op_SIMM = Op_const | Op_sign, 37 Op_UIMM = Op_const, 38 Op_d = Op_const | Op_sign, 39 Op_crbA = 0x00008000, 40 Op_crbB = 0x00010000, 41 Op_WS = Op_crbB, /* kludge, same field as crbB */ 42 Op_crbD = 0x00020000, 43 Op_crfD = 0x00040000, 44 Op_crfS = 0x00080000, 45 Op_ds = 0x00100000, 46 Op_me = 0x00200000, 47 Op_spr = 0x00400000, 48 Op_dcr = Op_spr, /* out of bits - cheat with Op_spr */ 49 Op_tbr = 0x00800000, 50 51 Op_L = 0x01000000, 52 Op_BD = 0x02000000, 53 Op_LI = 0x04000000, 54 Op_C = 0x08000000, 55 56 Op_NB = 0x10000000, 57 58 Op_sh_mb_sh = 0x20000000, 59 Op_sh = 0x40000000, 60 Op_SH = Op_sh | Op_sh_mb_sh, 61 Op_mb = 0x80000000, 62 Op_MB = Op_mb | Op_sh_mb_sh, 63 Op_ME = Op_MB, 64 65 }; 66 67 struct opcode { 68 char *name; 69 u_int32_t mask; 70 u_int32_t code; 71 enum function_mask func; 72 }; 73 74 typedef u_int32_t instr_t; 75 typedef void (op_class_func) (instr_t, vaddr_t); 76 77 u_int32_t extract_field(u_int32_t value, u_int32_t base, u_int32_t width); 78 void disasm_fields(const struct opcode *popcode, instr_t instr, vaddr_t loc, 79 char *disasm_str); 80 void dis_ppc(const struct opcode *opcodeset, instr_t instr, vaddr_t loc); 81 82 op_class_func op_ill, op_base; 83 op_class_func op_cl_x13, op_cl_x1e, op_cl_x1f; 84 op_class_func op_cl_x3a, op_cl_x3b; 85 op_class_func op_cl_x3e, op_cl_x3f; 86 87 op_class_func *opcodes_base[] = { 88 /*x00*/ op_ill, op_ill, op_base, op_ill, 89 /*x04*/ op_ill, op_ill, op_ill, op_base, 90 /*x08*/ op_base, op_base, op_ill, op_base, 91 /*x0C*/ op_base, op_base, op_base/*XXX*/, op_base/*XXX*/, 92 /*x10*/ op_base, op_base, op_base, op_cl_x13, 93 /*x14*/ op_base, op_base, op_ill, op_base, 94 /*x18*/ op_base, op_base, op_base, op_base, 95 /*x1C*/ op_base, op_base, op_cl_x1e, op_cl_x1f, 96 /*x20*/ op_base, op_base, op_base, op_base, 97 /*x24*/ op_base, op_base, op_base, op_base, 98 /*x28*/ op_base, op_base, op_base, op_base, 99 /*x2C*/ op_base, op_base, op_base, op_base, 100 /*x30*/ op_base, op_base, op_base, op_base, 101 /*x34*/ op_base, op_base, op_base, op_base, 102 /*x38*/ op_ill, op_ill, op_cl_x3a, op_cl_x3b, 103 /*x3C*/ op_ill, op_ill, op_cl_x3e, op_cl_x3f 104 }; 105 106 107 /* This table could be modified to make significant the "reserved" fields 108 * of the opcodes, But I didn't feel like it when typing in the table, 109 * I would recommend that this table be looked over for errors, 110 * This was derived from the table in Appendix A.2 of (Mot part # MPCFPE/AD) 111 * PowerPC Microprocessor Family: The Programming Environments 112 */ 113 114 const struct opcode opcodes[] = { 115 { "tdi", 0xfc000000, 0x08000000, Op_TO | Op_A | Op_SIMM }, 116 { "twi", 0xfc000000, 0x0c000000, Op_TO | Op_A | Op_SIMM }, 117 { "mulli", 0xfc000000, 0x1c000000, Op_D | Op_A | Op_SIMM }, 118 { "subfic", 0xfc000000, 0x20000000, Op_D | Op_A | Op_SIMM }, 119 { "cmpli", 0xfc000000, 0x28000000, Op_crfD | Op_L | Op_A | Op_SIMM }, 120 { "cmpi", 0xfc000000, 0x2c000000, Op_crfD | Op_L | Op_A | Op_SIMM }, 121 { "addic", 0xfc000000, 0x30000000, Op_D | Op_A | Op_SIMM }, 122 { "addic.", 0xfc000000, 0x34000000, Op_D | Op_A | Op_SIMM }, 123 { "addi", 0xfc000000, 0x38000000, Op_D | Op_A | Op_SIMM }, 124 { "addis", 0xfc000000, 0x3c000000, Op_D | Op_A | Op_SIMM }, 125 { "bc", 0xfc000000, 0x40000000, Op_BO | Op_BI | Op_BD | Op_AA | Op_LK }, 126 { "sc", 0xffffffff, 0x44000002, Op_BO | Op_BI | Op_BD | Op_AA | Op_LK }, 127 { "b", 0xfc000000, 0x48000000, Op_LI | Op_AA | Op_LK }, 128 129 { "rlwimi", 0xfc000000, 0x50000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 130 { "rlwinm", 0xfc000000, 0x54000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 131 { "rlwnm", 0xfc000000, 0x5c000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 132 133 { "ori", 0xfc000000, 0x60000000, Op_S | Op_A | Op_UIMM }, 134 { "oris", 0xfc000000, 0x64000000, Op_S | Op_A | Op_UIMM }, 135 { "xori", 0xfc000000, 0x68000000, Op_S | Op_A | Op_UIMM }, 136 { "xoris", 0xfc000000, 0x6c000000, Op_S | Op_A | Op_UIMM }, 137 138 { "andi.", 0xfc000000, 0x70000000, Op_S | Op_A | Op_UIMM }, 139 { "andis.", 0xfc000000, 0x74000000, Op_S | Op_A | Op_UIMM }, 140 141 { "lwz", 0xfc000000, 0x80000000, Op_D | Op_A | Op_d }, 142 { "lwzu", 0xfc000000, 0x84000000, Op_D | Op_A | Op_d }, 143 { "lbz", 0xfc000000, 0x88000000, Op_D | Op_A | Op_d }, 144 { "lbzu", 0xfc000000, 0x8c000000, Op_D | Op_A | Op_d }, 145 { "stw", 0xfc000000, 0x90000000, Op_S | Op_A | Op_d }, 146 { "stwu", 0xfc000000, 0x94000000, Op_S | Op_A | Op_d }, 147 { "stb", 0xfc000000, 0x98000000, Op_S | Op_A | Op_d }, 148 { "stbu", 0xfc000000, 0x9c000000, Op_S | Op_A | Op_d }, 149 150 { "lhz", 0xfc000000, 0xa0000000, Op_D | Op_A | Op_d }, 151 { "lhzu", 0xfc000000, 0xa4000000, Op_D | Op_A | Op_d }, 152 { "lha", 0xfc000000, 0xa8000000, Op_D | Op_A | Op_d }, 153 { "lhau", 0xfc000000, 0xac000000, Op_D | Op_A | Op_d }, 154 { "sth", 0xfc000000, 0xb0000000, Op_S | Op_A | Op_d }, 155 { "sthu", 0xfc000000, 0xb4000000, Op_S | Op_A | Op_d }, 156 { "lmw", 0xfc000000, 0xb8000000, Op_D | Op_A | Op_d }, 157 { "stmw", 0xfc000000, 0xbc000000, Op_S | Op_A | Op_d }, 158 159 { "lfs", 0xfc000000, 0xc0000000, Op_D | Op_A | Op_d }, 160 { "lfsu", 0xfc000000, 0xc4000000, Op_D | Op_A | Op_d }, 161 { "lfd", 0xfc000000, 0xc8000000, Op_D | Op_A | Op_d }, 162 { "lfdu", 0xfc000000, 0xcc000000, Op_D | Op_A | Op_d }, 163 164 { "stfs", 0xfc000000, 0xd0000000, Op_S | Op_A | Op_d }, 165 { "stfsu", 0xfc000000, 0xd4000000, Op_S | Op_A | Op_d }, 166 { "stfd", 0xfc000000, 0xd8000000, Op_S | Op_A | Op_d }, 167 { "stfdu", 0xfc000000, 0xdc000000, Op_S | Op_A | Op_d }, 168 { "", 0x0, 0x0, 0 } 169 170 }; 171 /* 13 * 4 = 4c */ 172 const struct opcode opcodes_13[] = { 173 /* 0x13 << 2 */ 174 { "mcrf", 0xfc0007fe, 0x4c000000, Op_crfD | Op_crfS }, 175 { "bclr", 0xfc0007fe, 0x4c000020, Op_BO | Op_BI | Op_LK }, 176 { "crnor", 0xfc0007fe, 0x4c000042, Op_crbD | Op_crbA | Op_crbB }, 177 { "rfi", 0xfc0007fe, 0x4c000064, 0 }, 178 { "crandc", 0xfc0007fe, 0x4c000102, Op_BO | Op_BI | Op_LK }, 179 { "isync", 0xfc0007fe, 0x4c00012c, 0 }, 180 { "crxor", 0xfc0007fe, 0x4c000182, Op_crbD | Op_crbA | Op_crbB }, 181 { "crnand", 0xfc0007fe, 0x4c0001c2, Op_crbD | Op_crbA | Op_crbB }, 182 { "crand", 0xfc0007fe, 0x4c000202, Op_crbD | Op_crbA | Op_crbB }, 183 { "creqv", 0xfc0007fe, 0x4c000242, Op_crbD | Op_crbA | Op_crbB }, 184 { "crorc", 0xfc0007fe, 0x4c000342, Op_crbD | Op_crbA | Op_crbB }, 185 { "cror", 0xfc0007fe, 0x4c000382, Op_crbD | Op_crbA | Op_crbB }, 186 { "bcctr", 0xfc0007fe, 0x4c000420, Op_BO | Op_BI | Op_LK }, 187 { "", 0x0, 0x0, 0 } 188 }; 189 190 /* 1e * 4 = 78 */ 191 const struct opcode opcodes_1e[] = { 192 { "rldicl", 0xfc00001c, 0x78000000, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 193 { "rldicr", 0xfc00001c, 0x78000004, Op_S | Op_A | Op_sh | Op_me | Op_Rc }, 194 { "rldic", 0xfc00001c, 0x78000008, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 195 { "rldimi", 0xfc00001c, 0x7800000c, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 196 { "rldcl", 0xfc00003e, 0x78000010, Op_S | Op_A | Op_B | Op_mb | Op_Rc }, 197 { "rldcr", 0xfc00003e, 0x78000012, Op_S | Op_A | Op_B | Op_me | Op_Rc }, 198 { "", 0x0, 0x0, 0 } 199 }; 200 201 /* 1f * 4 = 7c */ 202 const struct opcode opcodes_1f[] = { 203 /* 1f << 2 */ 204 { "cmp", 0xfc0007fe, 0x7c000000, Op_S | Op_A | Op_B | Op_me | Op_Rc }, 205 { "tw", 0xfc0007fe, 0x7c000008, Op_TO | Op_A | Op_B }, 206 { "subfc", 0xfc0003fe, 0x7c000010, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 207 { "mulhdu", 0xfc0007fe, 0x7c000012, Op_D | Op_A | Op_B | Op_Rc }, 208 { "addc", 0xfc0003fe, 0x7c000014, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 209 { "mulhwu", 0xfc0007fe, 0x7c000016, Op_D | Op_A | Op_B | Op_Rc }, 210 211 { "mfcr", 0xfc0007fe, 0x7c000026, Op_D }, 212 { "lwarx", 0xfc0007fe, 0x7c000028, Op_D | Op_A | Op_B }, 213 { "ldx", 0xfc0007fe, 0x7c00002a, Op_D | Op_A | Op_B }, 214 { "lwzx", 0xfc0007fe, 0x7c00002e, Op_D | Op_A | Op_B }, 215 { "slw", 0xfc0007fe, 0x7c000030, Op_D | Op_A | Op_B | Op_Rc }, 216 { "cntlzw", 0xfc0007fe, 0x7c000034, Op_D | Op_A | Op_Rc }, 217 { "sld", 0xfc0007fe, 0x7c000036, Op_D | Op_A | Op_B | Op_Rc }, 218 { "and", 0xfc0007fe, 0x7c000038, Op_D | Op_A | Op_B | Op_Rc }, 219 { "cmpl", 0xfc0007fe, 0x7c000040, Op_crfD | Op_L | Op_A | Op_B }, 220 { "subf", 0xfc0003fe, 0x7c000050, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 221 { "ldux", 0xfc0007fe, 0x7c00006a, Op_D | Op_A | Op_B }, 222 { "dcbst", 0xfc0007fe, 0x7c00006c, Op_A | Op_B }, 223 { "lwzux", 0xfc0007fe, 0x7c00006e, Op_D | Op_A | Op_B }, 224 { "cntlzd", 0xfc0007fe, 0x7c000074, Op_S | Op_A | Op_Rc }, 225 { "andc", 0xfc0007fe, 0x7c000078, Op_S | Op_A | Op_B | Op_Rc }, 226 { "td", 0xfc0007fe, 0x7c000088, Op_TO | Op_A | Op_B }, 227 { "mulhd", 0xfc0007fe, 0x7c000092, Op_D | Op_A | Op_B | Op_Rc }, 228 { "mulhw", 0xfc0007fe, 0x7c000096, Op_D | Op_A | Op_B | Op_Rc }, 229 { "mfmsr", 0xfc0007fe, 0x7c0000a6, Op_D }, 230 { "ldarx", 0xfc0007fe, 0x7c0000a8, Op_D | Op_A | Op_B }, 231 { "dcbf", 0xfc0007fe, 0x7c0000ac, Op_A | Op_B }, 232 { "lbzx", 0xfc0007fe, 0x7c0000ae, Op_D | Op_A | Op_B }, 233 { "neg", 0xfc0003fe, 0x7c0000d0, Op_D | Op_A | Op_OE | Op_Rc }, 234 { "lbzux", 0xfc0007fe, 0x7c0000ee, Op_D | Op_A | Op_B }, 235 { "nor", 0xfc0007fe, 0x7c0000f8, Op_S | Op_A | Op_B | Op_Rc }, 236 { "wrtee", 0xfc0003ff, 0x7c000106, Op_S }, 237 { "subfe", 0xfc0003fe, 0x7c000110, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 238 { "adde", 0xfc0003fe, 0x7c000114, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 239 { "mtcrf", 0xfc0007fe, 0x7c000120, Op_S | Op_CRM }, 240 { "mtmsr", 0xfc0007fe, 0x7c000124, Op_S }, 241 { "stdx", 0xfc0007fe, 0x7c00012a, Op_S | Op_A | Op_B }, 242 { "stwcx.", 0xfc0007ff, 0x7c00012d, Op_S | Op_A | Op_B }, 243 { "stwx", 0xfc0007fe, 0x7c00012e, Op_S | Op_A | Op_B }, 244 { "wrteei", 0xfc0003fe, 0x7c000146 }, /* XXX: out of flags! */ 245 { "stdux", 0xfc0007fe, 0x7c00016a, Op_S | Op_A | Op_B }, 246 { "stwux", 0xfc0007fe, 0x7c00016e, Op_S | Op_A | Op_B }, 247 { "subfze", 0xfc0003fe, 0x7c000190, Op_D | Op_A | Op_OE | Op_Rc }, 248 { "addze", 0xfc0003fe, 0x7c000194, Op_D | Op_A | Op_OE | Op_Rc }, 249 { "mtsr", 0xfc0007fe, 0x7c0001a4, Op_S | Op_SR }, 250 { "stdcx.", 0xfc0007ff, 0x7c0001ad, Op_S | Op_A | Op_B }, 251 { "stbx", 0xfc0007fe, 0x7c0001ae, Op_S | Op_A | Op_B }, 252 { "subfme", 0xfc0003fe, 0x7c0001d0, Op_D | Op_A | Op_OE | Op_Rc }, 253 { "mulld", 0xfc0003fe, 0x7c0001d2, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 254 { "addme", 0xfc0003fe, 0x7c0001d4, Op_D | Op_A | Op_OE | Op_Rc }, 255 { "mullw", 0xfc0003fe, 0x7c0001d6, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 256 { "mtsrin", 0xfc0007fe, 0x7c0001e4, Op_S | Op_B }, 257 { "dcbtst", 0xfc0007fe, 0x7c0001ec, Op_A | Op_B }, 258 { "stbux", 0xfc0007fe, 0x7c0001ee, Op_S | Op_A | Op_B }, 259 { "add", 0xfc0003fe, 0x7c000214, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 260 { "dcbt", 0xfc0007fe, 0x7c00022c, Op_A | Op_B }, 261 { "lhzx", 0xfc0007ff, 0x7c00022e, Op_D | Op_A | Op_B }, 262 { "eqv", 0xfc0007fe, 0x7c000238, Op_S | Op_A | Op_B | Op_Rc }, 263 { "tlbie", 0xfc0007fe, 0x7c000264, Op_B }, 264 { "eciwx", 0xfc0007fe, 0x7c00026c, Op_D | Op_A | Op_B }, 265 { "lhzux", 0xfc0007fe, 0x7c00026e, Op_D | Op_A | Op_B }, 266 { "xor", 0xfc0007fe, 0x7c000278, Op_S | Op_A | Op_B | Op_Rc }, 267 { "mfdcr", 0xfc0007fe, 0x7c000286, Op_D | Op_dcr }, 268 { "mfspr", 0xfc0007fe, 0x7c0002a6, Op_D | Op_spr }, 269 { "lwax", 0xfc0007fe, 0x7c0002aa, Op_D | Op_A | Op_B }, 270 { "lhax", 0xfc0007fe, 0x7c0002ae, Op_D | Op_A | Op_B }, 271 { "tlbia", 0xfc0007fe, 0x7c0002e4, 0 }, 272 { "mftb", 0xfc0007fe, 0x7c0002e6, Op_D | Op_tbr }, 273 { "lwaux", 0xfc0007fe, 0x7c0002ea, Op_D | Op_A | Op_B }, 274 { "lhaux", 0xfc0007fe, 0x7c0002ee, Op_D | Op_A | Op_B }, 275 { "sthx", 0xfc0007fe, 0x7c00032e, Op_S | Op_A | Op_B }, 276 { "orc", 0xfc0007fe, 0x7c000338, Op_S | Op_A | Op_B | Op_Rc }, 277 { "ecowx", 0xfc0007fe, 0x7c00036c, Op_S | Op_A | Op_B | Op_Rc }, 278 { "slbie", 0xfc0007fc, 0x7c000364, Op_B }, 279 { "sthux", 0xfc0007fe, 0x7c00036e, Op_S | Op_A | Op_B }, 280 { "or", 0xfc0007fe, 0x7c000378, Op_S | Op_A | Op_B | Op_Rc }, 281 { "mtdcr", 0xfc0007fe, 0x7c000386, Op_S | Op_dcr }, 282 { "divdu", 0xfc0003fe, 0x7c000392, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 283 { "divwu", 0xfc0003fe, 0x7c000396, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 284 { "mtspr", 0xfc0007fe, 0x7c0003a6, Op_S | Op_spr }, 285 { "dcbi", 0xfc0007fe, 0x7c0003ac, Op_A | Op_B }, 286 { "nand", 0xfc0007fe, 0x7c0003b8, Op_S | Op_A | Op_B | Op_Rc }, 287 { "dcread", 0xfc0007fe, 0x7c0003cc, Op_D | Op_A | Op_B }, 288 { "divd", 0xfc0003fe, 0x7c0003d2, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 289 { "divw", 0xfc0003fe, 0x7c0003d6, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 290 { "slbia", 0xfc0003fe, 0x7c0003e4, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 291 { "mcrxr", 0xfc0007fe, 0x7c000400, Op_crfD }, 292 { "lswx", 0xfc0007fe, 0x7c00042a, Op_D | Op_A | Op_B }, 293 { "lwbrx", 0xfc0007fe, 0x7c00042c, Op_D | Op_A | Op_B }, 294 { "lfsx", 0xfc0007fe, 0x7c00042e, Op_D | Op_A | Op_B }, 295 { "srw", 0xfc0007fe, 0x7c000430, Op_S | Op_A | Op_B | Op_Rc }, 296 { "srd", 0xfc0007fe, 0x7c000436, Op_S | Op_A | Op_B | Op_Rc }, 297 { "tlbsync", 0xfc0007fe, 0x7c00046c, 0 }, 298 { "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B }, 299 { "mfsr", 0xfc0007fe, 0x7c0004a6, Op_D | Op_SR }, 300 { "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB }, 301 { "sync", 0xfc0007fe, 0x7c0004ac, 0 }, 302 { "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B }, 303 { "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B }, 304 { "mfsrin", 0xfc0007fe, 0x7c000526, Op_D | Op_B }, 305 { "stswx", 0xfc0007fe, 0x7c00052a, Op_S | Op_A | Op_B }, 306 { "stwbrx", 0xfc0007fe, 0x7c00052c, Op_S | Op_A | Op_B }, 307 { "stfsx", 0xfc0007fe, 0x7c00052e, Op_S | Op_A | Op_B }, 308 { "stfsux", 0xfc0007fe, 0x7c00056e, Op_S | Op_A | Op_B }, 309 { "stswi", 0xfc0007fe, 0x7c0005aa, Op_S | Op_A | Op_NB }, 310 { "stfdx", 0xfc0007fe, 0x7c0005ae, Op_S | Op_A | Op_B }, 311 { "stfdux", 0xfc0007fe, 0x7c0005ee, Op_S | Op_A | Op_B }, 312 { "lhbrx", 0xfc0007fe, 0x7c00062c, Op_D | Op_A | Op_B }, 313 { "sraw", 0xfc0007fe, 0x7c000630, Op_S | Op_A | Op_B }, 314 { "srad", 0xfc0007fe, 0x7c000634, Op_S | Op_A | Op_B | Op_Rc }, 315 { "srawi", 0xfc0007fe, 0x7c000670, Op_S | Op_A | Op_B | Op_Rc }, 316 { "sradi", 0xfc0007fc, 0x7c000674, Op_S | Op_A | Op_sh }, 317 { "eieio", 0xfc0007fe, 0x7c0006ac, 0 }, 318 { "tlbsx", 0xfc0007fe, 0x7c000724, Op_S | Op_A | Op_B | Op_Rc }, 319 { "sthbrx", 0xfc0007fe, 0x7c00072c, Op_S | Op_A | Op_B }, 320 { "extsh", 0xfc0007fe, 0x7c000734, Op_S | Op_A | Op_B | Op_Rc }, 321 { "tlbre", 0xfc0007fe, 0x7c000764, Op_D | Op_A | Op_WS }, 322 { "extsb", 0xfc0007fe, 0x7c000774, Op_S | Op_A | Op_Rc }, 323 { "icbi", 0xfc0007fe, 0x7c0007ac, Op_A | Op_B }, 324 { "tlbwe", 0xfc0007fe, 0x7c0007a4, Op_S | Op_A | Op_WS }, 325 { "stfiwx", 0xfc0007fe, 0x7c0007ae, Op_S | Op_A | Op_B }, 326 { "extsw", 0xfc0007fe, 0x7c0007b4, Op_S | Op_A | Op_Rc }, 327 { "dcbz", 0xfc0007fe, 0x7c0007ec, Op_A | Op_B }, 328 { "", 0x0, 0x0, 0 } 329 }; 330 331 /* 3a * 4 = e8 */ 332 const struct opcode opcodes_3a[] = { 333 { "ld", 0xfc000003, 0xe8000000, Op_D | Op_A | Op_ds }, 334 { "ldu", 0xfc000003, 0xe8000001, Op_D | Op_A | Op_ds }, 335 { "lwa", 0xfc000003, 0xe8000002, Op_D | Op_A | Op_ds }, 336 { "", 0x0, 0x0, 0 } 337 }; 338 /* 3b * 4 = ec */ 339 const struct opcode opcodes_3b[] = { 340 { "fdivs", 0xfc00003e, 0xec000024, Op_D | Op_A | Op_B | Op_Rc }, 341 { "fsubs", 0xfc00003e, 0xec000028, Op_D | Op_A | Op_B | Op_Rc }, 342 343 { "fadds", 0xfc00003e, 0xec00002a, Op_D | Op_A | Op_B | Op_Rc }, 344 { "fsqrts", 0xfc00003e, 0xec00002c, Op_D | Op_B | Op_Rc }, 345 { "fres", 0xfc00003e, 0xec000030, Op_D | Op_B | Op_Rc }, 346 { "fmuls", 0xfc00003e, 0xec000032, Op_D | Op_A | Op_C | Op_Rc }, 347 { "fmsubs", 0xfc00003e, 0xec000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 348 { "fmadds", 0xfc00003e, 0xec00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 349 { "fnmsubs", 0xfc00003e, 0xec00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 350 { "fnmadds", 0xfc00003e, 0xec00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 351 { "", 0x0, 0x0, 0 } 352 }; 353 /* 3e * 4 = f8 */ 354 const struct opcode opcodes_3e[] = { 355 { "std", 0xfc000003, 0xf8000000, Op_S | Op_A | Op_ds }, 356 { "stdu", 0xfc000003, 0xf8000001, Op_S | Op_A | Op_ds }, 357 { "", 0x0, 0x0, 0 } 358 }; 359 360 /* 3f * 4 = fc */ 361 const struct opcode opcodes_3f[] = { 362 { "fcmpu", 0xfc0007fe, 0xfc000000, Op_crfD | Op_A | Op_B }, 363 { "frsp", 0xfc0007fe, 0xfc000018, Op_D | Op_B | Op_Rc }, 364 { "fctiw", 0xfc0007fe, 0xfc00001c, Op_D | Op_B | Op_Rc }, 365 { "fctiwz", 0xfc0007fe, 0xfc00001e, Op_D | Op_B | Op_Rc }, 366 367 { "fdiv", 0xfc00003e, 0xfc000024, Op_D | Op_A | Op_B | Op_Rc }, 368 { "fsub", 0xfc00003e, 0xfc000028, Op_D | Op_A | Op_B | Op_Rc }, 369 { "fadd", 0xfc00003e, 0xfc00002a, Op_D | Op_A | Op_B | Op_Rc }, 370 { "fsqrt", 0xfc00003e, 0xfc00002c, Op_D | Op_B | Op_Rc }, 371 { "fsel", 0xfc00003e, 0xfc00002e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 372 { "fmul", 0xfc00003e, 0xfc000032, Op_D | Op_A | Op_C | Op_Rc }, 373 { "frsqrte", 0xfc00003e, 0xfc000034, Op_D | Op_B | Op_Rc }, 374 { "fmsub", 0xfc00003e, 0xfc000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 375 { "fmadd", 0xfc00003e, 0xfc00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 376 { "fnmsub", 0xfc00003e, 0xfc00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 377 { "fnmadd", 0xfc00003e, 0xfc00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 378 379 { "fcmpo", 0xfc0007fe, 0xfc000040, Op_crfD | Op_A | Op_B }, 380 { "mtfsb1", 0xfc0007fe, 0xfc00004c, Op_crfD | Op_Rc }, 381 { "fneg", 0xfc0007fe, 0xfc000050, Op_D | Op_B | Op_Rc }, 382 { "mcrfs", 0xfc0007fe, 0xfc000080, Op_D | Op_B | Op_Rc }, 383 { "mtfsb0", 0xfc0007fe, 0xfc00008c, Op_crfD | Op_Rc }, 384 { "fmr", 0xfc0007fe, 0xfc000090, Op_D | Op_B | Op_Rc }, 385 { "mtfsfi", 0xfc0007fe, 0xfc00010c, Op_crfD | Op_IMM | Op_Rc }, 386 387 { "fnabs", 0xfc0007fe, 0xfc000110, Op_D | Op_B | Op_Rc }, 388 { "fabs", 0xfc0007fe, 0xfc000210, Op_D | Op_B | Op_Rc }, 389 { "mffs", 0xfc0007fe, 0xfc00048e, Op_D | Op_B | Op_Rc }, 390 { "mtfsf", 0xfc0007fe, 0xfc00058e, Op_FM | Op_B | Op_Rc }, 391 { "fctid", 0xfc0007fe, 0xfc00065c, Op_D | Op_B | Op_Rc }, 392 { "fctidz", 0xfc0007fe, 0xfc00065e, Op_D | Op_B | Op_Rc }, 393 { "fcfid", 0xfc0007fe, 0xfc00069c, Op_D | Op_B | Op_Rc }, 394 { "", 0x0, 0x0, 0 } 395 }; 396 397 398 struct specialreg { 399 int reg; 400 char *name; 401 }; 402 403 const struct specialreg sprregs[] = { 404 { 0x001, "xer" }, 405 { 0x008, "lr" }, 406 { 0x009, "ctr" }, 407 { 0x012, "dsisr" }, 408 { 0x013, "dar" }, 409 { 0x016, "dec" }, 410 { 0x019, "sdr1" }, 411 { 0x01a, "srr0" }, 412 { 0x01b, "srr1" }, 413 { 0x100, "usprg0" }, 414 { 0x110, "sprg0" }, 415 { 0x111, "sprg1" }, 416 { 0x112, "sprg2" }, 417 { 0x113, "sprg3" }, 418 { 0x114, "sprg4" }, 419 { 0x115, "sprg5" }, 420 { 0x116, "sprg6" }, 421 { 0x117, "sprg7" }, 422 { 0x118, "asr" }, 423 { 0x11a, "aer" }, 424 { 0x11c, "tbl" }, 425 { 0x11d, "tbu" }, 426 { 0x11f, "pvr" }, 427 { 0x210, "ibat0u" }, 428 { 0x211, "ibat0l" }, 429 { 0x212, "ibat1u" }, 430 { 0x213, "ibat1l" }, 431 { 0x214, "ibat2u" }, 432 { 0x215, "ibat2l" }, 433 { 0x216, "ibat3u" }, 434 { 0x217, "ibat3l" }, 435 { 0x218, "dbat0u" }, 436 { 0x219, "dbat0l" }, 437 { 0x21a, "dbat1u" }, 438 { 0x21b, "dbat1l" }, 439 { 0x21c, "dbat2u" }, 440 { 0x21d, "dbat2l" }, 441 { 0x21e, "dbat3u" }, 442 { 0x21f, "dbat3l" }, 443 { 0x3b0, "zpr" }, 444 { 0x3b1, "pid" }, 445 { 0x3b3, "ccr0" }, 446 { 0x3b4, "iac3" }, 447 { 0x3b5, "iac4" }, 448 { 0x3b6, "dvc1" }, 449 { 0x3b7, "dvc2" }, 450 { 0x3b9, "sgr" }, 451 { 0x3ba, "dcwr" }, 452 { 0x3bb, "sler" }, 453 { 0x3bc, "su0r" }, 454 { 0x3bd, "dbcr1" }, 455 { 0x3d3, "icdbdr" }, 456 { 0x3d4, "esr" }, 457 { 0x3d5, "dear" }, 458 { 0x3d6, "evpr" }, 459 { 0x3d8, "tsr" }, 460 { 0x3da, "tcr" }, 461 { 0x3db, "pit" }, 462 { 0x3de, "srr2" }, 463 { 0x3df, "srr3" }, 464 { 0x3f0, "dbsr" }, 465 { 0x3f2, "dbcr0" }, 466 { 0x3f4, "iac1" }, 467 { 0x3f5, "iac2" }, 468 { 0x3f6, "dac1" }, 469 { 0x3f7, "dac2" }, 470 { 0x3f9, "l2cr" }, 471 { 0x3fa, "dccr" }, 472 { 0x3fb, "iccr" }, 473 { 0x3ff, "pir" }, 474 { 0, NULL } 475 }; 476 477 const struct specialreg dcrregs[] = { 478 { 0x010, "sdram0_cfgaddr" }, 479 { 0x011, "sdram0_cfgdata" }, 480 { 0x012, "ebc0_cfgaddr" }, 481 { 0x013, "ebc0_cfgdata" }, 482 { 0x014, "dcp0_cfgaddr" }, 483 { 0x015, "dcp0_cfgdata" }, 484 { 0x018, "ocm0_isarc" }, 485 { 0x019, "ocm0_iscntl" }, 486 { 0x01a, "ocm0_dsarc" }, 487 { 0x01b, "ocm0_dscntl" }, 488 { 0x084, "plb0_besr" }, 489 { 0x086, "plb0_bear" }, 490 { 0x087, "plb0_acr" }, 491 { 0x0a0, "pob0_besr0" }, 492 { 0x0a2, "pob0_bear" }, 493 { 0x0a4, "pob0_besr1" }, 494 { 0x0b0, "cpc0_pllmr" }, 495 { 0x0b1, "cpc0_cr0" }, 496 { 0x0b2, "cpc0_cr1" }, 497 { 0x0b4, "cpc0_psr" }, 498 { 0x0b5, "cpc0_jtagid" }, 499 { 0x0b8, "cpc0_sr" }, 500 { 0x0b9, "cpc0_er" }, 501 { 0x0ba, "cpc0_fr" }, 502 { 0x0c0, "uic0_sr" }, 503 { 0x0c2, "uic0_er" }, 504 { 0x0c3, "uic0_cr" }, 505 { 0x0c4, "uic0_pr" }, 506 { 0x0c5, "uic0_tr" }, 507 { 0x0c6, "uic0_msr" }, 508 { 0x0c7, "uic0_vr" }, 509 { 0x0c8, "uic0_vcr" }, 510 { 0x100, "dma0_cr0" }, 511 { 0x101, "dma0_ct0" }, 512 { 0x102, "dma0_da0" }, 513 { 0x103, "dma0_sa0" }, 514 { 0x104, "dma0_sg0" }, 515 { 0x108, "dma0_cr1" }, 516 { 0x109, "dma0_ct1" }, 517 { 0x10a, "dma0_da1" }, 518 { 0x10b, "dma0_sa1" }, 519 { 0x10c, "dma0_sg1" }, 520 { 0x110, "dma0_cr2" }, 521 { 0x111, "dma0_ct2" }, 522 { 0x112, "dma0_da2" }, 523 { 0x113, "dma0_sa2" }, 524 { 0x114, "dma0_sg2" }, 525 { 0x118, "dma0_cr3" }, 526 { 0x119, "dma0_ct3" }, 527 { 0x11a, "dma0_da3" }, 528 { 0x11b, "dma0_sa3" }, 529 { 0x11c, "dma0_sg3" }, 530 { 0x120, "dma0_sr" }, 531 { 0x123, "dma0_sgc" }, 532 { 0x125, "dma0_slp" }, 533 { 0x126, "dma0_pol" }, 534 { 0x180, "mal0_cfg" }, 535 { 0x181, "mal0_esr" }, 536 { 0x182, "mal0_ier" }, 537 { 0x184, "mal0_txcasr" }, 538 { 0x185, "mal0_txcarr" }, 539 { 0x186, "mal0_txeobisr" }, 540 { 0x187, "mal0_txdeir" }, 541 { 0x190, "mal0_rxcasr" }, 542 { 0x191, "mal0_rxcarr" }, 543 { 0x192, "mal0_rxeobisr" }, 544 { 0x193, "mal0_rxdeir" }, 545 { 0x1a0, "mal0_txctp0r" }, 546 { 0x1a1, "mal0_txctp1r" }, 547 { 0x1a2, "mal0_txctp2r" }, 548 { 0x1a3, "mal0_txctp3r" }, 549 { 0x1c0, "mal0_rxctp0r" }, 550 { 0x1e0, "mal0_rcbs0" }, 551 { 0, NULL } 552 }; 553 554 void 555 op_ill(instr_t instr, vaddr_t loc) 556 { 557 db_printf("illegal instruction %x\n", instr); 558 } 559 560 u_int32_t 561 extract_field(u_int32_t value, u_int32_t base, u_int32_t width) 562 { 563 u_int32_t mask = (1 << width) - 1; 564 return ((value >> base) & mask); 565 } 566 567 const struct opcode * search_op(const struct opcode *); 568 569 void 570 disasm_fields(const struct opcode *popcode, instr_t instr, vaddr_t loc, 571 char *disasm_str) 572 { 573 char * pstr; 574 enum function_mask func; 575 576 pstr = disasm_str; 577 578 func = popcode->func; 579 if (func & Op_OE) { 580 u_int OE; 581 /* also for Op_S (they are the same) */ 582 OE = extract_field(instr, 31 - 21, 1); 583 if (OE) { 584 pstr += sprintf(pstr, "o"); 585 } 586 func &= ~Op_OE; 587 } 588 switch (func & Op_LKM) { 589 case Op_Rc: 590 if (instr & 0x1) { 591 pstr += sprintf(pstr, "."); 592 } 593 break; 594 case Op_AA: 595 if (instr & 0x2) { 596 pstr += sprintf(pstr, "a"); 597 loc = 0; /* Absolute address */ 598 } 599 case Op_LK: 600 if (instr & 0x1) { 601 pstr += sprintf(pstr, "l"); 602 } 603 break; 604 default: 605 func &= ~Op_LKM; 606 } 607 pstr += sprintf(pstr, "\t"); 608 609 /* XXX: special cases here, out of flags in a 32bit word. */ 610 if (strcmp(popcode->name, "wrteei") == 0) { 611 int E; 612 E = extract_field(instr, 31 - 16, 5); 613 pstr += sprintf(pstr, "%d", E); 614 return; 615 } 616 /* XXX: end of special cases here. */ 617 618 if (func & Op_D) { 619 u_int D; 620 /* also for Op_S (they are the same) */ 621 D = extract_field(instr, 31 - 10, 5); 622 pstr += sprintf(pstr, "r%d, ", D); 623 func &= ~Op_D; 624 } 625 if (func & Op_crbD) { 626 u_int crbD; 627 crbD = extract_field(instr, 31 - 10, 5); 628 pstr += sprintf(pstr, "crb%d, ", crbD); 629 func &= ~Op_crbD; 630 } 631 if (func & Op_crfD) { 632 u_int crfD; 633 crfD = extract_field(instr, 31 - 8, 3); 634 pstr += sprintf(pstr, "crf%d, ", crfD); 635 func &= ~Op_crfD; 636 } 637 if (func & Op_L) { 638 u_int L; 639 L = extract_field(instr, 31 - 10, 1); 640 if (L) { 641 pstr += sprintf(pstr, "L, "); 642 } 643 func &= ~Op_L; 644 } 645 if (func & Op_FM) { 646 u_int FM; 647 FM = extract_field(instr, 31 - 10, 8); 648 pstr += sprintf(pstr, "%d, ", FM); 649 func &= ~Op_FM; 650 } 651 if (func & Op_TO) { 652 u_int TO; 653 TO = extract_field(instr, 31 - 10, 1); 654 pstr += sprintf(pstr, "%d, ", TO); 655 func &= ~Op_TO; 656 } 657 if (func & Op_crfS) { 658 u_int crfS; 659 crfS = extract_field(instr, 31 - 13, 3); 660 pstr += sprintf(pstr, "%d, ", crfS); 661 func &= ~Op_crfS; 662 } 663 if (func & Op_BO) { 664 u_int BO; 665 BO = extract_field(instr, 31 - 10, 5); 666 pstr += sprintf(pstr, "%d, ", BO); 667 func &= ~Op_BO; 668 } 669 if (func & Op_A) { 670 u_int A; 671 A = extract_field(instr, 31 - 15, 5); 672 pstr += sprintf(pstr, "r%d, ", A); 673 func &= ~Op_A; 674 } 675 if (func & Op_B) { 676 u_int B; 677 B = extract_field(instr, 31 - 20, 5); 678 pstr += sprintf(pstr, "r%d, ", B); 679 func &= ~Op_B; 680 } 681 if (func & Op_C) { 682 u_int C; 683 C = extract_field(instr, 31 - 25, 5); 684 pstr += sprintf(pstr, "r%d, ", C); 685 func &= ~Op_C; 686 } 687 if (func & Op_BI) { 688 u_int BI; 689 BI = extract_field(instr, 31 - 10, 5); 690 pstr += sprintf(pstr, "%d, ", BI); 691 func &= ~Op_BI; 692 } 693 if (func & Op_crbA) { 694 u_int crbA; 695 crbA = extract_field(instr, 31 - 15, 5); 696 pstr += sprintf(pstr, "%d, ", crbA); 697 func &= ~Op_crbA; 698 } 699 if (func & Op_crbB) { 700 u_int crbB; 701 crbB = extract_field(instr, 31 - 20, 5); 702 pstr += sprintf(pstr, "%d, ", crbB); 703 func &= ~Op_crbB; 704 } 705 if (func & Op_CRM) { 706 u_int CRM; 707 CRM = extract_field(instr, 31 - 19, 8); 708 pstr += sprintf(pstr, "0x%x, ", CRM); 709 func &= ~Op_CRM; 710 } 711 if (func & Op_LI) { 712 int LI; 713 LI = extract_field(instr, 31 - 29, 24); 714 /* Need to sign extend and shift up 2, then add addr */ 715 LI = LI << 8; 716 LI = LI >> 6; 717 LI += loc; 718 db_symstr(pstr, LI, DB_STGY_ANY); 719 pstr += strlen(pstr); 720 func &= ~Op_LI; 721 } 722 switch (func & Op_SIMM) { 723 u_int IMM; 724 case Op_SIMM: /* same as Op_d */ 725 IMM = extract_field(instr, 31 - 31, 16); 726 if (IMM & 0x8000) { 727 pstr += sprintf(pstr, "-"); 728 IMM = 0x10000-IMM; 729 } 730 func &= ~Op_SIMM; 731 goto common; 732 case Op_UIMM: 733 IMM = extract_field(instr, 31 - 31, 16); 734 func &= ~Op_UIMM; 735 goto common; 736 common: 737 pstr += sprintf(pstr, "0x%x", IMM); 738 break; 739 default: 740 ; 741 } 742 if (func & Op_BD) { 743 u_int BD; 744 BD = extract_field(instr, 31 - 29, 14); 745 pstr += sprintf(pstr, "0x%x, ", BD); 746 func &= ~Op_BD; 747 } 748 if (func & Op_ds) { 749 u_int ds; 750 ds = extract_field(instr, 31 - 29, 14) << 2; 751 pstr += sprintf(pstr, "0x%x, ", ds); 752 func &= ~Op_ds; 753 } 754 if (func & Op_spr) { 755 u_int spr; 756 u_int sprl; 757 u_int sprh; 758 const struct specialreg *regs; 759 int i; 760 sprl = extract_field(instr, 31 - 15, 5); 761 sprh = extract_field(instr, 31 - 20, 5); 762 spr = sprh << 5 | sprl; 763 764 /* ugly hack - out of bitfields in the function mask */ 765 if (popcode->name[2] == 'd') /* m.Dcr */ 766 regs = dcrregs; 767 else 768 regs = sprregs; 769 for (i = 0; regs[i].name != NULL; i++) 770 if (spr == regs[i].reg) 771 break; 772 if (regs[i].reg == 0) 773 pstr += sprintf(pstr, "[unknown special reg (%d)]", spr); 774 else 775 pstr += sprintf(pstr, "%s", regs[i].name); 776 func &= ~Op_spr; 777 } 778 779 if (func & Op_me) { 780 u_int me, mel, meh; 781 mel = extract_field(instr, 31 - 25, 4); 782 meh = extract_field(instr, 31 - 26, 1); 783 me = meh << 4 | mel; 784 pstr += sprintf(pstr, ", 0x%x", me); 785 func &= ~Op_me; 786 } 787 if ((func & Op_MB) && (func & Op_sh_mb_sh)) { 788 u_int MB; 789 u_int ME; 790 MB = extract_field(instr, 31 - 20, 5); 791 pstr += sprintf(pstr, ", %d", MB); 792 ME = extract_field(instr, 31 - 25, 5); 793 pstr += sprintf(pstr, ", %d", ME); 794 } 795 if ((func & Op_SH) && (func & Op_sh_mb_sh)) { 796 u_int SH; 797 SH = extract_field(instr, 31 - 20, 5); 798 pstr += sprintf(pstr, ", %d", SH); 799 } 800 if ((func & Op_sh) && ! (func & Op_sh_mb_sh)) { 801 u_int sh, shl, shh; 802 shl = extract_field(instr, 31 - 19, 4); 803 shh = extract_field(instr, 31 - 20, 1); 804 sh = shh << 4 | shl; 805 pstr += sprintf(pstr, ", %d", sh); 806 } 807 if ((func & Op_mb) && ! (func & Op_sh_mb_sh)) { 808 u_int mb, mbl, mbh; 809 mbl = extract_field(instr, 31 - 25, 4); 810 mbh = extract_field(instr, 31 - 26, 1); 811 mb = mbh << 4 | mbl; 812 pstr += sprintf(pstr, ", %d", mb); 813 } 814 if ((func & Op_me) && ! (func & Op_sh_mb_sh)) { 815 u_int me, mel, meh; 816 mel = extract_field(instr, 31 - 25, 4); 817 meh = extract_field(instr, 31 - 26, 1); 818 me = meh << 4 | mel; 819 pstr += sprintf(pstr, ", %d", me); 820 } 821 if (func & Op_tbr) { 822 u_int tbr; 823 u_int tbrl; 824 u_int tbrh; 825 char *reg; 826 tbrl = extract_field(instr, 31 - 15, 5); 827 tbrh = extract_field(instr, 31 - 20, 5); 828 tbr = tbrh << 5 | tbrl; 829 830 switch (tbr) { 831 case 268: 832 reg = "tbl"; 833 break; 834 case 269: 835 reg = "tbu"; 836 break; 837 default: 838 reg = 0; 839 } 840 if (reg == 0) 841 pstr += sprintf(pstr, ", [unknown tbr %d ]", tbr); 842 else 843 pstr += sprintf(pstr, ", %s", reg); 844 func &= ~Op_tbr; 845 } 846 if (func & Op_SR) { 847 u_int SR; 848 SR = extract_field(instr, 31 - 15, 3); 849 pstr += sprintf(pstr, ", sr%d", SR); 850 func &= ~Op_SR; 851 } 852 if (func & Op_NB) { 853 u_int NB; 854 NB = extract_field(instr, 31 - 20, 5); 855 if (NB == 0) 856 NB = 32; 857 pstr += sprintf(pstr, ", %d", NB); 858 func &= ~Op_SR; 859 } 860 if (func & Op_IMM) { 861 u_int IMM; 862 IMM = extract_field(instr, 31 - 19, 4); 863 pstr += sprintf(pstr, ", %d", IMM); 864 func &= ~Op_SR; 865 } 866 } 867 868 void 869 op_base(instr_t instr, vaddr_t loc) 870 { 871 dis_ppc(opcodes, instr, loc); 872 } 873 874 void 875 op_cl_x13(instr_t instr, vaddr_t loc) 876 { 877 dis_ppc(opcodes_13, instr, loc); 878 } 879 880 void 881 op_cl_x1e(instr_t instr, vaddr_t loc) 882 { 883 dis_ppc(opcodes_1e, instr, loc); 884 } 885 886 void 887 op_cl_x1f(instr_t instr, vaddr_t loc) 888 { 889 dis_ppc(opcodes_1f, instr, loc); 890 } 891 892 void 893 op_cl_x3a(instr_t instr, vaddr_t loc) 894 { 895 dis_ppc(opcodes_3a, instr, loc); 896 } 897 898 void 899 op_cl_x3b(instr_t instr, vaddr_t loc) 900 { 901 dis_ppc(opcodes_3b, instr, loc); 902 } 903 904 void 905 op_cl_x3e(instr_t instr, vaddr_t loc) 906 { 907 dis_ppc(opcodes_3e, instr, loc); 908 } 909 910 void 911 op_cl_x3f(instr_t instr, vaddr_t loc) 912 { 913 dis_ppc(opcodes_3f, instr, loc); 914 } 915 916 void 917 dis_ppc(const struct opcode *opcodeset, instr_t instr, vaddr_t loc) 918 { 919 const struct opcode *op; 920 int found = 0; 921 int i; 922 char disasm_str[30]; 923 924 for (i = 0, op = &opcodeset[0]; 925 found == 0 && op->mask != 0; 926 i++, op = &opcodeset[i]) { 927 if ((instr & op->mask) == op->code) { 928 found = 1; 929 disasm_fields(op, instr, loc, disasm_str); 930 db_printf("%s%s\n", op->name, disasm_str); 931 return; 932 } 933 } 934 op_ill(instr, loc); 935 } 936 937 db_addr_t 938 db_disasm(db_addr_t loc, boolean_t extended) 939 { 940 int class; 941 instr_t opcode; 942 opcode = *(instr_t *)(loc); 943 class = opcode >> 26; 944 (opcodes_base[class])(opcode, loc); 945 946 return (loc + 4); 947 } 948 949 vaddr_t opc_disasm(vaddr_t loc, int); 950 951 vaddr_t 952 opc_disasm(vaddr_t loc, int xin) 953 { 954 int class; 955 instr_t opcode; 956 opcode = xin; 957 class = opcode >> 26; 958 (opcodes_base[class])(opcode, loc); 959 960 return (loc + 4); 961 } 962