1 /* $NetBSD: cpu.c,v 1.9 2002/10/02 15:52:31 thorpej Exp $ */ 2 3 /* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. Neither the "Broadcom Corporation" name nor any 19 * trademark or logo of Broadcom Corporation may be used to endorse or 20 * promote products derived from this software without the prior written 21 * permission of Broadcom Corporation. 22 * 23 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 26 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 27 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 28 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/device.h> 38 #include <sys/kernel.h> 39 #include <sys/systm.h> 40 41 #include <mips/locore.h> 42 #include <mips/cache.h> 43 44 #include <machine/cpu.h> 45 46 #include <mips/sibyte/include/zbbusvar.h> 47 #include <mips/sibyte/include/sb1250_regs.h> 48 #include <mips/sibyte/include/sb1250_scd.h> 49 #include <mips/sibyte/dev/sbscdvar.h> 50 51 #define READ_REG(rp) (mips3_ld((uint64_t *)(rp))) 52 53 static int cpu_match(struct device *, struct cfdata *, void *); 54 static void cpu_attach(struct device *, struct device *, void *); 55 56 CFATTACH_DECL(cpu, sizeof(struct device), 57 cpu_match, cpu_attach, NULL, NULL); 58 59 static int found = 0; 60 61 static int 62 cpu_match(struct device *parent, struct cfdata *match, void *aux) 63 { 64 struct zbbus_attach_args *zap = aux; 65 int part; 66 67 if (zap->za_locs.za_type != ZBBUS_ENTTYPE_CPU) 68 return (0); 69 70 /* 71 * The 3rd hex digit of the part number is the number of CPUs; 72 * ref Table 26, p38 1250-UM101-R. 73 */ 74 part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION))); 75 return (found < ((part >> 8) & 0xf)); 76 } 77 78 static void 79 cpu_attach(struct device *parent, struct device *self, void *aux) 80 { 81 int plldiv; 82 uint32_t config; 83 84 /* XXX this code must run on the target cpu */ 85 config = mips3_cp0_config_read(); 86 config &= ~MIPS3_CONFIG_K0_MASK; 87 config |= 0x05; /* XXX. cacheable coherent */ 88 mips3_cp0_config_write(config); 89 90 found++; 91 92 /* 93 * Flush all of the caches, so that any lines marked non-coherent will 94 * be flushed. Don't need to worry about L2; it's always 95 * coherent (XXX???). 96 */ 97 mips_icache_sync_all(); 98 mips_dcache_wbinv_all(); 99 100 /* Determine CPU frequency */ 101 102 /* XXX: We should determine the CPU frequency from a time source 103 * not coupled with the CPU crystal, like the RTC. Unfortunately 104 * we don't attach that yet... 105 */ 106 plldiv = G_SYS_PLL_DIV(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG))); 107 if (plldiv == 0) { 108 printf("PLL_DIV of zero found, assuming 6 (300MHz)\n"); 109 plldiv = 6; 110 111 printf("%s", self->dv_xname); 112 } 113 114 curcpu()->ci_cpu_freq = 50000000 * plldiv; 115 /* Compute the delay divisor and reciprical. */ 116 curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / 1000000; 117 MIPS_SET_CI_RECIPRICAL(curcpu()); 118 /* Compute clock cycles per hz */ 119 curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / hz; 120 121 printf(": %lu.%02luMHz (hz cycles = %lu, delay divisor = %lu)\n", 122 curcpu()->ci_cpu_freq / 1000000, 123 (curcpu()->ci_cpu_freq % 1000000) / 10000, 124 curcpu()->ci_cycles_per_hz, curcpu()->ci_divisor_delay); 125 126 /* 127 * If we're the primary CPU, no more work to do; we're already 128 * running! 129 */ 130 if (found == 1) { 131 printf("%s: ", self->dv_xname); 132 cpu_identify(); 133 } else { 134 #if defined(MULTIPROCESSOR) 135 # error! 136 #else 137 printf("%s: processor off-line; multiprocessor support " 138 "not present in kernel\n", /* sc->sc_dev. */self->dv_xname); 139 #endif 140 } 141 } 142