1 /* $NetBSD: zs.c,v 1.10 2002/05/02 20:26:49 rafal Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross and Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include "opt_ddb.h" 47 #include "opt_kgdb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/conf.h> 52 #include <sys/device.h> 53 #include <sys/file.h> 54 #include <sys/ioctl.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> 57 #include <sys/tty.h> 58 #include <sys/time.h> 59 #include <sys/syslog.h> 60 61 #include <machine/cpu.h> 62 #include <machine/intr.h> 63 #include <machine/autoconf.h> 64 #include <machine/z8530var.h> 65 66 #include <dev/cons.h> 67 #include <dev/ic/z8530reg.h> 68 69 #include <sgimips/hpc/hpcvar.h> 70 #include <sgimips/hpc/hpcreg.h> 71 72 #include <dev/arcbios/arcbios.h> 73 #include <dev/arcbios/arcbiosvar.h> 74 75 /* 76 * Some warts needed by z8530tty.c - 77 * The default parity REALLY needs to be the same as the PROM uses, 78 * or you can not see messages done with printf during boot-up... 79 */ 80 int zs_def_cflag = (CREAD | CS8 | HUPCL); 81 int zs_major = 0; 82 83 #define PCLK 3672000 /* PCLK pin input clock rate */ 84 85 #ifndef ZS_DEFSPEED 86 #define ZS_DEFSPEED 9600 87 #endif 88 89 /* 90 * Define interrupt levels. 91 */ 92 #define ZSHARD_PRI 64 93 94 /* SGI shouldn't need ZS_DELAY() as recovery time is done in hardware? */ 95 #define ZS_DELAY() delay(3) 96 97 /* The layout of this is hardware-dependent (padding, order). */ 98 struct zschan { 99 u_char pad1[3]; 100 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 101 u_char pad2[3]; 102 volatile u_char zc_data; /* data */ 103 }; 104 105 struct zsdevice { 106 struct zschan zs_chan_b; 107 struct zschan zs_chan_a; 108 }; 109 110 /* Return the byte offset of element within a structure */ 111 #define OFFSET(struct_def, el) ((size_t)&((struct_def *)0)->el) 112 113 #define ZS_CHAN_A OFFSET(struct zsdevice, zs_chan_a) 114 #define ZS_CHAN_B OFFSET(struct zsdevice, zs_chan_b) 115 #define ZS_REG_CSR 0 116 #define ZS_REG_DATA 1 117 static int zs_chan_offset[] = {ZS_CHAN_A, ZS_CHAN_B}; 118 119 static void zscnprobe __P((struct consdev *)); 120 static void zscninit __P((struct consdev *)); 121 static int zscngetc __P((dev_t)); 122 static void zscnputc __P((dev_t, int)); 123 static void zscnpollc __P((dev_t, int)); 124 125 static int cons_port; 126 127 struct consdev zs_cn = { 128 zscnprobe, 129 zscninit, 130 zscngetc, 131 zscnputc, 132 zscnpollc 133 }; 134 135 /* Flags from cninit() */ 136 static int zs_consunit = -1; 137 static int zs_conschan = -1; 138 139 /* Default speed for all channels */ 140 static int zs_defspeed = ZS_DEFSPEED; 141 static volatile int zssoftpending; 142 143 static u_char zs_init_reg[16] = { 144 0, /* 0: CMD (reset, etc.) */ 145 0, /* 1: No interrupts yet. */ 146 ZSHARD_PRI, /* 2: IVECT */ 147 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 148 ZSWR4_CLK_X16 | ZSWR4_ONESB, 149 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 150 0, /* 6: TXSYNC/SYNCLO */ 151 0, /* 7: RXSYNC/SYNCHI */ 152 0, /* 8: alias for data port */ 153 ZSWR9_MASTER_IE, 154 0, /*10: Misc. TX/RX control bits */ 155 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD | ZSWR11_TRXC_OUT_ENA, 156 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */ 157 0, /*13: BAUDHI (default=9600) */ 158 ZSWR14_BAUD_ENA, 159 ZSWR15_BREAK_IE, 160 }; 161 162 163 /**************************************************************** 164 * Autoconfig 165 ****************************************************************/ 166 167 /* Definition of the driver for autoconfig. */ 168 static int zs_hpc_match __P((struct device *, struct cfdata *, void *)); 169 static void zs_hpc_attach __P((struct device *, struct device *, void *)); 170 static int zs_print __P((void *, const char *name)); 171 172 struct cfattach zsc_hpc_ca = { 173 sizeof(struct zsc_softc), zs_hpc_match, zs_hpc_attach 174 }; 175 176 cdev_decl(zs); 177 extern struct cfdriver zsc_cd; 178 179 static int zshard __P((void *)); 180 void zssoft __P((void *)); 181 static int zs_get_speed __P((struct zs_chanstate *)); 182 struct zschan *zs_get_chan_addr (int zs_unit, int channel); 183 int zs_getc __P((void *)); 184 void zs_putc __P((void *, int)); 185 186 /* 187 * Is the zs chip present? 188 */ 189 static int 190 zs_hpc_match(parent, cf, aux) 191 struct device *parent; 192 struct cfdata *cf; 193 void *aux; 194 { 195 struct hpc_attach_args *ha = aux; 196 197 if (strcmp(ha->ha_name, cf->cf_driver->cd_name) == 0) 198 return (1); 199 200 return (0); 201 } 202 203 /* 204 * Attach a found zs. 205 * 206 * Match slave number to zs unit number, so that misconfiguration will 207 * not set up the keyboard as ttya, etc. 208 */ 209 static void 210 zs_hpc_attach(parent, self, aux) 211 struct device *parent; 212 struct device *self; 213 void *aux; 214 { 215 struct zsc_softc *zsc = (void *) self; 216 struct hpc_attach_args *haa = aux; 217 struct zsc_attach_args zsc_args; 218 struct zs_chanstate *cs; 219 struct zs_channel *ch; 220 int zs_unit, channel, err, s; 221 char *promconsdev; 222 223 promconsdev = ARCBIOS->GetEnvironmentVariable("ConsoleOut"); 224 225 zsc->zsc_bustag = haa->ha_st; 226 if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh, 227 haa->ha_devoff, 0x10, 228 &zsc->zsc_base)) != 0) { 229 printf(": unable to map 85c30 registers, error = %d\n", err); 230 return; 231 } 232 233 zs_unit = zsc->zsc_dev.dv_unit; 234 printf("\n"); 235 236 /* 237 * Initialize software state for each channel. 238 * 239 * Done in reverse order of channels since the first serial port 240 * is actually attached to the *second* channel, and vice versa. 241 * Doing it this way should force a 'zstty*' to attach zstty0 to 242 * channel 1 and zstty1 to channel 0. They couldn't have wired 243 * it up in a more sensible fashion, could they? 244 */ 245 for (channel = 1; channel >= 0; channel--) { 246 zsc_args.channel = channel; 247 ch = &zsc->zsc_cs_store[channel]; 248 cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch; 249 250 cs->cs_reg_csr = NULL; 251 cs->cs_reg_data = NULL; 252 cs->cs_channel = channel; 253 cs->cs_private = NULL; 254 cs->cs_ops = &zsops_null; 255 cs->cs_brg_clk = PCLK / 16; 256 257 if (bus_space_subregion(zsc->zsc_bustag, zsc->zsc_base, 258 zs_chan_offset[channel], 259 sizeof(struct zschan), 260 &ch->cs_regs) != 0) { 261 printf(": cannot map regs\n"); 262 return; 263 } 264 ch->cs_bustag = zsc->zsc_bustag; 265 266 memcpy(cs->cs_creg, zs_init_reg, 16); 267 memcpy(cs->cs_preg, zs_init_reg, 16); 268 269 zsc_args.hwflags = 0; 270 zsc_args.consdev = NULL; 271 272 if (zs_consunit == -1 && zs_conschan == -1) { 273 /* 274 * If this channel is being used by the PROM console, 275 * pass the generic zs driver a 'no reset' flag so the 276 * channel gets left in the appropriate state after 277 * attach. 278 * 279 * Note: the channel mappings are swapped. 280 */ 281 if (promconsdev != NULL && 282 strlen(promconsdev) == 9 && 283 strncmp(promconsdev, "serial", 6) == 0 && 284 (promconsdev[7] == '0' || promconsdev[7] == '1')) { 285 if (promconsdev[7] == '1' && channel == 0) 286 zsc_args.hwflags |= ZS_HWFLAG_NORESET; 287 else if (promconsdev[7] == '0' && channel == 1) 288 zsc_args.hwflags |= ZS_HWFLAG_NORESET; 289 } 290 } 291 292 /* If console, don't stomp speed, let zstty know */ 293 if (zs_unit == zs_consunit && channel == zs_conschan) { 294 zsc_args.consdev = &zs_cn; 295 zsc_args.hwflags = ZS_HWFLAG_CONSOLE; 296 297 cs->cs_defspeed = zs_get_speed(cs); 298 } else 299 cs->cs_defspeed = zs_defspeed; 300 301 cs->cs_defcflag = zs_def_cflag; 302 303 /* Make these correspond to cs_defcflag (-crtscts) */ 304 cs->cs_rr0_dcd = ZSRR0_DCD; 305 cs->cs_rr0_cts = 0; 306 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 307 cs->cs_wr5_rts = 0; 308 309 /* 310 * Clear the master interrupt enable. 311 * The INTENA is common to both channels, 312 * so just do it on the A channel. 313 */ 314 if (channel == 0) { 315 zs_write_reg(cs, 9, 0); 316 } 317 /* 318 * Look for a child driver for this channel. 319 * The child attach will setup the hardware. 320 */ 321 if (!config_found(self, (void *)&zsc_args, zs_print)) { 322 /* No sub-driver. Just reset it. */ 323 u_char reset = (channel == 0) ? 324 ZSWR9_A_RESET : ZSWR9_B_RESET; 325 326 s = splhigh(); 327 zs_write_reg(cs, 9, reset); 328 splx(s); 329 } 330 } 331 332 333 zsc->sc_si = softintr_establish(IPL_SOFTSERIAL, zssoft, zsc); 334 cpu_intr_establish(haa->ha_irq, IPL_TTY, zshard, NULL); 335 336 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 337 self->dv_xname, "intr"); 338 339 /* 340 * Set the master interrupt enable and interrupt vector. 341 * (common to both channels, do it on A) 342 */ 343 cs = zsc->zsc_cs[0]; 344 s = splhigh(); 345 /* interrupt vector */ 346 zs_write_reg(cs, 2, zs_init_reg[2]); 347 /* master interrupt control (enable) */ 348 zs_write_reg(cs, 9, zs_init_reg[9]); 349 splx(s); 350 } 351 352 static int 353 zs_print(aux, name) 354 void *aux; 355 const char *name; 356 { 357 struct zsc_attach_args *args = aux; 358 359 if (name != NULL) 360 printf("%s: ", name); 361 362 if (args->channel != -1) 363 printf(" channel %d", args->channel); 364 365 return UNCONF; 366 } 367 368 /* 369 * Our ZS chips all share a common, autovectored interrupt, 370 * so we have to look at all of them on each interrupt. 371 */ 372 static int 373 zshard(arg) 374 void *arg; 375 { 376 register struct zsc_softc *zsc; 377 register int rr3, unit, rval, softreq; 378 379 rval = 0; 380 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 381 zsc = zsc_cd.cd_devs[unit]; 382 if (zsc == NULL) 383 continue; 384 385 zsc->zsc_intrcnt.ev_count++; 386 while ((rr3 = zsc_intr_hard(zsc))) { 387 rval |= rr3; 388 } 389 390 softreq = zsc->zsc_cs[0]->cs_softreq; 391 softreq |= zsc->zsc_cs[1]->cs_softreq; 392 if (softreq && (zssoftpending == 0)) { 393 zssoftpending = 1; 394 softintr_schedule(zsc->sc_si); 395 } 396 } 397 return rval; 398 } 399 400 /* 401 * Similar scheme as for zshard (look at all of them) 402 */ 403 void 404 zssoft(arg) 405 void *arg; 406 { 407 register struct zsc_softc *zsc; 408 register int s, unit; 409 410 /* This is not the only ISR on this IPL. */ 411 if (zssoftpending == 0) 412 return; 413 414 /* 415 * The soft intr. bit will be set by zshard only if 416 * the variable zssoftpending is zero. The order of 417 * these next two statements prevents our clearing 418 * the soft intr bit just after zshard has set it. 419 */ 420 /*isr_soft_clear(ZSSOFT_PRI);*/ 421 zssoftpending = 0; 422 423 /* Make sure we call the tty layer at spltty. */ 424 s = spltty(); 425 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 426 zsc = zsc_cd.cd_devs[unit]; 427 if (zsc == NULL) 428 continue; 429 (void) zsc_intr_soft(zsc); 430 } 431 splx(s); 432 return; 433 } 434 435 436 /* 437 * Compute the current baud rate given a ZS channel. 438 */ 439 static int 440 zs_get_speed(cs) 441 struct zs_chanstate *cs; 442 { 443 int tconst; 444 445 tconst = zs_read_reg(cs, 12); 446 tconst |= zs_read_reg(cs, 13) << 8; 447 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 448 } 449 450 /* 451 * MD functions for setting the baud rate and control modes. 452 */ 453 int 454 zs_set_speed(cs, bps) 455 struct zs_chanstate *cs; 456 int bps; /* bits per second */ 457 { 458 int tconst, real_bps; 459 460 #if 0 461 while (!(zs_read_csr(cs) & ZSRR0_TX_READY)) 462 {/*nop*/} 463 #endif 464 /* Wait for transmit buffer to empty */ 465 if (bps == 0) { 466 return (0); 467 } 468 469 #ifdef DIAGNOSTIC 470 if (cs->cs_brg_clk == 0) 471 panic("zs_set_speed"); 472 #endif 473 474 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 475 if (tconst < 0) 476 return (EINVAL); 477 478 /* Convert back to make sure we can do it. */ 479 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 480 481 /* XXX - Allow some tolerance here? */ 482 #if 0 483 if (real_bps != bps) 484 return (EINVAL); 485 #endif 486 487 cs->cs_preg[12] = tconst; 488 cs->cs_preg[13] = tconst >> 8; 489 490 /* Caller will stuff the pending registers. */ 491 return (0); 492 } 493 494 int 495 zs_set_modes(cs, cflag) 496 struct zs_chanstate *cs; 497 int cflag; /* bits per second */ 498 { 499 int s; 500 501 /* 502 * Output hardware flow control on the chip is horrendous: 503 * if carrier detect drops, the receiver is disabled, and if 504 * CTS drops, the transmitter is stoped IN MID CHARACTER! 505 * Therefore, NEVER set the HFC bit, and instead use the 506 * status interrupt to detect CTS changes. 507 */ 508 s = splzs(); 509 cs->cs_rr0_pps = 0; 510 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 511 cs->cs_rr0_dcd = 0; 512 if ((cflag & MDMBUF) == 0) 513 cs->cs_rr0_pps = ZSRR0_DCD; 514 } else 515 cs->cs_rr0_dcd = ZSRR0_DCD; 516 if ((cflag & CRTSCTS) != 0) { 517 cs->cs_wr5_dtr = ZSWR5_DTR; 518 cs->cs_wr5_rts = ZSWR5_RTS; 519 cs->cs_rr0_cts = ZSRR0_CTS; 520 } else if ((cflag & MDMBUF) != 0) { 521 cs->cs_wr5_dtr = 0; 522 cs->cs_wr5_rts = ZSWR5_DTR; 523 cs->cs_rr0_cts = ZSRR0_DCD; 524 } else { 525 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 526 cs->cs_wr5_rts = 0; 527 cs->cs_rr0_cts = 0; 528 } 529 splx(s); 530 531 /* Caller will stuff the pending registers. */ 532 return (0); 533 } 534 535 536 /* 537 * Read or write the chip with suitable delays. 538 */ 539 540 u_char 541 zs_read_reg(cs, reg) 542 struct zs_chanstate *cs; 543 u_char reg; 544 { 545 u_char val; 546 struct zs_channel *zsc = (struct zs_channel *)cs; 547 548 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 549 ZS_DELAY(); 550 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 551 ZS_DELAY(); 552 return val; 553 } 554 555 void 556 zs_write_reg(cs, reg, val) 557 struct zs_chanstate *cs; 558 u_char reg, val; 559 { 560 struct zs_channel *zsc = (struct zs_channel *)cs; 561 562 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 563 ZS_DELAY(); 564 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 565 ZS_DELAY(); 566 } 567 568 u_char 569 zs_read_csr(cs) 570 struct zs_chanstate *cs; 571 { 572 struct zs_channel *zsc = (struct zs_channel *)cs; 573 register u_char val; 574 575 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 576 ZS_DELAY(); 577 return val; 578 } 579 580 void 581 zs_write_csr(cs, val) 582 struct zs_chanstate *cs; 583 u_char val; 584 { 585 struct zs_channel *zsc = (struct zs_channel *)cs; 586 587 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 588 ZS_DELAY(); 589 } 590 591 u_char 592 zs_read_data(cs) 593 struct zs_chanstate *cs; 594 { 595 struct zs_channel *zsc = (struct zs_channel *)cs; 596 register u_char val; 597 598 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA); 599 ZS_DELAY(); 600 return val; 601 } 602 603 void 604 zs_write_data(cs, val) 605 struct zs_chanstate *cs; 606 u_char val; 607 { 608 struct zs_channel *zsc = (struct zs_channel *)cs; 609 610 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA, val); 611 ZS_DELAY(); 612 } 613 614 void 615 zs_abort(cs) 616 struct zs_chanstate *cs; 617 { 618 #if defined(KGDB) 619 zskgdb(cs); 620 #elif defined(DDB) 621 Debugger(); 622 #endif 623 } 624 625 626 /*********************************************************/ 627 /* Polled character I/O functions for console and KGDB */ 628 /*********************************************************/ 629 630 struct zschan * 631 zs_get_chan_addr(zs_unit, channel) 632 int zs_unit, channel; 633 { 634 static int dumped_addr = 0; 635 struct zsdevice *addr; 636 struct zschan *zc; 637 638 addr = (struct zsdevice *) MIPS_PHYS_TO_KSEG1(0x1fbd9830); 639 640 if (channel == 0) { 641 zc = &addr->zs_chan_b; 642 } else { 643 zc = &addr->zs_chan_a; 644 } 645 646 if (dumped_addr == 0) { 647 dumped_addr++; 648 printf("zs channel %d had address %p\n", channel, zc); 649 } 650 651 return (zc); 652 } 653 654 int 655 zs_getc(arg) 656 void *arg; 657 { 658 register volatile struct zschan *zc = arg; 659 register int s, c, rr0; 660 661 s = splzs(); 662 /* Wait for a character to arrive. */ 663 do { 664 rr0 = zc->zc_csr; 665 ZS_DELAY(); 666 } while ((rr0 & ZSRR0_RX_READY) == 0); 667 668 c = zc->zc_data; 669 ZS_DELAY(); 670 splx(s); 671 672 return (c); 673 } 674 675 /* 676 * Polled output char. 677 */ 678 void 679 zs_putc(arg, c) 680 void *arg; 681 int c; 682 { 683 register volatile struct zschan *zc = arg; 684 register int s, rr0; 685 686 s = splzs(); 687 /* Wait for transmitter to become ready. */ 688 do { 689 rr0 = zc->zc_csr; 690 ZS_DELAY(); 691 } while ((rr0 & ZSRR0_TX_READY) == 0); 692 693 zc->zc_data = c; 694 wbflush(); 695 ZS_DELAY(); 696 splx(s); 697 } 698 699 /***************************************************************/ 700 void 701 zscnprobe(cn) 702 struct consdev *cn; 703 { 704 } 705 706 void 707 zscninit(cn) 708 struct consdev *cn; 709 { 710 char* consdev; 711 712 if ((consdev = ARCBIOS->GetEnvironmentVariable("ConsoleOut")) == NULL) 713 panic("zscninit without valid ARCS ConsoleOut setting!\n"); 714 715 if (strlen(consdev) != 9 || 716 strncmp(consdev, "serial", 6) != 0) 717 panic("zscninit with ARCS console not set to serial!\n"); 718 719 cons_port = consdev[7] - '0'; 720 721 /* 722 * Initialize the zstty console device major (needed by cnopen) 723 */ 724 for (zs_major = 0; zs_major < nchrdev; zs_major++) 725 if (cdevsw[zs_major].d_open == zsopen) 726 break; 727 728 cn->cn_dev = makedev(zs_major, cons_port); 729 cn->cn_pri = CN_REMOTE; 730 731 /* Mark this unit as the console */ 732 zs_consunit = 0; 733 734 /* SGI hardware wires serial port 1 to channel B, port 2 to A */ 735 if (cons_port == 0) 736 zs_conschan = 1; 737 else 738 zs_conschan = 0; 739 } 740 741 int 742 zscngetc(dev) 743 dev_t dev; 744 { 745 struct zschan *zs; 746 747 zs = zs_get_chan_addr(0, cons_port); 748 return zs_getc(zs); 749 } 750 751 void 752 zscnputc(dev, c) 753 dev_t dev; 754 int c; 755 { 756 struct zschan *zs; 757 758 zs = zs_get_chan_addr(0, cons_port); 759 zs_putc(zs, c); 760 } 761 762 void 763 zscnpollc(dev, on) 764 dev_t dev; 765 int on; 766 { 767 } 768