1 /* $NetBSD: hpcdma.c,v 1.20 2011/01/25 12:30:32 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wayne Knowles 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Support for SCSI DMA provided by the HPC. 41 * 42 * Note: We use SCSI0 offsets, etc. here. Since the layout of SCSI0 43 * and SCSI1 are the same, this is no problem. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: hpcdma.c,v 1.20 2011/01/25 12:30:32 tsutsui Exp $"); 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/buf.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <machine/bus.h> 57 58 #include <sgimips/hpc/hpcvar.h> 59 #include <sgimips/hpc/hpcreg.h> 60 #include <sgimips/hpc/hpcdma.h> 61 62 /* 63 * Allocate DMA Chain descriptor list 64 */ 65 void 66 hpcdma_init(struct hpc_attach_args *haa, struct hpc_dma_softc *sc, int ndesc) 67 { 68 bus_dma_segment_t seg; 69 int rseg, allocsz; 70 71 sc->sc_bst = haa->ha_st; 72 sc->sc_dmat = haa->ha_dmat; 73 sc->sc_ndesc = ndesc; 74 sc->sc_flags = 0; 75 76 if (bus_space_subregion(haa->ha_st, haa->ha_sh, haa->ha_dmaoff, 77 sc->hpc->scsi0_regs_size, &sc->sc_bsh) != 0) { 78 printf(": can't map DMA registers\n"); 79 return; 80 } 81 82 /* Alloc 1 additional descriptor - needed for DMA bug fix */ 83 allocsz = sizeof(struct hpc_dma_desc) * (ndesc + 1); 84 85 /* 86 * Allocate a block of memory for dma chaining pointers 87 */ 88 if (bus_dmamem_alloc(sc->sc_dmat, allocsz, 0, 0, &seg, 1, &rseg, 89 BUS_DMA_NOWAIT)) { 90 printf(": can't allocate sglist\n"); 91 return; 92 } 93 /* Map pages into kernel memory */ 94 if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, allocsz, 95 (void **)&sc->sc_desc_kva, BUS_DMA_NOWAIT)) { 96 printf(": can't map sglist\n"); 97 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 98 return; 99 } 100 101 if (bus_dmamap_create(sc->sc_dmat, allocsz, 1 /*seg*/, allocsz, 0, 102 BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) { 103 printf(": failed to create dmamap\n"); 104 return; 105 } 106 107 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 108 sc->sc_desc_kva, allocsz, NULL, BUS_DMA_NOWAIT)) { 109 printf(": can't load sglist\n"); 110 return; 111 } 112 113 sc->sc_desc_pa = sc->sc_dmamap->dm_segs[0].ds_addr; 114 } 115 116 117 void 118 hpcdma_sglist_create(struct hpc_dma_softc *sc, bus_dmamap_t dmamap) 119 { 120 struct hpc_dma_desc *hva; 121 bus_addr_t hpa; 122 bus_dma_segment_t *segp; 123 int i; 124 125 KASSERT(dmamap->dm_nsegs <= sc->sc_ndesc); 126 127 hva = sc->sc_desc_kva; 128 hpa = sc->sc_desc_pa; 129 segp = dmamap->dm_segs; 130 131 #ifdef DMA_DEBUG 132 printf("DMA_SGLIST<"); 133 #endif 134 for (i = dmamap->dm_nsegs; i; i--) { 135 #ifdef DMA_DEBUG 136 printf("%p:%ld, ", (void *)segp->ds_addr, segp->ds_len); 137 #endif 138 hpa += sizeof(struct hpc_dma_desc); /* next chain desc */ 139 if (sc->hpc->revision == 3) { 140 hva->hpc3_hdd_bufptr = segp->ds_addr; 141 hva->hpc3_hdd_ctl = segp->ds_len; 142 hva->hdd_descptr = hpa; 143 } else /* HPC 1/1.5 */ { 144 /* 145 * there doesn't seem to be any good way of doing this 146 * via an abstraction layer 147 */ 148 hva->hpc1_hdd_bufptr = segp->ds_addr; 149 hva->hpc1_hdd_ctl = segp->ds_len; 150 hva->hdd_descptr = hpa; 151 } 152 ++hva; 153 ++segp; 154 } 155 156 /* Work around HPC3 DMA bug */ 157 if (sc->hpc->revision == 3) { 158 hva->hpc3_hdd_bufptr = 0; 159 hva->hpc3_hdd_ctl = HPC3_HDD_CTL_EOCHAIN; 160 hva->hdd_descptr = 0; 161 } else { 162 hva--; 163 hva->hpc1_hdd_bufptr |= HPC1_HDD_CTL_EOCHAIN; 164 hva->hdd_descptr = 0; 165 } 166 167 #ifdef DMA_DEBUG 168 printf(">\n"); 169 #endif 170 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 171 0, sizeof(struct hpc_dma_desc) * (dmamap->dm_nsegs + 1), 172 BUS_DMASYNC_PREWRITE); 173 174 /* Load DMA Descriptor list */ 175 bus_space_write_4(sc->sc_bst, sc->sc_bsh, sc->hpc->scsi0_ndbp, 176 sc->sc_desc_pa); 177 } 178 179 void 180 hpcdma_cntl(struct hpc_dma_softc *sc, uint32_t mode) 181 { 182 183 bus_space_write_4(sc->sc_bst, sc->sc_bsh, sc->hpc->scsi0_ctl, mode); 184 } 185 186 void 187 hpcdma_reset(struct hpc_dma_softc *sc) 188 { 189 190 bus_space_write_4(sc->sc_bst, sc->sc_bsh, sc->hpc->scsi0_ctl, 191 sc->hpc->scsi_dmactl_reset); 192 delay(100); 193 bus_space_write_4(sc->sc_bst, sc->sc_bsh, sc->hpc->scsi0_ctl, 0); 194 delay(1000); 195 } 196 197 void 198 hpcdma_flush(struct hpc_dma_softc *sc) 199 { 200 uint32_t mode; 201 202 mode = bus_space_read_4(sc->sc_bst, sc->sc_bsh, sc->hpc->scsi0_ctl); 203 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 204 sc->hpc->scsi0_ctl, mode | sc->hpc->scsi_dmactl_flush); 205 206 /* Wait for Active bit to drop */ 207 while (bus_space_read_4(sc->sc_bst, sc->sc_bsh, sc->hpc->scsi0_ctl) & 208 sc->hpc->scsi_dmactl_active) { 209 bus_space_barrier(sc->sc_bst, sc->sc_bsh, sc->hpc->scsi0_ctl, 4, 210 BUS_SPACE_BARRIER_READ); 211 } 212 } 213