xref: /netbsd/sys/arch/sgimips/hpc/hpcdma.c (revision bf9ec67e)
1 /*	$NetBSD: hpcdma.c,v 1.4 2002/03/13 13:12:27 simonb Exp $	*/
2 
3 /*
4  * Copyright (c) 2001 Wayne Knowles
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Wayne Knowles
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*
40  * Support for SCSI DMA provided by the HPC.
41  *
42  * Note: We use SCSI0 offsets, etc. here.  Since the layout of SCSI0
43  * and SCSI1 are the same, this is no problem.
44  */
45 
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/device.h>
49 #include <sys/buf.h>
50 
51 #include <machine/bus.h>
52 
53 #include <sgimips/hpc/hpcvar.h>
54 #include <sgimips/hpc/hpcreg.h>
55 #include <sgimips/hpc/hpcdma.h>
56 
57 /*
58  * Allocate DMA Chain descriptor list
59  */
60 void
61 hpcdma_init(struct hpc_attach_args *haa, struct hpc_dma_softc *sc, int ndesc)
62 {
63 	bus_dma_segment_t seg;
64 	struct hpc_dma_desc *hdd;
65 	int rseg, allocsz;
66 
67 	sc->sc_bst = haa->ha_st;
68 	sc->sc_dmat = haa->ha_dmat;
69 	sc->sc_ndesc = ndesc;
70 	sc->sc_flags = 0;
71 
72 	if (bus_space_subregion(haa->ha_st, haa->ha_sh, haa->ha_dmaoff,
73 	    HPC_SCSI0_REGS_SIZE, &sc->sc_bsh) != 0) {
74 		printf(": can't map DMA registers\n");
75 		return;
76 	}
77 
78 	/* Alloc 1 additional descriptor - needed for DMA bug fix */
79 	allocsz = sizeof(struct hpc_dma_desc) * (ndesc + 1);
80 	KASSERT(allocsz <= NBPG);
81 
82 	if (bus_dmamap_create(sc->sc_dmat, NBPG, 1 /*seg*/,
83 			      NBPG, 0, BUS_DMA_WAITOK,
84 			      &sc->sc_dmamap) != 0) {
85 		printf(": failed to create dmamap\n");
86 		return;
87 	}
88 
89 	/*
90 	 * Allocate a block of memory for dma chaining pointers
91 	 */
92 	if (bus_dmamem_alloc(sc->sc_dmat, allocsz, 0, 0,
93 			     &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
94 		printf(": can't allocate sglist\n");
95 		return;
96 	}
97 	/* Map pages into kernel memory */
98 	if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, allocsz,
99 			   (caddr_t *)&hdd, BUS_DMA_NOWAIT)) {
100 		printf(": can't map sglist\n");
101 		bus_dmamem_free(sc->sc_dmat, &seg, rseg);
102 		return;
103 	}
104 
105 	if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, hdd,
106 			    allocsz, NULL, BUS_DMA_NOWAIT)) {
107 		printf(": can't load sglist\n");
108 		return;
109 	}
110 
111 	sc->sc_desc_kva = hdd;
112 	sc->sc_desc_pa = (void *) sc->sc_dmamap->dm_segs[0].ds_addr;
113 }
114 
115 
116 void
117 hpcdma_sglist_create(struct hpc_dma_softc *sc, bus_dmamap_t dmamap)
118 {
119 	struct hpc_dma_desc *hva, *hpa;
120 	bus_dma_segment_t *segp;
121 	int i;
122 
123 	KASSERT(dmamap->dm_nsegs <= sc->sc_ndesc);
124 
125 	hva  = sc->sc_desc_kva;
126 	hpa  = sc->sc_desc_pa;
127 	segp = dmamap->dm_segs;
128 
129 #ifdef DMA_DEBUG
130 	printf("DMA_SGLIST<");
131 #endif
132 	for (i = dmamap->dm_nsegs; i; i--) {
133 #ifdef DMA_DEBUG
134 		printf("%p:%ld, ", (void *)segp->ds_addr, segp->ds_len);
135 #endif
136 		hva->hdd_bufptr = segp->ds_addr;
137 		hva->hdd_ctl    = segp->ds_len;
138 		hva->hdd_descptr = (u_int32_t) ++hpa;
139 		++hva; ++segp;
140 	}
141 	/* Work around HPC3 DMA bug */
142 	hva->hdd_bufptr  = 0;
143 	hva->hdd_ctl     = HDD_CTL_EOCHAIN;
144 	hva->hdd_descptr = 0;
145 	hva++;
146 #ifdef DMA_DEBUG
147 	printf(">\n");
148 #endif
149 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
150 	    0, sc->sc_dmamap->dm_mapsize,
151 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
152 
153 	/* Load DMA Descriptor list */
154 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_NDBP,
155 			    (u_int32_t)sc->sc_desc_pa);
156 }
157 
158 void
159 hpcdma_cntl(struct hpc_dma_softc *sc, uint32_t mode)
160 {
161 
162 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL, mode);
163 }
164 
165 void
166 hpcdma_reset(struct hpc_dma_softc *sc)
167 {
168 
169 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL,
170 	    HPC_DMACTL_RESET);
171 	delay(100);
172 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL, 0);
173 	delay(1000);
174 }
175 
176 void
177 hpcdma_flush(struct hpc_dma_softc *sc)
178 {
179 	u_int32_t	mode;
180 
181 	mode = bus_space_read_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL);
182 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL,
183 	    			mode | HPC_DMACTL_FLUSH);
184 
185 	/* Wait for Active bit to drop */
186 	while (bus_space_read_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL) &
187 	    HPC_DMACTL_ACTIVE) {
188 		bus_space_barrier(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL, 4,
189 		    BUS_SPACE_BARRIER_READ);
190 	}
191 }
192