xref: /netbsd/sys/arch/sgimips/include/intr.h (revision bf9ec67e)
1 /*	$NetBSD: intr.h,v 1.13 2002/05/03 01:51:38 rafal Exp $	*/
2 
3 /*
4  * Copyright (c) 2000 Soren S. Jorvang
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *          This product includes software developed for the
18  *          NetBSD Project.  See http://www.netbsd.org/ for
19  *          information about NetBSD.
20  * 4. The name of the author may not be used to endorse or promote products
21  *    derived from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #ifndef	_SGIMIPS_INTR_H_
36 #define	_SGIMIPS_INTR_H_
37 
38 #define	IPL_NONE	0	/* Disable only this interrupt. */
39 #define	IPL_BIO		1	/* Disable block I/O interrupts. */
40 #define	IPL_NET		2	/* Disable network interrupts. */
41 #define	IPL_TTY		3	/* Disable terminal interrupts. */
42 #define	IPL_CLOCK	4	/* Disable clock interrupts. */
43 #define	IPL_STATCLOCK	5	/* Disable profiling interrupts. */
44 #ifndef __NO_SOFT_SERIAL_INTERRUPT
45 #define	IPL_SERIAL	6	/* Disable serial hardware interrupts. */
46 #endif
47 #define	IPL_HIGH	7	/* Disable all interrupts. */
48 #define NIPL		8
49 
50 /* Interrupt sharing types. */
51 #define IST_NONE	0	/* none */
52 #define IST_PULSE	1	/* pulsed */
53 #define IST_EDGE	2	/* edge-triggered */
54 #define IST_LEVEL	3	/* level-triggered */
55 
56 /* Soft interrupt numbers */
57 #define	IPL_SOFTSERIAL	0	/* serial software interrupts */
58 #define	IPL_SOFTNET	1	/* network software interrupts */
59 #define	IPL_SOFTCLOCK	2	/* clock software interrupts */
60 #define	IPL_NSOFT	3
61 
62 #define	IPL_SOFTNAMES {							\
63 	"serial",							\
64 	"net",								\
65 	"clock",							\
66 }
67 
68 #ifdef _KERNEL
69 #ifndef _LOCORE
70 
71 #include <sys/queue.h>
72 #include <sys/types.h>
73 #include <sys/device.h>
74 #include <mips/cpuregs.h>
75 
76 /*
77  * software simulated interrupt
78  */
79 #define setsoft(x)	do {			\
80 	extern u_int ssir;			\
81 	int s;					\
82 						\
83 	s = splhigh();				\
84 	ssir |= 1 << (x);			\
85 	_setsoftintr(MIPS_SOFT_INT_MASK_1);	\
86 	splx(s);				\
87 } while (0)
88 
89 #define softintr_schedule(arg)						\
90 do {									\
91 	struct sgimips_intrhand *__ih = (arg);				\
92 	__ih->ih_pending = 1;						\
93 	setsoft(__ih->ih_intrhead->intr_ipl);				\
94 } while (0)
95 
96 extern struct sgimips_intrhand *softnet_intrhand;
97 
98 #define	setsoftnet()	softintr_schedule(softnet_intrhand)
99 
100 #define NINTR	32
101 
102 struct sgimips_intrhand {
103 	LIST_ENTRY(sgimips_intrhand)
104 		ih_q;
105 	int	(*ih_fun) __P((void *));
106 	void	 *ih_arg;
107 	struct	sgimips_intr *ih_intrhead;
108 	int	ih_pending;
109 };
110 
111 struct sgimips_intr {
112 	LIST_HEAD(,sgimips_intrhand)
113 		intr_q;
114 	struct	evcnt ih_evcnt;
115 	unsigned long intr_ipl;
116 };
117 
118 extern struct sgimips_intrhand intrtab[];
119 
120 extern int		_splraise(int);
121 extern int		_spllower(int);
122 extern int		_splset(int);
123 extern int		_splget(void);
124 extern void		_splnone(void);
125 extern void		_setsoftintr(int);
126 extern void		_clrsoftintr(int);
127 
128 extern u_int32_t 	biomask;
129 extern u_int32_t 	netmask;
130 extern u_int32_t 	ttymask;
131 extern u_int32_t 	clockmask;
132 
133 #define splhigh()	_splraise(MIPS_INT_MASK)
134 #define spl0()		(void)_spllower(0)
135 #define splx(s)		(void)_splset(s)
136 #define splbio()	_splraise(biomask)
137 #define splnet()	_splraise(netmask)
138 #define spltty()	_splraise(ttymask)
139 #define splvm()		spltty()
140 #define splclock()	_splraise(clockmask)
141 #define splstatclock()	splclock()
142 
143 #define	splsched()	splhigh()
144 #define	spllock()	splhigh()
145 #define splserial()	spltty()
146 #define spllpt()	spltty()
147 
148 #define splsoft()	_splraise(MIPS_SOFT_INT_MASK_1)
149 #define splsoftclock()	splsoft()
150 #define splsoftnet()	splsoft()
151 
152 #define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_1)
153 
154 extern void *		cpu_intr_establish(int, int, int (*)(void *), void *);
155 void *			softintr_establish(int, void (*)(void *), void *);
156 void			softintr_disestablish(void *);
157 void			softintr_init(void);
158 void			softintr_dispatch(void);
159 
160 #endif /* _LOCORE */
161 #endif /* !_KERNEL */
162 
163 #endif	/* !_SGIMIPS_INTR_H_ */
164