1 /* $NetBSD: oiocreg.h,v 1.1 2009/02/10 06:04:56 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Stephen M. Rumble 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef _ARCH_SGIMIPS_DEV_OIOCREG_H_ 28 #define _ARCH_SGIMIPS_DEV_OIOCREG_H_ 29 30 /* Registers below are relative to: */ 31 #define OIOC_BASE_ADDRESS 0x1f900000 32 33 /* 34 * The IOC SCSI DMA engine consists of 257 16-bit address registers, which can 35 * point to 256 4096-byte buffers. 36 * 37 * IOC_SCSI_DMA_LOW contains the first 12 bits of a starting offset within 38 * the first page of a virtually contiguous buffer. The MSB indicates DMA 39 * transfer direction. 40 * 41 * There are 256 high address registers starting at IOC_SCSI_DMA_HIGH_BASE 42 * and occurring every 4 bytes. This provides 28 address bits - more than 43 * sufficient for these old machines. 44 */ 45 #define OIOC_SCSI_REGS 0x00000000 /* SCSI registers offset */ 46 #define OIOC_SCSI_REGS_SIZE 0x00200102 /* SCSI length */ 47 48 #define OIOC_SCSI_DMA_LOW 0x00000002 /* 16-bit */ 49 #define OIOC_SCSI_DMA_HIGH_BASE 0x00020002 /* 16-bit */ 50 #define OIOC_SCSI_DMA_FLUSH 0x00040000 /* 32-bit; write 0 to flush */ 51 52 #define OIOC_SCSI_DMA_NSEGS 256 53 #define OIOC_SCSI_DMA_HIGH(_x) (OIOC_SCSI_DMA_HIGH_BASE + ((_x) << 2)) 54 #define OIOC_SCSI_DMA_HIGH_SHFT 12 55 #define OIOC_SCSI_DMA_LOW_ADDR_MASK 0x0fff 56 #define OIOC_SCSI_DMA_LOW_ADDR_DMADIR 0x8000 /* if set: SCSI->MEM */ 57 58 #define OIOC_SCSI_RESET_OFF 0x00180000 /* 32-bit; read to set _RESET */ 59 #define OIOC_SCSI_RESET_ON 0x00180004 /* 32-bit; read to clr _RESET */ 60 61 #define OIOC_WD33C93_ASR 0x00200001 /* 8-bit; scsi asr register */ 62 #define OIOC_WD33C93_ASR_SIZE 1 63 #define OIOC_WD33C93_DATA 0x00200101 /* 8-bit; scsi data register */ 64 #define OIOC_WD33C93_DATA_SIZE 1 65 66 /* 67 * IOC has 64 (I think) 16-bit page remap registers occurring every 4 bytes 68 * starting at 0xbf920802. Each register takes a physical page number, N, which 69 * maps physical memory page N into LANCE's 24-bit address space at offset 70 * (N * 4096). 71 */ 72 #define OIOC_ENET_PGMAP_BASE 0x00020802 /* 16-bit */ 73 #define OIOC_ENET_NPGMAPS 64 /* 64 pages */ 74 #define OIOC_ENET_PGMAP_SIZE (OIOC_ENET_NPGMAPS * 4) 75 #define OIOC_ENET_PGMAP_OFF(n) ((n) << 2) /* every 4 bytes */ 76 77 #define OIOC_ENET_RESET_OFF 0x00060000 /* 8-bit; read to set _RESET */ 78 #define OIOC_ENET_RESET_ON 0x00060004 /* 8-bit; read to clr _RESET */ 79 #define OIOC_LANCE_RDP 0x00050000 /* 16-bit; le reg. data port */ 80 #define OIOC_LANCE_RDP_SIZE 2 81 #define OIOC_LANCE_RAP 0x00050100 /* 16-bit; le reg. access port*/ 82 #define OIOC_LANCE_RAP_SIZE 2 83 84 #define OIOC2_CONFIG 0x00180008 /* 32-bit; IOC2 (IP6/10) only */ 85 86 /* OIOC2_CONFIG bits; only BURST, NOSYNC and HIWAT are writable. */ 87 #define OIOC2_CONFIG_HIWAT_MASK 0x0000000f 88 #define OIOC2_CONFIG_HIWAT_SHFT 0x00000000 89 #define OIOC2_CONFIG_ID_MASK 0x00000030 90 #define OIOC2_CONFIG_ID_SHFT 0x00000004 91 #define OIOC2_CONFIG_NOSYNC_MASK 0x00000040 92 #define OIOC2_CONFIG_NOSYNC_SHFT 0x00000006 93 #define OIOC2_CONFIG_BURST_MASK 0x00000080 94 #define OIOC2_CONFIG_BURST_SHFT 0x00000007 95 #define OIOC2_CONFIG_COUNT_MASK 0x00007f00 96 #define OIOC2_CONFIG_COUNT_SHFT 0x00000008 97 #define OIOC2_CONFIG_RSRVD_MASK 0x00008000 98 #define OIOC2_CONFIG_RSRVD_SHFT 0x0000000f 99 #define OIOC2_CONFIG_SCP_MASK 0x003f0000 100 #define OIOC2_CONFIG_SCP_SHFT 0x00000010 101 #define OIOC2_CONFIG_RSRVD2_MASK 0x0fc00000 102 #define OIOC2_CONFIG_RSRVD2_SHFT 0x00000016 103 #define OIOC2_CONFIG_IOP_MASK 0xf0000000 104 #define OIOC2_CONFIG_IOP_SHFT 0x0000001c 105 106 #endif /* _ARCH_SGIMIPS_DEV_OIOCREG_H_ */ 107