xref: /netbsd/sys/arch/sgimips/sgimips/cpu.c (revision bf9ec67e)
1 /*	$NetBSD: cpu.c,v 1.9 2002/03/13 13:12:29 simonb Exp $	*/
2 
3 /*
4  * Copyright (c) 2000 Soren S. Jorvang
5  * Copyright (c) 2001 Jason R. Thorpe.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *          This product includes software developed for the
19  *          NetBSD Project.  See http://www.netbsd.org/ for
20  *          information about NetBSD.
21  * 4. The name of the author may not be used to endorse or promote products
22  *    derived from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #include "opt_machtypes.h"
37 
38 #include <sys/param.h>
39 #include <sys/device.h>
40 #include <sys/systm.h>
41 
42 #include <mips/cache.h>
43 
44 #include <machine/cpu.h>
45 #include <machine/locore.h>
46 #include <machine/autoconf.h>
47 #include <machine/machtype.h>
48 
49 #include <dev/arcbios/arcbios.h>
50 #include <dev/arcbios/arcbiosvar.h>
51 
52 static int	cpu_match(struct device *, struct cfdata *, void *);
53 static void	cpu_attach(struct device *, struct device *, void *);
54 
55 struct cfattach cpu_ca = {
56 	sizeof(struct device), cpu_match, cpu_attach
57 };
58 
59 static void
60 sgimips_find_l2cache(struct arcbios_component *comp,
61     struct arcbios_treewalk_context *atc)
62 {
63 	struct device *self = atc->atc_cookie;
64 
65 	if (comp->Class != COMPONENT_CLASS_CacheClass)
66 		return;
67 
68 	switch (comp->Type) {
69 	case COMPONENT_TYPE_SecondaryICache:
70 		panic("%s: split L2 cache", self->dv_xname);
71 	case COMPONENT_TYPE_SecondaryDCache:
72 	case COMPONENT_TYPE_SecondaryCache:
73 		mips_sdcache_size = COMPONENT_KEY_Cache_CacheSize(comp->Key);
74 		mips_sdcache_line_size =
75 		    COMPONENT_KEY_Cache_LineSize(comp->Key);
76 		/* XXX */
77 		mips_sdcache_ways = 1;
78 		break;
79 	}
80 }
81 
82 static int
83 cpu_match(parent, match, aux)
84 	struct device *parent;
85 	struct cfdata *match;
86 	void *aux;
87 {
88 	return 1;
89 }
90 
91 static void
92 cpu_attach(parent, self, aux)
93 	struct device *parent;
94 	struct device *self;
95 	void *aux;
96 {
97 	/*
98 	 * Walk the ARCBIOS device tree to find the L2 cache.
99 	 *
100 	 * XXX We should be walking the tree to attach the CPUs,
101 	 * XXX etc, but we don't currently do that.
102 	 */
103 	arcbios_tree_walk(sgimips_find_l2cache, self);
104 
105 	printf(": ");
106 	cpu_identify();
107 
108 #ifdef IP22
109 	if (mach_type == MACH_SGI_IP22) {		/* XXX Indy */
110 		extern void ip22_cache_init(struct device *);
111 		ip22_cache_init(self);
112 	}
113 #endif
114 }
115