1/* $NetBSD: ip22_cache.S,v 1.5 2005/12/11 12:18:58 christos Exp $ */ 2 3/* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * Code to manipulate the L2 SysAD cache on R4600-based SGI IP22/24 systems. 40 */ 41 42#include <mips/asm.h> 43#include <mips/cpuregs.h> 44 45 .set noreorder 46 .set mips3 47 48#define PROLOGUE \ 49 mfc0 t0, MIPS_COP_0_STATUS ; \ 50 nop ; \ 51 nop ; \ 52 nop ; \ 53 li v0, ~MIPS_SR_INT_IE /* ints off */ ; \ 54 and t1, v0, t0 ; \ 55 or t1, MIPS3_SR_KX /* enable 64-bit */ ; \ 56 mtc0 t1, MIPS_COP_0_STATUS ; \ 57 nop ; \ 58 nop ; \ 59 nop ; \ 60 nop 61 62#define EPILOGUE \ 63 mtc0 t0, MIPS_COP_0_STATUS ; \ 64 nop ; \ 65 nop ; \ 66 nop ; \ 67 nop 68 69/* 70 * ip22_sdcache_do_wbinv: 71 * 72 * Write-back and invalidate the cache lines [a0..a1]. 73 */ 74LEAF_NOPROFILE(ip22_sdcache_do_wbinv) 75 PROLOGUE 76 77 /* 78 * Translate the cache indices into the magic cache 79 * flush space. 80 */ 81 dli v0, 0x9000000080000000 /* base of cache flush space */ 82 or a0, v0 /* first */ 83 or a1, v0 /* last */ 84 85 /* 86 * Flush the cache by performing a store into the 87 * magic cache flush space. 88 */ 891: sw zero, 0(a0) 90 bne a0, a1, 1b 91 daddu a0, 32 92 93 EPILOGUE 94 95 j ra 96 nop 97END(ip22_sdcache_do_wbinv) 98 99LEAF_NOPROFILE(ip22_sdcache_enable) 100 PROLOGUE 101 102 li a0, 0x1 103 dsll a0, 31 104 lui a1, 0x9000 105 dsll32 a1, 0 106 or a0, a1, a0 107 sb zero, 0(a0) 108 109 EPILOGUE 110 111 j ra 112 nop 113END(ip22_sdcache_enable) 114 115LEAF_NOPROFILE(ip22_sdcache_disable) 116 PROLOGUE 117 118 li a0, 0x1 119 dsll a0, 31 120 lui a1, 0x9000 121 dsll32 a1, 0 122 or a0, a1, a0 123 sh zero, 0(a0) 124 125 EPILOGUE 126 127 j ra 128 nop 129END(ip22_sdcache_disable) 130