1*95e1ffb1Schristos /* $NetBSD: adcreg.h,v 1.3 2005/12/11 12:18:58 christos Exp $ */ 281428320Suwe 381428320Suwe /* 481428320Suwe * Copyright (c) 2003 Valeriy E. Ushakov 581428320Suwe * All rights reserved. 681428320Suwe * 781428320Suwe * Redistribution and use in source and binary forms, with or without 881428320Suwe * modification, are permitted provided that the following conditions 981428320Suwe * are met: 1081428320Suwe * 1. Redistributions of source code must retain the above copyright 1181428320Suwe * notice, this list of conditions and the following disclaimer. 1281428320Suwe * 2. Redistributions in binary form must reproduce the above copyright 1381428320Suwe * notice, this list of conditions and the following disclaimer in the 1481428320Suwe * documentation and/or other materials provided with the distribution. 1581428320Suwe * 3. The name of the author may not be used to endorse or promote products 1681428320Suwe * derived from this software without specific prior written permission 1781428320Suwe * 1881428320Suwe * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1981428320Suwe * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2081428320Suwe * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2181428320Suwe * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2281428320Suwe * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2381428320Suwe * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2481428320Suwe * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2581428320Suwe * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2681428320Suwe * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2781428320Suwe * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2881428320Suwe */ 2981428320Suwe 3081428320Suwe #ifndef _SH3_ADCREG_H_ 3181428320Suwe #define _SH3_ADCREG_H_ 3281428320Suwe 3381428320Suwe #define SH7709_ADDRAH 0xa4000080 3481428320Suwe #define SH7709_ADDRAL 0xa4000082 3581428320Suwe #define SH7709_ADDRBH 0xa4000084 3681428320Suwe #define SH7709_ADDRBL 0xa4000086 3781428320Suwe #define SH7709_ADDRCH 0xa4000088 3881428320Suwe #define SH7709_ADDRCL 0xa400008a 3981428320Suwe #define SH7709_ADDRDH 0xa400008c 4081428320Suwe #define SH7709_ADDRDL 0xa400008e 4181428320Suwe 4281428320Suwe 4381428320Suwe #define SH7709_ADCSR 0xa4000090 4481428320Suwe 4581428320Suwe #define SH7709_ADCSR_ADF 0x80 /* end flag */ 4681428320Suwe #define SH7709_ADCSR_ADIE 0x40 /* interrupt enable */ 4781428320Suwe #define SH7709_ADCSR_ADST 0x20 /* start conversion */ 4881428320Suwe #define SH7709_ADCSR_MULTI 0x10 /* multi mode */ 4981428320Suwe #define SH7709_ADCSR_CKS 0x08 /* clock select */ 5081428320Suwe #define SH7709_ADCSR_CH_MASK 0x07 /* channel select mask */ 5181428320Suwe 5281428320Suwe #define SH7709_ADCSR_BITS \ 5381428320Suwe "\177\020" "b\07F\0" "b\06IE\0" "b\05ST\0" "b\04MULTI\0" \ 54390e87a8Suwe "f\03\01CKS\0" "f\0\03CH\0" 5581428320Suwe 5681428320Suwe 5781428320Suwe #define SH7709_ADCR 0xa4000092 5881428320Suwe 5981428320Suwe #define SH7709_ADCR_TRGE_MASK 0xc0 /* external trigger enabled when 11 */ 6081428320Suwe #define SH7709_ADCR_SCN 0x20 /* scan mode (if SH7709_ADCSR_MULTI) */ 6181428320Suwe 6281428320Suwe #define SH7709_ADCR_BITS \ 6381428320Suwe "\177\020" "F\06\02\0" ":\03TRGE\0" "b\05SCAN\0" 6481428320Suwe 6581428320Suwe #endif /* _SH3_ADCREG_H_ */ 66