1 /* $NetBSD: cache.h,v 1.4 2002/05/09 12:30:45 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cache configurations. 41 * 42 * SH3 I/D unified virtual-index physical-tag cache. 43 * SH4 I/D separated virtual-index physical-tag cache. 44 * 45 * 46 * size line-size entry way 47 * SH7708 4/8K 16B 128 2/4 P0, P2, U0 write-through/back selectable 48 * P1 write-through 49 * SH7709 4/8K 16B 128 2/4 write-through/back selectable 50 * SH7709A 16K 16B 256 4 write-through/back selectable 51 * 52 * SH7750 I$ D$ line-size entry way 53 * 8K 8/16K 32B 256 1 write-through/back selectable 54 * 55 * 56 * Cache operations. 57 * 58 * There are some rules that must be followed: 59 * 60 * I-cache Synch (all or range): 61 * The goal is to synchronize the instruction stream, 62 * so you may need to write-back dirty data cache 63 * blocks first. If a range is requested, and you 64 * can't synchronize just a range, you have to hit 65 * the whole thing. 66 * 67 * D-cache Write-back Invalidate range: 68 * If you can't WB-Inv a range, you must WB-Inv the 69 * entire D-cache. 70 * 71 * D-cache Invalidate: 72 * If you can't Inv the D-cache without doing a 73 * Write-back, YOU MUST PANIC. This is to catch 74 * errors in calling code. Callers must be aware 75 * of this scenario, and must handle it appropriately 76 * (consider the bus_dma(9) operations). 77 * 78 * D-cache Write-back: 79 * If you can't Write-back without doing an invalidate, 80 * that's fine. Then treat this as a WB-Inv. Skipping 81 * the invalidate is merely an optimization. 82 * 83 * All operations: 84 * Valid virtual addresses must be passed to the 85 * cache operation. 86 * 87 * 88 * sh_icache_sync_all Synchronize I-cache 89 * 90 * sh_icache_sync_range Synchronize I-cache range 91 * 92 * sh_icache_sync_range_index (index ops) 93 * 94 * sh_dcache_wbinv_all Write-back Invalidate D-cache 95 * 96 * sh_dcache_wbinv_range Write-back Invalidate D-cache range 97 * 98 * sh_dcache_wbinv_range_index (index ops) 99 * 100 * sh_dcache_inv_range Invalidate D-cache range 101 * 102 * sh_dcache_wb_range Write-back D-cache range 103 * 104 * If I/D unified cache (SH3), I-cache ops are writeback invalidate 105 * operation. 106 * If write-through mode, sh_dcache_wb_range is no-operation. 107 * 108 */ 109 110 #ifndef _SH3_CACHE_H_ 111 #define _SH3_CACHE_H_ 112 113 #ifdef _KERNEL 114 struct sh_cache_ops { 115 void (*_icache_sync_all)(void); 116 void (*_icache_sync_range)(vaddr_t, vsize_t); 117 void (*_icache_sync_range_index)(vaddr_t, vsize_t); 118 119 void (*_dcache_wbinv_all)(void); 120 void (*_dcache_wbinv_range)(vaddr_t, vsize_t); 121 void (*_dcache_wbinv_range_index)(vaddr_t, vsize_t); 122 void (*_dcache_inv_range)(vaddr_t, vsize_t); 123 void (*_dcache_wb_range)(vaddr_t, vsize_t); 124 }; 125 126 /* Cache configurations */ 127 #define sh_cache_enable_unified sh_cache_enable_icache 128 extern int sh_cache_enable_icache; 129 extern int sh_cache_enable_dcache; 130 extern int sh_cache_write_through; 131 extern int sh_cache_write_through_p0_u0_p3; 132 extern int sh_cache_write_through_p1; 133 extern int sh_cache_ways; 134 extern int sh_cache_unified; 135 #define sh_cache_size_unified sh_cache_size_icache 136 extern int sh_cache_size_icache; 137 extern int sh_cache_size_dcache; 138 extern int sh_cache_line_size; 139 /* for n-way set associative cache */ 140 extern int sh_cache_way_size; 141 extern int sh_cache_way_shift; 142 extern int sh_cache_entry_mask; 143 144 /* Special mode */ 145 extern int sh_cache_ram_mode; 146 extern int sh_cache_index_mode_icache; 147 extern int sh_cache_index_mode_dcache; 148 149 extern struct sh_cache_ops sh_cache_ops; 150 151 #define sh_icache_sync_all() \ 152 (*sh_cache_ops._icache_sync_all)() 153 154 #define sh_icache_sync_range(v, s) \ 155 (*sh_cache_ops._icache_sync_range)((v), (s)) 156 157 #define sh_icache_sync_range_index(v, s) \ 158 (*sh_cache_ops._icache_sync_range_index)((v), (s)) 159 160 #define sh_dcache_wbinv_all() \ 161 (*sh_cache_ops._dcache_wbinv_all)() 162 163 #define sh_dcache_wbinv_range(v, s) \ 164 (*sh_cache_ops._dcache_wbinv_range)((v), (s)) 165 166 #define sh_dcache_wbinv_range_index(v, s) \ 167 (*sh_cache_ops._dcache_wbinv_range_index)((v), (s)) 168 169 #define sh_dcache_inv_range(v, s) \ 170 (*sh_cache_ops._dcache_inv_range)((v), (s)) 171 172 #define sh_dcache_wb_range(v, s) \ 173 (*sh_cache_ops._dcache_wb_range)((v), (s)) 174 175 void sh_cache_init(void); 176 void sh_cache_information(void); 177 178 #if defined(SH3) && defined(SH4) 179 #define SH_HAS_VIRTUAL_ALIAS CPU_IS_SH4 180 #define SH_HAS_UNIFIED_CACHE CPU_IS_SH3 181 #define SH_HAS_WRITEBACK_CACHE (!sh_cache_write_through) 182 #elif defined(SH3) 183 #define SH_HAS_VIRTUAL_ALIAS 0 184 #define SH_HAS_UNIFIED_CACHE 1 185 #define SH_HAS_WRITEBACK_CACHE (!sh_cache_write_through) 186 #elif defined(SH4) 187 #define SH_HAS_VIRTUAL_ALIAS 1 188 #define SH_HAS_UNIFIED_CACHE 0 189 #define SH_HAS_WRITEBACK_CACHE (!sh_cache_write_through) 190 #endif 191 192 #endif /* _KERNEL */ 193 #endif /* _SH3_CACHE_H_ */ 194