1 /* $NetBSD: cache_sh4.h,v 1.5 2002/04/28 17:10:33 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * SH4: SH7750 SH7750S 41 */ 42 43 #ifndef _SH3_CACHE_SH4_H_ 44 #define _SH3_CACHE_SH4_H_ 45 #include <sh3/devreg.h> 46 #ifdef _KERNEL 47 48 #define SH4_ICACHE_SIZE 8192 49 #define SH4_DCACHE_SIZE 16384 50 #define SH4_CACHE_LINESZ 32 51 52 #define SH4_CCR 0xff00001c 53 #define SH4_CCR_IIX 0x00008000 54 #define SH4_CCR_ICI 0x00000800 55 #define SH4_CCR_ICE 0x00000100 56 #define SH4_CCR_OIX 0x00000080 57 #define SH4_CCR_ORA 0x00000020 58 #define SH4_CCR_OCI 0x00000008 59 #define SH4_CCR_CB 0x00000004 60 #define SH4_CCR_WT 0x00000002 61 #define SH4_CCR_OCE 0x00000001 62 63 #define SH4_QACR0 0xff000038 64 #define SH4_QACR1 0xff00003c 65 #define SH4_QACR_AREA_SHIFT 2 66 #define SH4_QACR_AREA_MASK 0x0000001c 67 68 /* I-cache address/data array */ 69 #define SH4_CCIA 0xf0000000 70 /* address specification */ 71 #define CCIA_A 0x00000008 /* associate bit */ 72 #define CCIA_ENTRY_SHIFT 5 /* line size 32B */ 73 #define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 74 /* data specification */ 75 #define CCIA_V 0x00000001 76 #define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 77 78 #define SH4_CCID 0xf1000000 79 /* address specification */ 80 #define CCID_L_SHIFT 2 81 #define CCID_L_MASK 0x1c /* line-size is 32B */ 82 #define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 128-entries */ 83 84 /* D-cache address/data array */ 85 #define SH4_CCDA 0xf4000000 86 /* address specification */ 87 #define CCDA_A 0x00000008 /* associate bit */ 88 #define CCDA_ENTRY_SHIFT 5 /* line size 32B */ 89 #define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ 90 /* data specification */ 91 #define CCDA_V 0x00000001 92 #define CCDA_U 0x00000002 93 #define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 94 95 #define SH4_CCDD 0xf5000000 96 97 /* Store Queue */ 98 #define SH4_SQ 0xe0000000 99 100 /* 101 * cache flush macro for locore level code. 102 */ 103 #define SH4_CACHE_FLUSH() \ 104 do { \ 105 u_int32_t __e, __a; \ 106 \ 107 /* D-cache */ \ 108 for (__e = 0; __e < (SH4_DCACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\ 109 __a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \ 110 (*(__volatile__ u_int32_t *)__a) &= ~(CCDA_U | CCDA_V); \ 111 } \ 112 /* I-cache */ \ 113 for (__e = 0; __e < (SH4_ICACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\ 114 __a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \ 115 (*(__volatile__ u_int32_t *)__a) &= ~(CCIA_V); \ 116 } \ 117 } while(/*CONSTCOND*/0) 118 119 #define SH7750_CACHE_FLUSH() SH4_CACHE_FLUSH() 120 #define SH7750S_CACHE_FLUSH() SH4_CACHE_FLUSH() 121 122 #ifndef _LOCORE 123 extern void sh4_cache_config(void); 124 #endif 125 #endif /* _KERNEL */ 126 #endif /* !_SH3_CACHE_SH4_H_ */ 127