1 /* $NetBSD: scifreg.h,v 1.4 2002/05/19 15:10:46 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _SH3_SCIFREG_H_ 30 #define _SH3_SCIFREG_H_ 31 32 /* 33 * Serial Communication Interface (SCIF) 34 */ 35 36 #if !defined(SH4) 37 38 /* SH3 definitions */ 39 40 #define SHREG_SCSMR2 (*(volatile unsigned char *) 0xa4000150) 41 #define SHREG_SCBRR2 (*(volatile unsigned char *) 0xa4000152) 42 #define SHREG_SCSCR2 (*(volatile unsigned char *) 0xa4000154) 43 #define SHREG_SCFTDR2 (*(volatile unsigned char *) 0xa4000156) 44 #define SHREG_SCSSR2 (*(volatile unsigned short *) 0xa4000158) 45 #define SHREG_SCFRDR2 (*(volatile unsigned char *) 0xa400015A) 46 #define SHREG_SCFCR2 (*(volatile unsigned char *) 0xa400015C) 47 #define SHREG_SCFDR2 (*(volatile unsigned short *) 0xa400015E) 48 49 #define SCSCR2_TIE 0x80 /* Transmit Interrupt Enable */ 50 #define SCSCR2_RIE 0x40 /* Recieve Interrupt Enable */ 51 #define SCSCR2_TE 0x20 /* Transmit Enable */ 52 #define SCSCR2_RE 0x10 /* Receive Enable */ 53 #define SCSCR2_CKE1 0x02 /* ClocK Enable 1 */ 54 #define SCSCR2_CKE0 0x01 /* ClocK Enable 0 */ 55 56 #define SCSSR2_ER 0x0080 /* ERror */ 57 #define SCSSR2_TEND 0x0040 /* Transmit END */ 58 #define SCSSR2_TDFE 0x0020 /* Transmit Data Fifo Empty */ 59 #define SCSSR2_BRK 0x0010 /* BReaK detection */ 60 #define SCSSR2_FER 0x0008 /* Framing ERror */ 61 #define SCSSR2_PER 0x0004 /* Parity ERror */ 62 #define SCSSR2_RDF 0x0002 /* Recieve fifo Data Full */ 63 #define SCSSR2_DR 0x0001 /* Data Ready */ 64 65 #define SCFCR2_RTRG1 0x80 /* Receive TRiGger 1 */ 66 #define SCFCR2_RTRG0 0x40 /* Receive TRiGger 0 */ 67 #define SCFCR2_TTRG1 0x20 /* Transmit TRiGger 1 */ 68 #define SCFCR2_TTRG0 0x10 /* Transmit TRiGger 0 */ 69 #define SCFCR2_MCE 0x08 /* Modem Control Enable */ 70 #define SCFCR2_TFRST 0x04 /* Transmit Fifo register ReSeT */ 71 #define SCFCR2_RFRST 0x02 /* Receive Fifo register ReSeT */ 72 #define SCFCR2_LOOP 0x01 /* LOOP back test */ 73 #define FIFO_RCV_TRIGGER_1 0x00 74 #define FIFO_RCV_TRIGGER_4 0x40 75 #define FIFO_RCV_TRIGGER_8 0x80 76 #define FIFO_RCV_TRIGGER_14 0xc0 77 #define FIFO_XMT_TRIGGER_8 0x00 78 #define FIFO_XMT_TRIGGER_4 0x10 79 #define FIFO_XMT_TRIGGER_2 0x20 80 #define FIFO_XMT_TRIGGER_1 0x30 81 82 #else 83 84 /* SH4 definitions */ 85 86 #define SHREG_SCSMR2 (*(volatile unsigned short *) 0xffe80000) 87 #define SHREG_SCBRR2 (*(volatile unsigned char *) 0xffe80004) 88 #define SHREG_SCSCR2 (*(volatile unsigned short *) 0xffe80008) 89 #define SHREG_SCFTDR2 (*(volatile unsigned char *) 0xffe8000c) 90 #define SHREG_SCFSR2 (*(volatile unsigned short *) 0xffe80010) 91 #define SHREG_SCFRDR2 (*(volatile unsigned char *) 0xffe80014) 92 #define SHREG_SCFCR2 (*(volatile unsigned short *) 0xffe80018) 93 #define SHREG_SCFDR2 (*(volatile unsigned short *) 0xffe8001c) 94 #define SHREG_SCSPTR2 (*(volatile unsigned short *) 0xffe80020) 95 #define SHREG_SCLSR2 (*(volatile unsigned short *) 0xffe80024) 96 97 /* alias */ 98 #define SHREG_SCSFDR2 SHREG_SCFTDR2 99 #define SHREG_SCSSR2 SHREG_SCFSR2 100 101 #define SCSCR2_TIE 0x0080 /* Transmit Interrupt Enable */ 102 #define SCSCR2_RIE 0x0040 /* Recieve Interrupt Enable */ 103 #define SCSCR2_TE 0x0020 /* Transmit Enable */ 104 #define SCSCR2_RE 0x0010 /* Receive Enable */ 105 #define SCSCR2_CKE1 0x0002 /* ClocK Enable 1 */ 106 107 #define SCSSR2_ER 0x0080 /* ERror */ 108 #define SCSSR2_TEND 0x0040 /* Transmit END */ 109 #define SCSSR2_TDFE 0x0020 /* Transmit Data Fifo Empty */ 110 #define SCSSR2_BRK 0x0010 /* BReaK detection */ 111 #define SCSSR2_FER 0x0008 /* Framing ERror */ 112 #define SCSSR2_PER 0x0004 /* Parity ERror */ 113 #define SCSSR2_RDF 0x0002 /* Recieve fifo Data Full */ 114 #define SCSSR2_DR 0x0001 /* Data Ready */ 115 116 #define SCFCR2_RTRG1 0x0080 /* Receive TRiGger 1 */ 117 #define SCFCR2_RTRG0 0x0040 /* Receive TRiGger 0 */ 118 #define SCFCR2_TTRG1 0x0020 /* Transmit TRiGger 1 */ 119 #define SCFCR2_TTRG0 0x0010 /* Transmit TRiGger 0 */ 120 #define SCFCR2_MCE 0x0008 /* Modem Control Enable */ 121 #define SCFCR2_TFRST 0x0004 /* Transmit Fifo register ReSeT */ 122 #define SCFCR2_RFRST 0x0002 /* Receive Fifo register ReSeT */ 123 #define SCFCR2_LOOP 0x0001 /* LOOP back test */ 124 #define FIFO_RCV_TRIGGER_1 0x0000 125 #define FIFO_RCV_TRIGGER_4 0x0040 126 #define FIFO_RCV_TRIGGER_8 0x0080 127 #define FIFO_RCV_TRIGGER_14 0x00c0 128 #define FIFO_XMT_TRIGGER_8 0x0000 129 #define FIFO_XMT_TRIGGER_4 0x0010 130 #define FIFO_XMT_TRIGGER_2 0x0020 131 #define FIFO_XMT_TRIGGER_1 0x0030 132 133 #define SCLSR2_ORER 0x0001 /* overrun error */ 134 135 #endif 136 137 /* common definitions */ 138 139 #define SCFDR2_TXCNT 0xff00 /* Tx CouNT */ 140 #define SCFDR2_RECVCNT 0x00ff /* Rx CouNT */ 141 #define SCFDR2_TXF_FULL 0x1000 /* Tx FULL */ 142 #define SCFDR2_RXF_EPTY 0x0000 /* Rx EMPTY */ 143 144 #endif /* !_SH3_SCIFREG_ */ 145