1/* $NetBSD: exception_vector.S,v 1.9 2002/05/09 12:24:21 uch Exp $ */ 2 3/*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the NetBSD 18 * Foundation, Inc. and its contributors. 19 * 4. Neither the name of The NetBSD Foundation nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36#include "opt_cputype.h" 37#include "opt_ddb.h" 38#include "assym.h" 39 40#include <sh3/param.h> 41#include <sh3/asm.h> 42#include <sh3/locore.h> 43#include <sh3/exception.h> 44#include <sh3/ubcreg.h> 45#include <sh3/mmu_sh3.h> 46#include <sh3/mmu_sh4.h> 47 48/* 49 * Exception vectors. following routines are copied to vector addreses. 50 * sh_vector_generic: VBR + 0x100 51 * sh_vector_tlbmiss: VBR + 0x400 52 * sh_vector_interrupt: VBR + 0x600 53 */ 54 55/* 56 * void sh_vector_generic(void) __attribute__((__noreturn__)): 57 * copied to VBR+0x100. This code should be relocatable and max 384 58 * instructions. 59 */ 60 .globl _C_LABEL(sh_vector_generic), _C_LABEL(sh_vector_generic_end) 61 .text 62 .align 2 63_C_LABEL(sh_vector_generic): 64 __EXCEPTION_ENTRY 65 __INTR_MASK(r0, r1) 66 /* Identify exception cause */ 67 MOV (EXPEVT, r0) 68 mov.l @r0, r0 69 mov.l r0, @(TF_EXPEVT, r14) /* trapframe->tf_expevt = EXPEVT */ 70 /* Get curproc */ 71 mov.l 3f, r1 72 mov.l @r1, r4 /* 1st arg */ 73 /* Check TLB exception or not */ 74 mov.l _L.TLB_PROT_ST, r1 75 cmp/hi r1, r0 76 bt 1f 77 MOV (TEA, r0) 78 mov.l @r0, r6 /* 3rd arg */ 79 mov.l _L.VPN_MASK, r1 80 and r1, r6 /* va = trunc_page(va) */ 81 __EXCEPTION_UNBLOCK(r0, r1) 82 mov.l _L.tlb, r0 83 jsr @r0 84 mov r14, r5 /* 2nd arg */ 85 bra 2f 86 nop 871: mov r4, r8 88#ifdef DDB 89 mov #0, r2 90 MOV (BBRA, r1) 91 mov.w r2, @r1 /* disable UBC */ 92 mov.l r2, @(TF_UBC, r14) /* clear trapframe->tf_ubc */ 93#endif /* DDB */ 94 __EXCEPTION_UNBLOCK(r0, r1) 95 mov.l _L.general, r0 96 jsr @r0 97 mov r14, r5 98 99 /* Check for ASTs on exit to user mode. */ 100 mov r8, r4 101 mov.l _L.ast, r0 102 jsr @r0 103 mov r14, r5 104#ifdef DDB /* BBRA = trapframe->tf_ubc */ 105 __EXCEPTION_BLOCK(r0, r1) 106 mov.l @(TF_UBC, r14), r0 107 MOV (BBRA, r1) 108 mov.w r0, @r1 109#endif /* DDB */ 1102: __EXCEPTION_RETURN 111 /* NOTREACHED */ 112 .align 2 1133: .long _C_LABEL(curproc) 114REG_SYMBOL(EXPEVT) 115REG_SYMBOL(BBRA) 116REG_SYMBOL(TEA) 117_L.tlb: .long _C_LABEL(tlb_exception) 118_L.general: .long _C_LABEL(general_exception) 119_L.ast: .long _C_LABEL(ast) 120_L.TLB_PROT_ST: .long 0xc0 121_L.VPN_MASK: .long 0xfffff000 122_C_LABEL(sh_vector_generic_end): .long 0 123 124#ifdef SH3 125/* 126 * void sh3_vector_tlbmiss(void) __attribute__((__noreturn__)): 127 * copied to VBR+0x400. This code should be relocatable and max 256 128 * instructions. 129 */ 130 .globl _C_LABEL(sh3_vector_tlbmiss), _C_LABEL(sh3_vector_tlbmiss_end) 131 .text 132 .align 2 133_C_LABEL(sh3_vector_tlbmiss): 134 __EXCEPTION_ENTRY 135 mov.l _L.TEA3, r0 136 mov.l @r0, r6 137 mov.l __L.VPN_MASK, r1 138 and r1, r6 /* 3rd arg */ 139#if !defined(P1_STACK) 140 /* Load kernel stack */ 141 tst r6, r6 /* check VPN == 0 */ 142 bt 6f 143 mov.l _L.CURUPTE, r1 144 mov.l @r1, r1 145 mov #UPAGES,r3 146 mov #1, r2 1474: mov.l @r1+, r7 148 cmp/eq r7, r6 /* md_upte.addr: u-area VPN */ 149 bt 5f 150 add #4, r1 /* skip md_upte.data */ 151 cmp/eq r2, r3 152 bf/s 4b 153 add #1, r2 154 bra 6f 155 nop 1565: mov.l @r1, r2 /* md_upte.data: u-area PTE */ 157 mov.l _L.PTEL, r1 158 mov.l r2, @r1 159 mov.l _L.PTEH, r1 160 mov.l @r1, r2 161 mov.l __L.VPN_MASK, r0 162 and r2, r0 163 mov.l r0, @r1 /* ASID 0 */ 164 ldtlb 165 mov.l r2, @r1 /* restore ASID */ 166 bra 3f 167 nop 168#endif /* !P1_STACK */ 1696: mov.l _L.EXPEVT3, r0 170 mov.l @r0, r0 171 mov.l r0, @(TF_EXPEVT, r14) /* trapframe->tf_expevt = EXPEVT */ 172 mov.l 2f, r0 173 mov.l @r0, r4 /* 1st arg */ 174 __INTR_MASK(r0, r1) 175 __EXCEPTION_UNBLOCK(r0, r1) 176 mov.l 1f, r0 177 jsr @r0 178 mov r14, r5 /* 2nd arg */ 1793: __EXCEPTION_RETURN 180 .align 2 1812: .long _C_LABEL(curproc) 1821: .long _C_LABEL(tlb_exception) 183_L.EXPEVT3: .long SH3_EXPEVT 184_L.TEA3: .long SH3_TEA 185_L.PTEL: .long SH3_PTEL 186_L.PTEH: .long SH3_PTEH 187__L.VPN_MASK: .long 0xfffff000 188_L.CURUPTE: .long _C_LABEL(curupte) 189 .align 2 190_C_LABEL(sh3_vector_tlbmiss_end): .long 0 191#endif /* SH3 */ 192 193#ifdef SH4 194/* 195 * void sh4_vector_tlbmiss(void) __attribute__((__noreturn__)): 196 * copied to VBR+0x400. This code should be relocatable and max 256 197 * instructions. 198 */ 199 .globl _C_LABEL(sh4_vector_tlbmiss), _C_LABEL(sh4_vector_tlbmiss_end) 200 .text 201 .align 2 202_C_LABEL(sh4_vector_tlbmiss): 203 __EXCEPTION_ENTRY 204 mov.l _L.TEA4, r0 205 mov.l @r0, r6 206 mov.l ___L.VPN_MASK, r1 207 and r1, r6 /* va = trunc_page(va) */ 208 mov.l _L.EXPEVT4, r0 209 mov.l @r0, r0 210 mov.l r0, @(TF_EXPEVT, r14) /* trapframe->tf_expevt = EXPEVT */ 211 mov.l 2f, r0 212 mov.l @r0, r4 /* 1st arg */ 213 __INTR_MASK(r0, r1) 214 __EXCEPTION_UNBLOCK(r0, r1) 215 mov.l 1f, r0 216 jsr @r0 217 mov r14, r5 /* 2nd arg */ 218 __EXCEPTION_RETURN 219 .align 2 2201: .long _C_LABEL(tlb_exception) 2212: .long _C_LABEL(curproc) 222_L.EXPEVT4: .long SH4_EXPEVT 223_L.TEA4: .long SH4_TEA 224___L.VPN_MASK: .long 0xfffff000 225_C_LABEL(sh4_vector_tlbmiss_end): .long 0 226#endif /* SH4 */ 227 228/* 229 * void sh_vector_interrupt(void) __attribute__((__noreturn__)): 230 * copied to VBR+0x600. This code should be relocatable. 231 */ 232 .globl _C_LABEL(sh_vector_interrupt), _C_LABEL(sh_vector_interrupt_end) 233 .align 2 234 .text 235_C_LABEL(sh_vector_interrupt): 236 __EXCEPTION_ENTRY 237 xor r0, r0 238 mov.l r0, @(TF_EXPEVT, r14) /* (for debug) */ 239 stc r0_bank,r6 /* ssp */ 240 /* Enable exception for P3 access */ 241 __INTR_MASK(r0, r1) 242 __EXCEPTION_UNBLOCK(r0, r1) 243 /* uvmexp.intrs++ */ 244 mov.l __L.uvmexp.intrs, r0 245 mov.l @r0, r1 246 add #1 r1 247 mov.l r1, @r0 248 /* Dispatch interrupt handler */ 249 mov.l __L.intc_intr, r0 250 jsr @r0 /* intc_intr(ssr, spc, ssp) */ 251 nop 252 /* Check for ASTs on exit to user mode. */ 253 mov.l 1f, r0 254 mov.l @r0, r4 /* 1st arg */ 255 mov.l __L.ast, r0 256 jsr @r0 257 mov r14, r5 /* 2nd arg */ 258 __EXCEPTION_RETURN 259 .align 2 2601: .long _C_LABEL(curproc) 261__L.intc_intr: .long _C_LABEL(intc_intr) 262__L.ast: .long _C_LABEL(ast) 263__L.uvmexp.intrs: .long _C_LABEL(uvmexp) + UVMEXP_INTRS 264_C_LABEL(sh_vector_interrupt_end): .long 0 265