xref: /netbsd/sys/arch/shark/include/intr.h (revision bf9ec67e)
1 /*	$NetBSD: intr.h,v 1.1 2002/02/10 01:57:21 thorpej Exp $	*/
2 
3 /*
4  * Copyright (c) 1997 Mark Brinicombe.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *	This product includes software developed by Mark Brinicombe
18  *	for the NetBSD Project.
19  * 4. The name of the company nor the name of the author may be used to
20  *    endorse or promote products derived from this software without specific
21  *    prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  */
35 
36 #ifndef _ARM32_INTR_H_
37 #define _ARM32_INTR_H_
38 
39 /* Define the various Interrupt Priority Levels */
40 
41 /* Hardware Interrupt Priority Levels are not mutually exclusive. */
42 
43 #define IPL_BIO		0	/* block I/O */
44 #define IPL_NET		1	/* network */
45 #define IPL_TTY		2	/* terminal */
46 #define IPL_IMP		3	/* memory allocation */
47 #define IPL_AUDIO	4	/* audio */
48 #define IPL_CLOCK	5	/* clock */
49 #define IPL_HIGH	6	/*  */
50 #define IPL_SERIAL	7	/* serial */
51 #define IPL_NONE	8
52 
53 #define IPL_LEVELS	8
54 
55 #define	IST_UNUSABLE	-1	/* interrupt cannot be used */
56 #define	IST_NONE	0	/* none (dummy) */
57 #define	IST_PULSE	1	/* pulsed */
58 #define	IST_EDGE	2	/* edge-triggered */
59 #define	IST_LEVEL	3	/* level-triggered */
60 
61 /* Software interrupt priority levels */
62 
63 #define SOFTIRQ_CLOCK	0
64 #define SOFTIRQ_NET	1
65 #define SOFTIRQ_SERIAL	2
66 
67 #define SOFTIRQ_BIT(x)	(1 << x)
68 
69 #include <machine/irqhandler.h>
70 #include <arm/arm32/psl.h>
71 
72 #endif	/* _ARM32_INTR_H */
73