1 /* $NetBSD: icu.h,v 1.3 2005/12/11 12:19:02 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)icu.h 5.6 (Berkeley) 5/9/91 35 */ 36 37 /* 38 * AT/386 Interrupt Control constants 39 * W. Jolitz 8/89 40 */ 41 42 #ifndef _ARM32_ISA_ICU_H_ 43 #define _ARM32_ISA_ICU_H_ 44 45 #ifndef _LOCORE 46 47 /* 48 * Interrupt "level" mechanism variables, masks, and macros 49 */ 50 extern unsigned imen; /* interrupt mask enable */ 51 52 #define SET_ICUS() { \ 53 outb(IO_ICU1 + 1, imen); \ 54 outb(IO_ICU2 + 1, imen >> 8); \ 55 } 56 57 #endif /* !_LOCORE */ 58 59 /* 60 * Interrupt enable bits -- in order of priority 61 */ 62 #define IRQ_SLAVE 2 63 64 /* 65 * Interrupt Control offset into Interrupt descriptor table (IDT) 66 */ 67 #define ICU_OFFSET 32 /* 0-31 are processor exceptions */ 68 #define ICU_LEN 16 /* 32-47 are ISA interrupts */ 69 70 #endif /* !_ARM32_ISA_ICU_H_ */ 71