1 /* $NetBSD: scr.c,v 1.25 2009/11/27 03:23:13 rmind Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 **++ 38 ** 39 ** FACILITY: 40 ** 41 ** Driver for smart card 42 ** 43 ** ABSTRACT: 44 ** 45 ** The driver provides access to a Smart Card for the DNARD. 46 ** 47 ** There is no Smart Card silicon. Several i/o pins 48 ** connect to the pads on the Smart Card, and the driver is 49 ** is responsible for driving the signals in accordance with 50 ** ISO 7816-3 (the Smart Card spec) 51 ** 52 ** This driver puts a high load on the system due to the need 53 ** to interrupt at a high rate (up to 50 kHz) during bit detection. 54 ** 55 ** 56 ** The driver is dived into the standard top half ioctl, and bottom 57 ** half interrupt. The interrupt is FIQ, which requires its own stack. 58 ** disable_interrupts and restore_interrupts must be used to protect from 59 ** a FIQ. Since splxxx functions do not use this, the bottom half cannot 60 ** use any standard functions (ie like wakeup, timeout, etc. 61 ** Thus the communication from the bottom half 62 ** to the top half uses a "done" bit called masterDone. This bit 63 ** is set by the master state machine when all bottom half work is 64 ** complete. The top half checks/sleeps on this masterDone bit. 65 ** 66 ** The FIQ is driven by Timer 2 (T2)in the sequoia. All times are 67 ** referenced to T2 counts. 68 ** 69 ** The bottom half is done as a several linked state machines. 70 ** The top level machine is the maserSM (ie master State Machine). This 71 ** machine calls mid level protocol machines, ie ATRSM (Answer To Reset 72 ** State Machine), t0SendSM (T=0 Send State Machine), and t0RecvSM (T=0 Recv 73 ** State Machine). These mid level protocol machines in turn call low level 74 ** bit-bashing machines, ie coldResetSM, t0SendByteSM, T0RecvByteSM. 75 ** 76 ** Smart Cards are driven in a command/response mode. Ie you issue a command 77 ** to the Smart Card and it responds. This command/response mode is reflected 78 ** in the structure of the driver. Ie the ioctl gets a command, it 79 ** gives it to the bottom half to execute and goes to sleep. The bottom half 80 ** executes the command and gets the response to from the card and then 81 ** notifies the top half that it has completed. Commands usually complete 82 ** in under a second. 83 ** 84 ** 85 ** 86 ** AUTHORS: 87 ** 88 ** E. J. Grohn 89 ** Digital Equipment Corporation. 90 ** 91 ** CREATION DATE: 92 ** 93 ** 27-July-97 94 ** 95 **-- 96 */ 97 98 /* 99 ** 100 ** INCLUDE FILES 101 ** 102 */ 103 104 #include <sys/cdefs.h> 105 __KERNEL_RCSID(0, "$NetBSD: scr.c,v 1.25 2009/11/27 03:23:13 rmind Exp $"); 106 107 #include "opt_ddb.h" 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/ioctl.h> 112 /* #include <sys/select.h> */ 113 /* #include <sys/tty.h> */ 114 #include <sys/proc.h> 115 #include <sys/conf.h> 116 /* #include <sys/file.h> */ 117 /* #include <sys/uio.h> */ 118 #include <sys/kernel.h> 119 /* #include <sys/syslog.h> */ 120 #include <sys/types.h> 121 #include <sys/device.h> 122 #include <dev/isa/isavar.h> 123 #include <arm/cpufunc.h> 124 125 126 /* SCR_DEBUG is the master switch for turning on debugging */ 127 //#define SCR_DEBUG 1 128 #ifdef SCR_DEBUG 129 #define KERNEL_DEBUG 130 #ifdef DDB 131 #define DEBUGGER printf("file = %s, line = %d\n",__FILE__,__LINE__);Debugger() 132 #else 133 #define DEBUGGER panic("file = %s, line = %d",__FILE__,__LINE__); 134 #endif 135 #else 136 #define DEBUGGER 137 #endif 138 139 140 #include <machine/kerndebug.h> 141 //#include <machine/intr.h> 142 #include <dev/ic/i8253reg.h> 143 #include <shark/shark/hat.h> 144 #include <shark/shark/sequoia.h> 145 #include <machine/scrio.h> 146 147 148 149 150 /* 151 ** 152 ** MACRO DEFINITIONS 153 ** 154 */ 155 156 157 #define scr_lcr scr_cfcr 158 159 /* 160 ** Macro to extract the minor device number from the device Identifier 161 */ 162 #define SCRUNIT(x) (minor(x)) 163 164 /* 165 ** some macros to assist in debugging 166 */ 167 #ifdef SCR_DEBUG 168 #define KERNEL_DEBUG 169 #define ASSERT(f) do { if (!(f)) { DEBUGGER;} }while(0) 170 #define TOGGLE_TEST_PIN() scrToggleTestPin() 171 #define INVALID_STATE_CMD(sc,state,cmd) invalidStateCmd(sc,state,cmd,__LINE__); 172 #else 173 #define ASSERT(f) 174 #define TOGGLE_TEST_PIN() 175 //#define INVALID_STATE_CMD(sc,state,cmd) panic("scr: invalid state/cmd, sc = %X, state = %X, cmd = %X, line = %d",sc,state,cmd,__LINE__); 176 #define INVALID_STATE_CMD(sc,state,cmd) sc->bigTrouble = true; 177 178 #endif 179 180 181 /* 182 ** The first and last bytes of the debug control variables is reserved for 183 ** the standard KERN_DEBUG_xxx macros, so we can tailor the middle two bytes 184 */ 185 #define SCRPROBE_DEBUG_INFO 0x00000100 186 #define SCRATTACH_DEBUG_INFO 0x00000200 187 #define SCROPEN_DEBUG_INFO 0x00000400 188 #define SCRCLOSE_DEBUG_INFO 0x00000800 189 #define SCRREAD_DEBUG_INFO 0x00001000 190 #define SCRWRITE_DEBUG_INFO 0x00002000 191 #define SCRIOCTL_DEBUG_INFO 0x00004000 192 #define MASTER_SM_DEBUG_INFO 0x00008000 193 #define COLD_RESET_SM_DEBUG_INFO 0x00010000 194 #define ATR_SM_DEBUG_INFO 0x00020000 195 #define T0_RECV_BYTE_SM_DEBUG_INFO 0x00040000 196 #define T0_SEND_BYTE_SM_DEBUG_INFO 0x00080000 197 #define T0_RECV_SM_DEBUG_INFO 0x00100000 198 #define T0_SEND_SM_DEBUG_INFO 0x00200000 199 200 201 int scrdebug = //SCRPROBE_DEBUG_INFO | 202 //SCRATTACH_DEBUG_INFO | 203 //SCROPEN_DEBUG_INFO | 204 //SCRCLOSE_DEBUG_INFO | 205 //SCRREAD_DEBUG_INFO | 206 //SCRWRITE_DEBUG_INFO | 207 //SCRIOCTL_DEBUG_INFO | 208 //MASTER_SM_DEBUG_INFO | 209 //COLD_RESET_SM_DEBUG_INFO| 210 //ATR_SM_DEBUG_INFO | 211 //T0_RECV_BYTE_SM_DEBUG_INFO | 212 //T0_SEND_BYTE_SM_DEBUG_INFO | 213 //T0_RECV_SM_DEBUG_INFO | 214 //T0_SEND_SM_DEBUG_INFO | 215 0; 216 217 218 219 220 221 222 /* 223 ** the bottom half of the driver is done as several linked state machines 224 ** below are all the states of the machines, and the commands that are 225 ** sent to each machine 226 */ 227 228 /* commands to Master State Machine from ioctl */ 229 #define mcOn 0x0100 /* ioctl on */ 230 #define mcT0DataSend 0x0102 /* ioctl send */ 231 #define mcT0DataRecv 0x0103 /* ioctl recv */ 232 233 /* commands to Master State Machine from lower state machines */ 234 #define mcColdReset 0x0105 /* cold reset finished */ 235 #define mcATR 0x0106 /* ATR has finished */ 236 #define mcT0Send 0x0108 /* T0 send finished */ 237 #define mcT0Recv 0x010a /* T0 recv finished */ 238 239 /* states in Master state machine (ms = Master State) */ 240 #define msIdleOff 0x0200 /* in idle state, card powered off */ 241 #define msColdReset 0x0201 /* turning on power, clock, reset */ 242 #define msATR 0x0202 /* getting ATR sequence from card */ 243 #define msIdleOn 0x0203 /* idle, put card powered on */ 244 #define msT0Send 0x0204 /* sending T0 data */ 245 #define msT0Recv 0x0205 /* recving T0 data */ 246 247 248 249 250 /* commands to T0 send state machine */ 251 #define t0scStart 0x0300 /* start */ 252 #define t0scTWorkWaiting 0x0301 /* work waiting timeout */ 253 254 /* states in T0 send state machine */ 255 #define t0ssIdle 0x0400 /* idle state */ 256 #define t0ssSendHeader 0x0401 /* send 5 header bytes */ 257 #define t0ssRecvProcedure 0x0402 /* wait for procedure byte */ 258 #define t0ssSendByte 0x0403 /* send 1 byte */ 259 #define t0ssSendData 0x0404 /* send all bytes */ 260 #define t0ssRecvSW1 0x0405 /* wait for sw1 */ 261 #define t0ssRecvSW2 0x0406 /* wait for sw2 */ 262 263 264 265 266 267 /* commands to T0 recv state machine */ 268 #define t0rcStart 0x0500 /* start */ 269 #define t0rcTWorkWaiting 0x0501 /* work waiting timeout */ 270 271 /* states in T0 recv state machine */ 272 #define t0rsIdle 0x0600 /* idle state */ 273 #define t0rsSendHeader 0x0601 /* send 5 header bytes */ 274 #define t0rsRecvProcedure 0x0602 /* wait for procedure byte */ 275 #define t0rsRecvByte 0x0603 /* recv 1 byte */ 276 #define t0rsRecvData 0x0604 /* recv all bytes */ 277 #define t0rsRecvSW1 0x0605 /* wait for sw1 */ 278 #define t0rsRecvSW2 0x0606 /* wait for sw2 */ 279 280 281 282 /* commands to Cold Reset state machine */ 283 #define crcStart 0x0900 /* start */ 284 #define crcT2 0x0902 /* timeout T2 ISO 7816-3, P6, Figure 2 */ 285 286 /* states in cold reset state machine */ 287 #define crsIdle 0x0a00 /* idle */ 288 #define crsT2Wait 0x0a01 /* wait for T2 ISO 7816-3.P6. Figure 2 */ 289 290 291 292 293 294 /* commands to Answer To Reset (ATR) state machine */ 295 #define atrcStart 0x0b00 /* start */ 296 #define atrcT3 0x0b04 /* got T3 timeout */ 297 #define atrcTWorkWaiting 0x0b05 /* work waiting timeout */ 298 299 /* states in Answer To Reset (ATR) state machine */ 300 #define atrsIdle 0x0c00 /* idle */ 301 #define atrsTS 0x0c01 /* looking for TS, (initial bytes) */ 302 #define atrsT0 0x0c02 /* looking for T0, (format bytes) */ 303 #define atrsTABCD 0x0c03 /* looking for TAx (interface bytes)*/ 304 #define atrsTK 0x0c04 /* looking for TK (history bytes) */ 305 #define atrsTCK 0x0c05 /* looking for TCK (check bytes */ 306 307 308 /* commands to T0 Recv Byte state machine */ 309 #define t0rbcStart 0x0d00 /* start */ 310 #define t0rbcAbort 0x0d01 /* abort */ 311 #define t0rbcTFindStartEdge 0x0d02 /* start bit edge search */ 312 #define t0rbcTFindStartMid 0x0d03 /* start bit mid search */ 313 #define t0rbcTClockData 0x0d04 /* data bit search */ 314 #define t0rbcTErrorStart 0x0d05 /* start to send error */ 315 #define t0rbcTErrorStop 0x0d06 /* stop sending error */ 316 317 /* states in T0 Recv Byte state machine */ 318 #define t0rbsIdle 0x0e00 /* idle */ 319 #define t0rbsFindStartEdge 0x0e01 /* looking for start bit */ 320 #define t0rbsFindStartMid 0x0e02 /* looking for start bit */ 321 #define t0rbsClockData 0x0e03 /* looking for data bits */ 322 #define t0rbsSendError 0x0e04 /* output error bit */ 323 324 325 326 327 /* commands to T0 Send Byte state machine */ 328 #define t0sbcStart 0x0f00 /* start the machine */ 329 #define t0sbcAbort 0x0f01 /* abort the machine */ 330 #define t0sbcTGuardTime 0x0f02 /* guard time finished */ 331 #define t0sbcTClockData 0x0f03 /* clock time finished */ 332 #define t0sbcTError 0x0f04 /* start to send error */ 333 #define t0sbcTResend 0x0f05 /* if parity error, then wait unfill we can re-send */ 334 335 336 337 /* states in T0 Send Byte state machine */ 338 #define t0sbsIdle 0x1000 /* idle */ 339 #define t0sbsWaitGuardTime 0x1001 /* wait for guard time to finish */ 340 #define t0sbsClockData 0x1002 /* clocking out data & parity */ 341 #define t0sbsWaitError 0x1003 /* waiting for error indicator */ 342 #define t0sbsWaitResend 0x1004 /* waiting to start re-send if error */ 343 344 345 346 347 /* 348 ** generic middle level state machine commands 349 ** sent by T0 Send Byte & T0 recv Byte to T0 Send and T0 Recv 350 */ 351 #define gcT0RecvByte 0x1100 /* receive finished */ 352 #define gcT0RecvByteErr 0x1101 /* receive got error */ 353 #define gcT0SendByte 0x1102 /* send finished */ 354 #define gcT0SendByteErr 0x1103 /* send got error */ 355 356 357 358 359 360 361 /* 362 ** 363 ** below are definitions associated with Smart Card 364 ** 365 */ 366 367 368 /* 369 ** Frequency of clock sent to card 370 ** NCI's card is running at 1/2 freq, so in debug we can make 371 ** use of this to toggle more debug signals and still be within 372 ** interrupt time budget 373 */ 374 #ifdef SCR_DEBUG 375 #define CARD_FREQ_DEF (3579000/2) 376 #else 377 #define CARD_FREQ_DEF (3579000) 378 #endif 379 380 381 382 /* byte logic level and msb/lsb coding */ 383 #define CONVENTION_UNKNOWN 0 384 #define CONVENTION_INVERSE 1 385 #define CONVENTION_DIRECT 2 386 #define CONVENIONT_INVERSE_ID 0x3f 387 #define CONVENTION_DIRECT_FIX 0x3b 388 #define CONVENTION_DIRECT_ID 0x23 389 390 391 /* macros that help us set the T2 count for bit bashing */ 392 #define CLK_COUNT_START (((372 * TIMER_FREQ) / sc->cardFreq) /5) 393 #define CLK_COUNT_DATA (((372 * TIMER_FREQ) / sc->cardFreq) ) 394 #define START_2_DATA 5 395 396 /* default settings to use if not specified in ATR */ 397 #define N_DEFAULT 0 /* guard time default */ 398 #define Fi_DEFAULT 372 /* clock rate conversion default */ 399 #define Di_DEFAULT 1 /* bit rate adjustment factor */ 400 #define Wi_DEFAULT 10 /* waiting time */ 401 402 403 /* table for clock rate adjustment in ATR */ 404 int FI2Fi[16] = {372, 372, 558, 744,1116,1488,1860, 0, 405 0, 512, 768,1024,1536,2048, 0, 0}; 406 407 /* table for bit rate adjustment in ATR*/ 408 int DI2Di[16] = { 0, 1, 2, 4, 8, 16, 32, 0, 409 12, 20, 0, 0, 0, 0, 0, 0}; 410 411 /* values of atrY in the ATR sequence*/ 412 #define ATR_Y_TA 0x10 413 #define ATR_Y_TB 0x20 414 #define ATR_Y_TC 0x40 415 #define ATR_Y_TD 0x80 416 417 /* T0,T1,etc information in ATR sequence*/ 418 #define PROTOCOL_T0 0x0001 /* bit 0 for T0 */ 419 #define PROTOCOL_T1 0x0002 /* bit 1 for T1 */ 420 #define PROTOCOL_T2 0x0004 /* bit 2 for T2*/ 421 #define PROTOCOL_T3 0x0008 /* bit 3 for T3*/ 422 /* etc */ 423 424 425 /* timeouts for various places - see ISO 7816-3 */ 426 #define T_t2 ((300 * TIMER_FREQ) / sc->cardFreq) 427 #define T_t3 ((40000 * (TIMER_FREQ/1024)) / (sc->cardFreq/1024)) 428 #define T_WORK_WAITING (((960 * sc->Wi * sc->Fi ) / (sc->cardFreq/1024)) * (TIMER_FREQ/1024)) 429 #define PARITY_ERROR_MAX 3 /* maximum parity errors on 1 byte before giving up */ 430 431 /* 432 ** its possible for the HAT to wedge. If that happens, all timing is sick, so 433 ** we use timeout below (driven of system sleeps) as a "watchdog" 434 */ 435 #define MAX_FIQ_TIME 5 /* maximum time we are willing to run the FIQ */ 436 437 438 /* used to decode T0 commands */ 439 #define CMD_BUF_INS_OFF 1 /* offset to INS in header */ 440 #define CMD_BUF_DATA_LEN_OFF 4 /* offset to data length in header */ 441 442 443 /* 444 ** 445 ** DATA STRUCTURES 446 ** 447 */ 448 typedef unsigned char BYTE; 449 450 /* our soft c structure */ 451 struct scr_softc 452 { 453 struct device dev; 454 int open; 455 456 /* configuration information */ 457 int status; /* status to be returned */ 458 int cardFreq; /* freq supplied to card */ 459 int convention; /* ie direct or inverse */ 460 int protocolType; /* bit 0 indicates T0, bit 1 indicates T1,etc */ 461 int N; /* guard time */ 462 int Fi; /* clock rate */ 463 int Di; /* bit rate adjustment */ 464 int Wi; /* work waiting time */ 465 int clkCountStartRecv; /* count for clock start bits on recv */ 466 int clkCountDataRecv; /* count for clock data bits on recv*/ 467 int clkCountDataSend; /* count for clock data bits on send */ 468 469 /* state machines */ 470 int masterS ; 471 int t0RecvS; 472 int t0SendS; 473 int coldResetS; 474 int ATRS; 475 int t0RecvByteS; 476 int t0SendByteS; 477 478 /* extra stuff kept for t0send state machine */ 479 int commandCount; /* number of command bytes sent */ 480 int dataCount; /* number of data bytes send/recv */ 481 int dataMax; /* max number of data bytes to send/recv */ 482 483 /* extra stuff kept for t0RecvByteS, t0SendByteS machines */ 484 void (*t0ByteParent)(struct scr_softc *,int); /* state machine that is controlling this SM */ 485 int shiftBits; /* number of bits shifted */ 486 BYTE shiftByte; /* intermediate value of bit being shifted */ 487 BYTE dataByte; /* actual value of byte */ 488 int shiftParity; /* value of parity */ 489 int shiftParityCount; /* number of retries due to parity error */ 490 491 /* extra stuff kept for ATR machine */ 492 int atrY; /* indicates if TA,TB,TC,TD is to follow */ 493 int atrK; /* number of historical characters*/ 494 int atrKCount; /* progressive could of historical characters*/ 495 int atrTABCDx; /* the 'i' in TA(i), TB(i), TC(i) and TD(i) */ 496 int atrFi; /* value of Fi */ 497 int atrDi; /* value of Di */ 498 499 int masterDone; /* flag used by bottom half to tell top half its done */ 500 int bigTrouble; /* david/jim, remove this when the dust settles */ 501 502 /* pointers used by ioctl */ 503 ScrOn * pIoctlOn; /* pointer to on ioctl data */ 504 ScrT0 * pIoctlT0; /* pointer to T0 ioctl data */ 505 }; 506 507 /* number of devices */ 508 static int devices = 0; 509 510 /* used as reference for tsleep */ 511 static int tsleepIdent; 512 513 514 /* 515 ** only 1 device is using the hat at any one time 516 ** variable below must be acquired using splhigh before using the hat 517 */ 518 static int hatLock = false; 519 520 521 522 523 /* 524 ** data structures associated with our timeout queue that we run for the 525 ** bottom half of the driver 526 */ 527 528 /* timeout callout structure */ 529 typedef struct callout_t 530 { 531 struct callout_t *c_next; /* next callout in queue */ 532 struct scr_softc *c_sc; /* soft c */ 533 int c_arg; /* function argument */ 534 void (*c_func)(struct scr_softc*,int); /* function to call */ 535 int c_time; /* ticks to the event */ 536 }Callout; 537 538 /* actual callout array */ 539 #define SCR_CLK_CALLOUT_COUNT 10 540 static Callout scrClkCalloutArray[SCR_CLK_CALLOUT_COUNT]; 541 542 /* callout lists */ 543 static Callout *scrClkCallFree; /* free queue */ 544 static Callout scrClkCallTodo; /* todo queue */ 545 546 /* 547 ** information kept for the clock/FIQ that drives our timeout queue 548 */ 549 static int scrClkEnable = 0; /* true if clock enabled */ 550 static void myHatWedge(int nFIQs); /* callback that informs us if FIQ has wedged */ 551 static int scrClkCount; /* number used to set t2 that drives FIQ */ 552 553 #define HATSTACKSIZE 1024 /* size of stack used during a FIQ */ 554 static unsigned char hatStack[HATSTACKSIZE]; /* actual stack used during a FIQ */ 555 556 557 558 559 560 561 562 563 564 565 566 567 /* 568 ** 569 ** FUNCTIONAL PROTOTYPES 570 ** 571 */ 572 573 /* 574 ** 575 ** functions in top half of driver 576 ** 577 */ 578 579 /* configure routines */ 580 int scrprobe(struct device *, struct cfdata *, void *); 581 void scrattach(struct device *, struct device *, void *); 582 583 static void initStates(struct scr_softc * sc); 584 585 586 587 588 /* 589 ** 590 ** functions in bottom half of driver 591 ** 592 */ 593 594 /* top level state machine */ 595 static void masterSM(struct scr_softc * sc,int cmd); 596 597 /* mid level state machines, ie protocols */ 598 static void t0SendSM(struct scr_softc * sc,int cnd); 599 static void t0RecvSM(struct scr_softc * sc,int cnd); 600 static void ATRSM(struct scr_softc * sc,int cnd); 601 602 /* low level state machines, ie bash hardware bits */ 603 static void coldResetSM(struct scr_softc * sc,int cnd); 604 605 static void t0SendByteSM(struct scr_softc * sc,int cnd); 606 static void t0RecvByteSM(struct scr_softc * sc,int cnd); 607 608 static void cardOff(struct scr_softc * sc); 609 610 /* 611 ** functions used for our own timeout routines. 612 ** we cannot use system ones as we are running at a spl level 613 ** that can interrupt the system timeout routines 614 */ 615 static void scrClkInit(void); 616 static void scrClkStart(struct scr_softc* sc,int countPerTick); 617 static void scrClkAdj(int count); 618 static void scrClkStop(void); 619 static void hatClkIrq(int count); 620 621 static void scrTimeout(void (*func)(struct scr_softc*,int), struct scr_softc*, int arg, int count); 622 static void scrUntimeout(void (*func)(struct scr_softc*,int), struct scr_softc*, int arg); 623 624 625 /* debug functions */ 626 #ifdef SCR_DEBUG 627 static void invalidStateCmd(struct scr_softc* sc,int state,int cmd, int line); 628 static char * getText(int x); 629 #endif 630 631 632 633 634 635 CFATTACH_DECL(scr, sizeof(struct scr_softc), 636 scrprobe, scrattach, NULL, NULL); 637 638 extern struct cfdriver scr_cd; 639 640 dev_type_open(scropen); 641 dev_type_close(scrclose); 642 dev_type_ioctl(scrioctl); 643 644 const struct cdevsw scr_cdevsw = { 645 scropen, scrclose, noread, nowrite, scrioctl, 646 nostop, notty, nopoll, nommap, nokqfilter, D_TTY 647 }; 648 649 /* 650 **++ 651 ** FUNCTIONAL DESCRIPTION: 652 ** 653 ** scrProbe 654 ** 655 ** This is the probe routine for the Smart Card. Because the 656 ** Smart Card is hard wired, there is no probing to peform. The 657 ** function ensures that a succesfull problem occurs only once. 658 ** 659 ** FORMAL PARAMETERS: 660 ** 661 ** parent - input : pointer to the parent device 662 ** match - not used 663 ** aux - output : pointer to an isa_attach_args structure. 664 ** 665 ** IMPLICIT INPUTS: 666 ** 667 ** none. 668 ** 669 ** IMPLICIT OUTPUTS: 670 ** 671 ** none. 672 ** 673 ** FUNCTION VALUE: 674 ** 675 ** 0 - Probe failed to find the requested device. 676 ** 1 - Probe successfully talked to the device. 677 ** 678 ** SIDE EFFECTS: 679 ** 680 ** none. 681 **-- 682 */ 683 int scrprobe(parent, match, aux) 684 struct device *parent; 685 struct cfdata *match; 686 void *aux; 687 { 688 struct isa_attach_args *ia = aux; 689 int rv = 0; 690 691 KERN_DEBUG (scrdebug, SCRPROBE_DEBUG_INFO,("scrprobe: called, name = %s\n", 692 device_cfdata(parent)->cf_name)); 693 694 if (device_is_a(parent, "ofisascr") && devices == 0) 695 { 696 /* set "devices" to ensure that we respond only once */ 697 devices++; 698 699 /* tell the caller that we are not using any resource */ 700 ia->ia_nio = 0; 701 ia->ia_niomem = 0; 702 ia->ia_nirq = 0; 703 ia->ia_ndrq = 0; 704 rv = 1; 705 706 707 KERN_DEBUG (scrdebug, SCRPROBE_DEBUG_INFO,("scrprobe: successful \n")); 708 709 } 710 711 712 return (rv); 713 714 } /* End scrprobe() */ 715 716 717 /* 718 **++ 719 ** FUNCTIONAL DESCRIPTION: 720 ** 721 ** scrattach 722 ** 723 ** Initialize the clock and state machines 724 ** 725 ** FORMAL PARAMETERS: 726 ** 727 ** parent - input : pointer to my parents device structure. 728 ** self - output : pointer to my softc with device structure at front. 729 ** aux - input : pointer to the isa_attach_args structure. 730 ** 731 ** IMPLICIT INPUTS: 732 ** 733 ** nill 734 ** 735 ** IMPLICIT OUTPUTS: 736 ** 737 ** scrconsinit - clock callout functions set 738 ** state machines all at idle 739 ** 740 ** FUNCTION VALUE: 741 ** 742 ** none. 743 ** 744 ** SIDE EFFECTS: 745 ** 746 ** none. 747 **-- 748 */ 749 void scrattach(parent, self, aux) 750 struct device *parent; 751 struct device *self; 752 void *aux; 753 { 754 struct scr_softc *sc = (void *)self; 755 756 printf("\n"); 757 if (device_is_a(parent, "ofisascr")) 758 { 759 KERN_DEBUG (scrdebug, SCRATTACH_DEBUG_INFO,("scrattach: called \n")); 760 761 /* set initial state machine values */ 762 scrClkInit(); 763 initStates(sc); 764 sc->open = false; 765 } 766 767 else 768 { 769 panic("scrattach: not on an ISA bus, attach impossible"); 770 } /* End else we aren't on ISA and we can't handle it */ 771 772 773 return; 774 } /* End scrattach() */ 775 776 777 /* 778 **++ 779 ** FUNCTIONAL DESCRIPTION: 780 ** 781 ** initStates 782 ** 783 ** sets the state of all machines to idle 784 ** 785 ** FORMAL PARAMETERS: 786 ** 787 ** sc - Pointer to the softc structure. 788 ** 789 ** IMPLICIT INPUTS: 790 ** 791 ** nill 792 ** 793 ** IMPLICIT OUTPUTS: 794 ** 795 ** nill 796 ** 797 ** FUNCTION VALUE: 798 ** 799 ** nill 800 ** 801 ** SIDE EFFECTS: 802 ** 803 ** nill 804 **-- 805 */ 806 static void initStates(struct scr_softc * sc) 807 { 808 sc->masterS = msIdleOff; 809 sc->t0RecvS = t0rsIdle; 810 sc->t0SendS = t0ssIdle; 811 sc->coldResetS = crsIdle; 812 sc->ATRS = atrsIdle; 813 sc->t0RecvByteS = t0rbsIdle; 814 sc->t0SendByteS = t0sbsIdle; 815 } 816 817 818 819 /* 820 **++ 821 ** FUNCTIONAL DESCRIPTION: 822 ** 823 ** scrOpen 824 ** 825 ** Opens the driver. We only let the device be opened 826 ** once for security reasons 827 ** 828 ** FORMAL PARAMETERS: 829 ** 830 ** dev - input : Device identifier consisting of major and minor numbers. 831 ** flag - input : Indicates if this is a blocking I/O call. 832 ** mode - not used. 833 ** l - input : Pointer to the lwp structure of the light weight process 834 ** performing the open. 835 ** 836 ** IMPLICIT INPUTS: 837 ** 838 ** none. 839 ** 840 ** IMPLICIT OUTPUTS: 841 ** 842 ** none. 843 ** 844 ** FUNCTION VALUE: 845 ** 846 ** ENXIO - invalid device specified for open. 847 ** EBUSY - The unit is already open 848 ** 849 ** SIDE EFFECTS: 850 ** 851 ** none. 852 **-- 853 */ 854 int scropen(dev_t dev, int flag, int mode, struct lwp *l) 855 { 856 struct scr_softc *sc; 857 858 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO, 859 ("scropen: called with minor device %d and flag 0x%x\n", 860 SCRUNIT(dev), flag)); 861 862 sc = device_lookup_private(&scr_cd, SCRUNIT(dev)); 863 if (!sc) 864 { 865 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return ENXIO\n")); 866 return (ENXIO); 867 } 868 869 870 // david,jim - remove ifdef this when NCI can cope with only 1 open 871 #if 0 872 if (sc->open) 873 { 874 875 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return EBUSY\n")); 876 return (EBUSY); 877 } 878 879 880 /* set all initial conditions */ 881 sc->open = true; 882 #endif 883 884 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("scropen: success \n")); 885 /* Now invoke the line discipline open routine 886 */ 887 888 return 0; 889 890 } /* End scropen() */ 891 892 893 /* 894 **++ 895 ** FUNCTIONAL DESCRIPTION: 896 ** 897 ** This function closed the driver 898 ** 899 ** FORMAL PARAMETERS: 900 ** 901 ** dev - input : Device identifier consisting of major and minor numbers. 902 ** flag - Not used. 903 ** mode - Not used. 904 ** p - Not used. 905 ** 906 ** IMPLICIT INPUTS: 907 ** 908 ** scr_cd - used to locate the softc structure for the device unit 909 ** identified by dev. 910 ** 911 ** IMPLICIT OUTPUTS: 912 ** 913 ** The device is put into an idle state. 914 ** 915 ** FUNCTION VALUE: 916 ** 917 ** 0 - Always returns success. 918 ** 919 ** SIDE EFFECTS: 920 ** 921 ** none. 922 **-- 923 */ 924 int scrclose(dev_t dev, int flag, int mode, struct lwp *l) 925 { 926 #if 0 927 struct scr_softc *sc = device_lookup_private(&scr_cd, SCRUNIT(dev)); 928 #endif 929 930 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO, 931 ("scrclose: called for minor device %d flag 0x%x\n", 932 SCRUNIT(dev), flag)); 933 934 // david,jim - remove ifdef this when NCI can cope with only 1 open 935 #if 0 936 /* Check we are open in the first place 937 */ 938 if (sc->open) 939 { 940 /* put everything in the idle state */ 941 scrClkInit(); 942 initStates(sc); 943 sc->open = false; 944 945 } 946 947 948 else 949 { 950 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO,("\t scrclose, device not open\n")); 951 } 952 #endif 953 954 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO,("scrclose exiting\n")); 955 return(0); 956 } 957 958 /* 959 **++ 960 ** FUNCTIONAL DESCRIPTION: 961 ** 962 ** This routine is responsible for performing I/O controls. 963 ** 964 ** There are 4 commands. Status, On, T0 and Off. 965 ** 966 ** Status checks to see if the card is inserted. This command 967 ** does not use the state machines 968 ** 969 ** On turns the card on and gets the ATR sequence from the card. 970 ** This command does use the state machines 971 ** 972 ** T0 is used to read and write the card. This command does use 973 ** the state machines 974 ** 975 ** Off turns the card off. This command does not use the state 976 ** machines. 977 ** 978 ** 979 ** FORMAL PARAMETERS: 980 ** 981 ** dev - input : Device identifier consisting of major and minor numbers. 982 ** cmd - input : The requested IOCTL command to be performed. 983 ** See scrio.h for details 984 ** 985 ** 986 ** Bit Position { 3322222222221111111111 987 ** { 10987654321098765432109876543210 988 ** Meaning | DDDLLLLLLLLLLLLLGGGGGGGGCCCCCCCC 989 ** 990 ** D - Command direction, in/out/both. 991 ** L - Command argument length. 992 ** G - Command group, 't' used for tty. 993 ** C - Actual command enumeration. 994 ** 995 ** data - input/output : Direction depends on the command. 996 ** flag - input : Not used by us but passed to line discipline and ttioctl 997 ** l - input : pointer to lwp structure of user. 998 ** 999 ** IMPLICIT INPUTS: 1000 ** 1001 ** none. 1002 ** 1003 ** IMPLICIT OUTPUTS: 1004 ** 1005 ** sc->masterS state of master state machine 1006 ** 1007 ** 1008 ** FUNCTION VALUE: 1009 ** 1010 ** ENOTTY if not correct ioctl 1011 ** 1012 ** 1013 ** SIDE EFFECTS: 1014 ** 1015 **-- 1016 */ 1017 int 1018 scrioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1019 { 1020 struct scr_softc* sc = device_lookup_private(&scr_cd, SCRUNIT(dev)); 1021 1022 int error = 0; /* error value returned */ 1023 int masterDoneRetries= 0; /* nuber of times we looked at masterDone */ 1024 int done; /* local copy of masterDone */ 1025 1026 ScrStatus * pIoctlStatus; /* pointer to status ioctl */ 1027 ScrOff * pIoctlOff; /* pointer to off ioctl */ 1028 1029 u_int savedInts; /* saved interrupts */ 1030 int s; /* saved spl value */ 1031 1032 1033 1034 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO, 1035 ("scrioctl: called for device 0x%x, command 0x%lx, " 1036 "flag 0x%x\n", 1037 SCRUNIT(dev), cmd, flag)); 1038 1039 1040 1041 switch (cmd) 1042 { 1043 /* 1044 ** get the status of the card, ie is it in, in but off, in and on 1045 */ 1046 case SCRIOSTATUS: 1047 pIoctlStatus = (ScrStatus*)data; 1048 if (scrGetDetect()) 1049 { 1050 savedInts = disable_interrupts(I32_bit | F32_bit); 1051 if (sc->masterS == msIdleOn) 1052 { 1053 pIoctlStatus->status = CARD_ON; 1054 } 1055 else 1056 { 1057 ASSERT(sc->masterS == msIdleOff); 1058 pIoctlStatus->status = CARD_INSERTED; 1059 } 1060 restore_interrupts(savedInts); 1061 } 1062 1063 else 1064 { 1065 pIoctlStatus->status = CARD_REMOVED; 1066 } 1067 break; 1068 1069 1070 1071 /* 1072 ** turn the card on and get the ATR sequence 1073 */ 1074 case SCRIOON: 1075 sc->pIoctlOn = (ScrOn*)data; 1076 // acquire the hat lock. 1077 while (1) 1078 { 1079 s = splhigh(); 1080 if(!hatLock) 1081 { 1082 hatLock = true; 1083 splx(s); 1084 break; 1085 } 1086 splx(s); 1087 1088 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1089 } 1090 1091 1092 // check to see if the card is in 1093 if(!scrGetDetect()) 1094 { 1095 initStates(sc); 1096 cardOff(sc); 1097 // do not call scrClkInit() as it is idle already 1098 sc->pIoctlOn->status = ERROR_CARD_REMOVED; 1099 } 1100 1101 1102 // check to see if we are already on 1103 else if(sc->masterS == msIdleOn) 1104 { 1105 sc->pIoctlOn->status = ERROR_CARD_ON; 1106 } 1107 1108 // card was in, card is off, so lets start it 1109 else 1110 { 1111 // set up the top half 1112 sc->masterDone = false; 1113 sc->bigTrouble = false; /* david/jim, remove this when the dust settles */ 1114 1115 1116 1117 // start bottom half 1118 scrClkStart (sc,400); 1119 savedInts = disable_interrupts(I32_bit | F32_bit); 1120 masterSM(sc,mcOn); 1121 restore_interrupts(savedInts); 1122 1123 1124 1125 // see if bottom half done 1126 while (1) 1127 { 1128 // check that we have not looped too many times 1129 if(masterDoneRetries >= MAX_FIQ_TIME * hz) 1130 { 1131 //printf("MAX_FIQ_TIME reached \n"); 1132 // big problems, so reset bottom 1133 savedInts = disable_interrupts(I32_bit | F32_bit); 1134 scrClkInit(); 1135 initStates(sc); 1136 cardOff(sc); 1137 sc->status = ERROR_CARD_REMOVED; 1138 sc->masterDone = true; 1139 restore_interrupts(savedInts); 1140 // dont stop clock, done at bottom of case 1141 } 1142 masterDoneRetries++; 1143 1144 // get done bit 1145 savedInts = disable_interrupts(I32_bit | F32_bit); 1146 done = sc->masterDone; 1147 restore_interrupts(savedInts); 1148 1149 // see if all done 1150 if(done) 1151 { 1152 break; 1153 } 1154 1155 1156 // wait for a while 1157 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1158 } 1159 1160 1161 // stop bottom half 1162 scrClkStop(); 1163 1164 1165 /* need to fix up count bits in non hat interrupt time, so */ 1166 if (sc->status == ERROR_OK) 1167 { 1168 sc->clkCountStartRecv = CLK_COUNT_START; 1169 sc->clkCountDataRecv = sc->clkCountStartRecv * START_2_DATA; 1170 sc->clkCountDataSend = CLK_COUNT_DATA; 1171 } 1172 1173 1174 1175 /* takes while to turn off all lines, so keep out of hat */ 1176 if (sc->masterS != msIdleOn) 1177 { 1178 cardOff(sc); 1179 } 1180 // get the status back from the state machine 1181 sc->pIoctlOn->status = sc->status; 1182 1183 1184 } 1185 1186 1187 // release the hat lock. 1188 s = splhigh(); 1189 ASSERT(hatlock); 1190 hatLock = false; 1191 splx(s); 1192 1193 // david,jim hack to stop ioctl memcpy problem, to be removed when problem fixed ejg 1194 if (sc->pIoctlOn->status != ERROR_OK) 1195 { 1196 sc->pIoctlOn->atrLen = 0; 1197 } 1198 break; 1199 1200 1201 /* 1202 ** turn the card off 1203 */ 1204 case SCRIOOFF: 1205 pIoctlOff = (ScrOff*)data; 1206 // card off does not requires any state processing, so do work here 1207 initStates(sc); 1208 cardOff(sc); 1209 // do not call scrClkInit() as it is idle already 1210 pIoctlOff->status = ERROR_OK; 1211 break; 1212 1213 1214 /* 1215 ** do a T0 read or write 1216 */ 1217 case SCRIOT0: 1218 sc->pIoctlT0 = (ScrT0*)data; 1219 1220 // acquire the hat lock. 1221 while (1) 1222 { 1223 s = splhigh(); 1224 if(!hatLock) 1225 { 1226 hatLock = true; 1227 splx(s); 1228 break; 1229 } 1230 splx(s); 1231 1232 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1233 } 1234 1235 // check to see if the card is in 1236 if(!scrGetDetect()) 1237 { 1238 initStates(sc); 1239 cardOff(sc); 1240 // do not call scrClkInit() as it is idle already 1241 sc->pIoctlT0->status = ERROR_CARD_REMOVED; 1242 } 1243 1244 1245 // check to see if card is off 1246 else if(sc->masterS == msIdleOff) 1247 { 1248 sc->pIoctlT0->status = ERROR_CARD_OFF; 1249 } 1250 1251 // card was in, card is on, lets do command 1252 else 1253 1254 { 1255 // set up the top half 1256 sc->masterDone = false; 1257 sc->bigTrouble = false; /* david/jim, remove this when the dust settles */ 1258 1259 // start bottom half 1260 scrClkStart (sc,sc->clkCountDataSend); 1261 savedInts = disable_interrupts(I32_bit | F32_bit); 1262 if (sc->pIoctlT0->writeBuffer) 1263 { 1264 masterSM(sc,mcT0DataSend); 1265 } 1266 else 1267 { 1268 masterSM(sc,mcT0DataRecv); 1269 } 1270 restore_interrupts(savedInts); 1271 1272 1273 // see if bottom half done 1274 while (1) 1275 { 1276 // check that we have not looped too many times 1277 if(masterDoneRetries >= MAX_FIQ_TIME * hz) 1278 { 1279 //printf("MAX_FIQ_TIME reached \n"); 1280 // big problems, so reset bottom 1281 savedInts = disable_interrupts(I32_bit | F32_bit); 1282 scrClkInit(); 1283 initStates(sc); 1284 cardOff(sc); 1285 sc->status = ERROR_CARD_REMOVED; 1286 sc->masterDone = true; 1287 restore_interrupts(savedInts); 1288 } 1289 masterDoneRetries++; 1290 1291 1292 // get done bit 1293 savedInts = disable_interrupts(I32_bit | F32_bit); 1294 done = sc->masterDone; 1295 restore_interrupts(savedInts); 1296 1297 1298 // see if all done 1299 if(done) 1300 { 1301 break; 1302 } 1303 1304 1305 // wait for a while 1306 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1307 } 1308 1309 // stop bottom half 1310 scrClkStop(); 1311 1312 1313 1314 // get the status back from the state machine 1315 sc->pIoctlT0->status = sc->status; 1316 } 1317 1318 1319 // release the hat lock. 1320 s = splhigh(); 1321 hatLock = false; 1322 splx(s); 1323 1324 1325 1326 // david, jim hack to stop ioctl memcpy problem, to be removed when problem fixed ejg 1327 if (sc->pIoctlT0->status != ERROR_OK) 1328 { 1329 sc->pIoctlT0->dataLen = 0; 1330 } 1331 break; 1332 1333 default: 1334 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO,("\t scrioctl: unknown command, ENOTTY \n")); 1335 error = ENOTTY; 1336 break; 1337 } 1338 1339 1340 1341 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO, 1342 ("scrioctl: exiting with sc->status %d\n", error)); 1343 return (error); 1344 } /* End scrioctl */ 1345 1346 1347 1348 1349 1350 1351 /* 1352 ** 1353 ** All functions below this point are the bottom half of the driver 1354 ** 1355 ** All are called during a FIQ, except for some functions in masterSM which 1356 ** provides the interface between the bottom half and top half of 1357 ** the driver (nb masterDone() helps masterSM() out with this interface 1358 ** between top and bottom parts of the driver. 1359 ** 1360 */ 1361 1362 1363 /* 1364 **++ 1365 ** FUNCTIONAL DESCRIPTION: 1366 ** 1367 ** masterSM 1368 ** 1369 ** This state machine implements the top level state control It 1370 ** receives commands to turn the card on, and do T0 reads and T0 writes 1371 ** from the scrioctl. It then calls mid level state machine to action 1372 ** these commands. 1373 ** 1374 ** This machine is the only machine to keep state between scrioctl calls. 1375 ** Between calls, the state will be either msIdleOff, or msIdleOn. msIdleOff 1376 ** indicates that no signals are applied to the card. msidleOn indicates that 1377 ** power and clock are supplied to the card, and that the card has performed 1378 ** a successful ATR sequence. 1379 ** 1380 ** This routine gets called during FIQ interrupts and from scrioctl. It is a 1381 ** requirement that the scrioctl disables interrupts before calling this function. 1382 ** 1383 ** NB:- there is no way for the machine to get from msIdleOn to msIdleOff. Since 1384 ** this is just a mater of turning all signals off and resetting state machines, 1385 ** scrioctl takes a shortcut and resets everything itself. Ie it hits everything 1386 ** with a big hammer!! 1387 ** 1388 ** FORMAL PARAMETERS: 1389 ** 1390 ** sc - Pointer to the softc structure. 1391 ** cmd - command to the state machine, can be from ioctl, or mid level SM 1392 ** 1393 ** IMPLICIT INPUTS: 1394 ** 1395 ** sc->masterS state of this machine 1396 ** sc->pIoctlT0 pointer to T0 ioctl 1397 ** 1398 ** IMPLICIT OUTPUTS: 1399 ** 1400 ** 1401 ** FUNCTION VALUE: 1402 ** 1403 ** nill 1404 ** 1405 ** SIDE EFFECTS: 1406 ** 1407 ** power and clock applied to card if successful ATR 1408 **-- 1409 */ 1410 static void masterSM(struct scr_softc * sc,int cmd) 1411 { 1412 1413 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1414 1415 switch (sc->masterS) 1416 { 1417 case msIdleOff: 1418 switch (cmd) 1419 { 1420 case mcOn: 1421 if (scrGetDetect()) 1422 { 1423 /* 1424 ** the card is off, and we want it on 1425 */ 1426 1427 /* set initial values */ 1428 sc->status = 0; 1429 sc->convention = CONVENTION_UNKNOWN; 1430 sc->protocolType = 0; 1431 sc->N = N_DEFAULT; 1432 sc->Fi = Fi_DEFAULT; 1433 sc->Di = Di_DEFAULT; 1434 sc->Wi = Wi_DEFAULT; 1435 sc->cardFreq = CARD_FREQ_DEF; 1436 sc->clkCountStartRecv = CLK_COUNT_START; 1437 sc->clkCountDataRecv = sc->clkCountStartRecv * START_2_DATA; 1438 sc->clkCountDataSend = CLK_COUNT_DATA; 1439 1440 /* get coldResetSM to turn on power, clock, reset */ 1441 sc->masterS = msColdReset; 1442 coldResetSM(sc,crcStart); 1443 } 1444 else 1445 { 1446 /* card not inserted, so just set status and give up */ 1447 sc->status = ERROR_CARD_REMOVED; 1448 sc->masterDone = true; 1449 } 1450 break; 1451 1452 default: 1453 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1454 break; 1455 } 1456 break; 1457 1458 case msColdReset: 1459 switch (cmd) 1460 { 1461 case mcColdReset: 1462 /* 1463 ** coldResetSM has turned on power, clock , reset 1464 ** tell ATRSM to get the ATR sequence from the card 1465 */ 1466 sc->masterS = msATR; 1467 ATRSM(sc,atrcStart); 1468 break; 1469 1470 default: 1471 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1472 break; 1473 } 1474 break; 1475 1476 case msATR: 1477 switch (cmd) 1478 { 1479 case mcATR: 1480 /* 1481 ** ATRSM has tried to get ATR sequence, so give 1482 ** back results to scrioctl. ATR sequence data 1483 ** was copied directly into ioctl data area, so 1484 ** no need to copy data 1485 */ 1486 if(sc->status == ERROR_OK) 1487 { 1488 sc->masterS = msIdleOn; 1489 } 1490 else 1491 { 1492 sc->masterS = msIdleOff; 1493 } 1494 sc->masterDone = true; 1495 break; 1496 1497 1498 default: 1499 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1500 break; 1501 } 1502 break; 1503 1504 case msIdleOn: 1505 switch (cmd) 1506 { 1507 // nb there is no command to go to the IdleOff state. This 1508 // is a reset of the state machine, so is done in ioctl 1509 1510 case mcT0DataSend: 1511 /* 1512 ** card is on, and we want to T0 Send, so 1513 ** as t0SendSM to do work 1514 */ 1515 sc->status = ERROR_OK; 1516 sc->masterS = msT0Send; 1517 t0SendSM(sc,t0scStart); 1518 break; 1519 1520 case mcT0DataRecv: 1521 /* 1522 ** card is on, and we want to T0 Recv, so 1523 ** as t0RecvSM to do work 1524 */ 1525 sc->status = ERROR_OK; 1526 sc->masterS = msT0Recv; 1527 t0RecvSM(sc,t0rcStart); 1528 break; 1529 1530 default: 1531 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1532 break; 1533 } 1534 1535 break; 1536 1537 case msT0Send: 1538 switch (cmd) 1539 { 1540 case mcT0Send: 1541 /* 1542 ** t0SendSM has tried to send , so lets give back results 1543 */ 1544 sc->masterS = msIdleOn; 1545 sc->masterDone = true; 1546 break; 1547 1548 default: 1549 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1550 break; 1551 } 1552 break; 1553 1554 case msT0Recv: 1555 switch (cmd) 1556 { 1557 case mcT0Recv: 1558 /* 1559 ** t0RecvSM has tried to recv , so lets give back results 1560 ** data was written directly into ioctl data area, so we 1561 ** do not need to copy any data 1562 */ 1563 sc->pIoctlT0->dataLen = sc->dataCount; 1564 sc->masterS = msIdleOn; 1565 sc->masterDone = true; 1566 break; 1567 1568 default: 1569 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1570 break; 1571 } 1572 break; 1573 1574 default: 1575 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1576 break; 1577 1578 } 1579 } 1580 1581 1582 1583 1584 /* 1585 **++ 1586 ** FUNCTIONAL DESCRIPTION: 1587 ** 1588 ** t0SendSM 1589 ** 1590 ** This is the T=0 Send State Machine. It is responsible 1591 ** for performing the send part of the ISO 7816-3 T=0 1592 ** protocol. It is mid level protocol state machine. 1593 ** 1594 ** Once started, this machine is driven entirely via the 1595 ** FIQ/timeout structure . 1596 ** 1597 ** 1598 ** 1599 ** FORMAL PARAMETERS: 1600 ** 1601 ** sc - Pointer to the softc structure. 1602 ** cmd - command to this machine 1603 ** 1604 ** IMPLICIT INPUTS: 1605 ** 1606 ** sc->t0SendS state of this machine 1607 ** sc->pIoctlT0->command command to send to card 1608 ** sc->pIoctlT0->data data to send to card 1609 ** 1610 ** IMPLICIT OUTPUTS: 1611 ** 1612 ** sc->status error status from this machine 1613 ** sc->pIoctlT0->sw1 command status from card 1614 ** sc->pIoctlT0->sw2 command status from card 1615 ** sc->status error status from this machine 1616 ** 1617 ** FUNCTION VALUE: 1618 ** 1619 ** nill 1620 ** 1621 ** SIDE EFFECTS: 1622 ** 1623 ** nill 1624 **-- 1625 */ 1626 static void t0SendSM (struct scr_softc * sc, int cmd) 1627 { 1628 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1629 /* 1630 ** check for major failures that are common to most states 1631 */ 1632 if (cmd == t0scTWorkWaiting || 1633 cmd == gcT0RecvByteErr || 1634 cmd == gcT0SendByteErr 1635 ) 1636 { 1637 switch(cmd) 1638 { 1639 case t0scTWorkWaiting: 1640 ASSERT(sc->t0SendS != t0ssIdle); 1641 1642 /* kill all lower machines */ 1643 t0SendByteSM(sc,t0sbcAbort); 1644 t0RecvByteSM(sc,t0rbcAbort); 1645 1646 /* set status */ 1647 sc->status = ERROR_WORK_WAITING; 1648 break; 1649 1650 case gcT0RecvByteErr: // fall through 1651 case gcT0SendByteErr: 1652 scrUntimeout(t0SendSM, sc, t0scTWorkWaiting); 1653 // done set status, already set in lower machine 1654 break; 1655 1656 default: 1657 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1658 break; 1659 } 1660 1661 /* change states */ 1662 sc->t0SendS = t0ssIdle; 1663 masterSM(sc,mcT0Send); 1664 return; 1665 } 1666 1667 switch (sc->t0SendS) 1668 { 1669 case t0ssIdle: 1670 switch (cmd) 1671 { 1672 case t0scStart: 1673 /* set initial values */ 1674 sc->t0SendS = t0ssSendHeader; 1675 sc->t0ByteParent = t0SendSM; 1676 sc->commandCount = 0; 1677 sc->dataCount = 0; 1678 sc->dataMax = sc->pIoctlT0->command[CMD_BUF_DATA_LEN_OFF]; 1679 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1680 1681 // get a byte 1682 t0SendByteSM(sc,t0sbcStart); 1683 break; 1684 1685 default: 1686 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1687 break; 1688 } 1689 break; 1690 1691 case t0ssSendHeader: 1692 switch (cmd) 1693 { 1694 case gcT0SendByte: 1695 sc->commandCount++; 1696 if (sc->commandCount < CMD_BUF_LEN) 1697 { 1698 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1699 t0SendByteSM(sc,t0sbcStart); 1700 } 1701 else 1702 { 1703 ASSERT(sc->commandCount == CMD_BUF_LEN); 1704 1705 sc->t0SendS = t0ssRecvProcedure; 1706 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1707 t0RecvByteSM(sc,t0rbcStart); 1708 } 1709 break; 1710 1711 default: 1712 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1713 break; 1714 } 1715 break; 1716 1717 case t0ssRecvProcedure: 1718 switch (cmd) 1719 { 1720 case gcT0RecvByte: 1721 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1722 /* see if we should send all remaining bytes */ 1723 if ( (sc->dataByte == sc->pIoctlT0->command[CMD_BUF_INS_OFF]) || 1724 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0x01)) ) 1725 { 1726 ASSERT(sc->dataCount < sc->dataMax); 1727 sc->t0SendS = t0ssSendData; 1728 sc->dataByte = sc->pIoctlT0->data[sc->dataCount]; 1729 t0SendByteSM(sc,t0sbcStart); 1730 sc->dataCount++; 1731 } 1732 1733 /* see if we should send one data byte */ 1734 else if ((sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFF)) || 1735 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFE)) ) 1736 { 1737 ASSERT(sc->dataCount < sc->dataMax); 1738 sc->t0SendS = t0ssSendByte; 1739 sc->dataByte = sc->pIoctlT0->data[ sc->dataCount]; 1740 t0SendByteSM(sc,t0sbcStart); 1741 sc->dataCount++; 1742 } 1743 1744 /* see if we should extend the work waiting period */ 1745 else if (sc->dataByte == 0x60) 1746 { 1747 t0RecvByteSM(sc,t0rbcStart); 1748 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1749 } 1750 1751 #ifdef ORIGINAL_SW1_CODE /* XXX XXX XXX cgd */ 1752 /* see if we have a SW1 byte */ 1753 else if ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) 1754 && 1755 sc->dataByte != 0x60) 1756 #else /* XXX XXX XXX cgd */ 1757 /* see if we have a SW1 byte */ 1758 else if ( ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) ) 1759 && 1760 sc->dataByte != 0x60) 1761 #endif /* XXX XXX XXX cgd */ 1762 { 1763 sc->pIoctlT0->sw1 = sc->dataByte; 1764 sc->t0SendS = t0ssRecvSW2; 1765 t0RecvByteSM(sc,t0rbcStart); 1766 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1767 } 1768 1769 /* got bad data byte, log error and get out */ 1770 else 1771 { 1772 sc->status = ERROR_BAD_PROCEDURE_BYTE; 1773 1774 /* change state */ 1775 sc->t0SendS = t0ssIdle; 1776 masterSM(sc,mcT0Send); 1777 } 1778 break; 1779 1780 default: 1781 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1782 break; 1783 } 1784 break; 1785 1786 case t0ssSendByte: 1787 switch (cmd) 1788 { 1789 case gcT0SendByte: 1790 if (sc->dataCount < sc->dataMax) 1791 { 1792 sc->t0SendS = t0ssRecvProcedure; 1793 } 1794 1795 /* wait for sw1 byte */ 1796 else 1797 { 1798 ASSERT(sc->dataCount == sc->dataMax); 1799 sc->t0SendS = t0ssRecvSW1; 1800 } 1801 1802 // ask for another byte 1803 t0RecvByteSM(sc,t0rbcStart); 1804 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1805 break; 1806 1807 default: 1808 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1809 break; 1810 } 1811 break; 1812 1813 case t0ssSendData: 1814 switch (cmd) 1815 { 1816 case gcT0SendByte: 1817 /* send data */ 1818 if (sc->dataCount < sc->dataMax) 1819 { 1820 sc->t0SendS = t0ssSendData; 1821 sc->dataByte = sc->pIoctlT0->data[ sc->dataCount]; 1822 t0SendByteSM(sc,t0sbcStart); 1823 sc->dataCount++; 1824 } 1825 1826 /* wait for sw1 byte */ 1827 else 1828 { 1829 ASSERT(sc->dataCount == sc->dataMax); 1830 sc->t0SendS = t0ssRecvSW1; 1831 t0RecvByteSM(sc,t0rbcStart); 1832 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1833 } 1834 break; 1835 1836 default: 1837 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1838 break; 1839 } 1840 break; 1841 1842 case t0ssRecvSW1: 1843 switch (cmd) 1844 { 1845 case gcT0RecvByte: 1846 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1847 sc->pIoctlT0->sw1 = sc->dataByte; 1848 sc->t0SendS = t0ssRecvSW2; 1849 t0RecvByteSM(sc,t0rbcStart); 1850 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1851 break; 1852 default: 1853 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1854 break; 1855 } 1856 break; 1857 1858 case t0ssRecvSW2: 1859 switch (cmd) 1860 { 1861 case gcT0RecvByte: 1862 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1863 sc->pIoctlT0->sw2 = sc->dataByte; 1864 sc->t0SendS = t0ssIdle; 1865 masterSM(sc,mcT0Send); 1866 break; 1867 1868 default: 1869 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1870 break; 1871 } 1872 break; 1873 1874 default: 1875 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1876 break; 1877 } 1878 } 1879 1880 1881 1882 /* 1883 **++ 1884 ** FUNCTIONAL DESCRIPTION: 1885 ** 1886 ** t0RecvSM 1887 ** 1888 ** This is the T=0 Recv State Machine. It is responsible 1889 ** for performing the recv part of the ISO 7816-3 T=0 1890 ** protocol. It is mid level protocol state machine. 1891 ** 1892 ** Once started, this machine is driven entirely via the 1893 ** FIQ/timeout structure . 1894 ** 1895 ** FORMAL PARAMETERS: 1896 ** 1897 ** sc - Pointer to the softc structure. 1898 ** cmd - command to this machine 1899 ** 1900 ** IMPLICIT INPUTS: 1901 ** 1902 ** sc->t0RecvS state of this machine 1903 ** sc->pIoctlT0->command command to send to card 1904 ** 1905 ** IMPLICIT OUTPUTS: 1906 ** 1907 ** sc->pIoctlT0->data data from card 1908 ** sc->pIoctlT0->dataLen size of data from card 1909 ** sc->pIoctlT0->sw1 command status from card 1910 ** sc->pIoctlT0->sw2 command status from card 1911 ** sc->status error status from this machine 1912 ** 1913 ** FUNCTION VALUE: 1914 ** 1915 ** nill 1916 ** 1917 ** SIDE EFFECTS: 1918 ** 1919 ** nill 1920 **-- 1921 */ 1922 static void t0RecvSM (struct scr_softc * sc,int cmd) 1923 { 1924 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1925 1926 /* 1927 ** check for major failures that are common to most states 1928 */ 1929 if (cmd == t0rcTWorkWaiting || 1930 cmd == gcT0RecvByteErr || 1931 cmd == gcT0SendByteErr ) 1932 1933 { 1934 switch(cmd) 1935 { 1936 1937 case t0rcTWorkWaiting: 1938 ASSERT(sc->t0RecvS != t0rsIdle); 1939 1940 /* kill all lower level machines */ 1941 t0SendByteSM(sc,t0sbcAbort); 1942 t0RecvByteSM(sc,t0rbcAbort); 1943 1944 /* set status */ 1945 sc->status = ERROR_WORK_WAITING; 1946 break; 1947 1948 case gcT0RecvByteErr: // fall through 1949 case gcT0SendByteErr: 1950 /* kill all the timers */ 1951 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 1952 break; 1953 1954 default: 1955 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 1956 break; 1957 1958 } 1959 1960 1961 1962 /* change state */ 1963 sc->t0RecvS = t0rsIdle; 1964 masterSM(sc,mcT0Recv); 1965 1966 /* all done */ 1967 return; 1968 } 1969 1970 switch (sc->t0RecvS) 1971 { 1972 case t0rsIdle: 1973 switch (cmd) 1974 { 1975 case t0rcStart: 1976 /* set initial values */ 1977 sc->t0RecvS = t0rsSendHeader; 1978 sc->t0ByteParent = t0RecvSM; 1979 sc->commandCount = 0; 1980 sc->dataCount = 0; 1981 sc->dataMax = sc->pIoctlT0->command[CMD_BUF_DATA_LEN_OFF]; 1982 if (sc->dataMax == 0) 1983 { 1984 sc->dataMax = 256; 1985 } 1986 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1987 t0SendByteSM(sc,t0sbcStart); 1988 break; 1989 1990 default: 1991 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 1992 break; 1993 } 1994 break; 1995 1996 case t0rsSendHeader: 1997 switch (cmd) 1998 { 1999 case gcT0SendByte: 2000 sc->commandCount++; 2001 if (sc->commandCount < CMD_BUF_LEN) 2002 { 2003 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 2004 t0SendByteSM(sc,t0sbcStart); 2005 } 2006 else 2007 { 2008 ASSERT(sc->commandCount == CMD_BUF_LEN); 2009 2010 sc->t0RecvS = t0rsRecvProcedure; 2011 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2012 t0RecvByteSM(sc,t0rbcStart); 2013 } 2014 break; 2015 2016 default: 2017 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2018 break; 2019 } 2020 break; 2021 2022 case t0rsRecvProcedure: 2023 switch (cmd) 2024 { 2025 case gcT0RecvByte: 2026 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2027 2028 /* see if we should recv all remaining bytes */ 2029 if ( (sc->dataByte == sc->pIoctlT0->command[CMD_BUF_INS_OFF]) || 2030 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0x01)) ) 2031 { 2032 ASSERT(sc->dataCount < sc->dataMax); 2033 2034 sc->t0RecvS = t0rsRecvData; 2035 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2036 t0RecvByteSM(sc,t0rbcStart); 2037 } 2038 2039 /* see if we should send one data byte */ 2040 else if ((sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFF)) || 2041 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFE)) ) 2042 { 2043 ASSERT(sc->dataCount < sc->dataMax); 2044 sc->t0RecvS = t0rsRecvByte; 2045 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2046 t0RecvByteSM(sc,t0rbcStart); 2047 } 2048 2049 /* see if we should extend the work waiting period */ 2050 else if (sc->dataByte == 0x60) 2051 { 2052 t0RecvByteSM(sc,t0rbcStart); 2053 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2054 } 2055 2056 #ifdef ORIGINAL_SW1_CODE /* XXX XXX XXX cgd */ 2057 /* see if we have a SW1 byte */ 2058 else if ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) 2059 && 2060 sc->dataByte != 0x60) 2061 #else /* XXX XXX XXX cgd */ 2062 /* see if we have a SW1 byte */ 2063 else if ( ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) ) 2064 && 2065 sc->dataByte != 0x60) 2066 #endif /* XXX XXX XXX cgd */ 2067 { 2068 sc->pIoctlT0->sw1 = sc->dataByte; 2069 sc->t0RecvS = t0rsRecvSW2; 2070 t0RecvByteSM(sc,t0rbcStart); 2071 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2072 } 2073 2074 /* got bad data byte, log error and get out */ 2075 else 2076 { 2077 sc->status = ERROR_BAD_PROCEDURE_BYTE; 2078 2079 /* change state */ 2080 sc->t0RecvS = t0rsIdle; 2081 masterSM(sc,mcT0Recv); 2082 } 2083 break; 2084 2085 default: 2086 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2087 break; 2088 } 2089 break; 2090 2091 case t0rsRecvByte: 2092 switch (cmd) 2093 { 2094 case gcT0RecvByte: 2095 /* clock in byte */ 2096 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2097 sc->pIoctlT0->data[sc->dataCount] = sc->dataByte; 2098 sc->dataCount++; 2099 2100 2101 if (sc->dataCount < sc->dataMax) 2102 { 2103 /* get procedure byte */ 2104 sc->t0RecvS = t0rsRecvProcedure; 2105 } 2106 2107 else 2108 { 2109 ASSERT(sc->dataCount == sc->dataMax); 2110 sc->t0RecvS = t0rsRecvSW1; 2111 } 2112 2113 // ask for another byte 2114 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2115 t0RecvByteSM(sc,t0rbcStart); 2116 break; 2117 2118 default: 2119 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2120 break; 2121 } 2122 break; 2123 2124 case t0rsRecvData: 2125 switch (cmd) 2126 { 2127 case gcT0RecvByte: 2128 /* clock in data */ 2129 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2130 sc->pIoctlT0->data[sc->dataCount] = sc->dataByte; 2131 sc->dataCount++; 2132 2133 /* decide if we have all data */ 2134 if (sc->dataCount >= sc->dataMax) 2135 { 2136 KERN_DEBUG (scrdebug, T0_RECV_SM_DEBUG_INFO,("\t\tt0RecvSM: changing state to t0rsRecvSW1\n")); 2137 ASSERT(sc->dataCount == sc->dataMax); 2138 sc->t0RecvS = t0rsRecvSW1; 2139 } 2140 2141 /* ask for another byte */ 2142 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2143 t0RecvByteSM(sc,t0rbcStart); 2144 break; 2145 2146 default: 2147 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2148 break; 2149 } 2150 break; 2151 2152 case t0rsRecvSW1: 2153 switch (cmd) 2154 { 2155 case gcT0RecvByte: 2156 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2157 sc->pIoctlT0->sw1 = sc->dataByte; 2158 2159 sc->t0RecvS = t0rsRecvSW2; 2160 t0RecvByteSM(sc,t0rbcStart); 2161 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2162 break; 2163 default: 2164 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2165 break; 2166 } 2167 break; 2168 2169 case t0rsRecvSW2: 2170 switch (cmd) 2171 { 2172 case gcT0RecvByte: 2173 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2174 sc->pIoctlT0->sw2 = sc->dataByte; 2175 2176 sc->t0RecvS = t0rsIdle; 2177 masterSM(sc,mcT0Recv); 2178 break; 2179 2180 default: 2181 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2182 break; 2183 } 2184 break; 2185 2186 default: 2187 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2188 break; 2189 } 2190 } 2191 2192 2193 /* 2194 **++ 2195 ** FUNCTIONAL DESCRIPTION: 2196 ** 2197 ** coldResetSM 2198 ** 2199 ** This state machine switches on the power, clock and reset pins 2200 ** in the correct order/timing. 2201 ** It is a low level bit-bashing state machine. 2202 ** 2203 ** 2204 ** FORMAL PARAMETERS: 2205 ** 2206 ** sc - Pointer to the softc structure. 2207 ** cmd - command to this machine 2208 ** 2209 ** IMPLICIT INPUTS: 2210 ** 2211 ** sc->coldResetS state of this machine 2212 ** 2213 ** IMPLICIT OUTPUTS: 2214 ** 2215 ** nill 2216 ** 2217 ** FUNCTION VALUE: 2218 ** 2219 ** nill 2220 ** 2221 ** SIDE EFFECTS: 2222 ** 2223 ** signals to card are on 2224 **-- 2225 */ 2226 static void coldResetSM(struct scr_softc * sc,int cmd) 2227 { 2228 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2229 2230 switch (sc->coldResetS) 2231 { 2232 case crsIdle: 2233 switch (cmd) 2234 { 2235 case crcStart: 2236 scrSetReset(true); 2237 scrSetClock(true); 2238 scrSetDataHighZ(); 2239 scrSetPower(true); 2240 2241 /* start a t2 timer */ 2242 scrTimeout(coldResetSM,sc,crcT2,T_t2); 2243 sc->coldResetS = crsT2Wait; 2244 break; 2245 2246 default: 2247 INVALID_STATE_CMD(sc,sc->masterS,cmd); 2248 break; 2249 } 2250 break; 2251 2252 case crsT2Wait: 2253 switch (cmd) 2254 { 2255 case crcT2: 2256 /* turn off rst */ 2257 scrSetReset(false); 2258 2259 /* tell master state machine that we are all done */ 2260 sc->coldResetS = crsIdle; 2261 masterSM(sc,mcColdReset); 2262 break; 2263 2264 default: 2265 INVALID_STATE_CMD(sc,sc->masterS,cmd); 2266 break; 2267 } 2268 break; 2269 2270 2271 default: 2272 INVALID_STATE_CMD(sc,sc->coldResetS,cmd); 2273 break; 2274 } 2275 } 2276 2277 /* 2278 **++ 2279 ** FUNCTIONAL DESCRIPTION: 2280 ** 2281 ** ATRSM 2282 ** 2283 ** This is the Answer To Reset State Machine. It is responsible 2284 ** for performing the Answer To Reset as specified in ISO 7816-3. 2285 ** It is mid level protocol state machine. 2286 ** 2287 ** Once started, this machine is driven entirely via the 2288 ** FIQ/timeout structure. 2289 ** 2290 ** 2291 ** During the first byte, we have to check if the card is operating 2292 ** at full speed or half speed. The first couple of bits are 2293 ** checked to see if it is 1/2 speed, and if so, the clock is changed 2294 ** and the state adjustes 2295 ** 2296 ** At the end of the first byte we have to determin the logic being 2297 ** used by the card, ie is it active high/low and msb/lsb. 2298 ** 2299 ** 2300 ** FORMAL PARAMETERS: 2301 ** 2302 ** sc - Pointer to the softc structure. 2303 ** cmd - command to this machine 2304 ** 2305 ** IMPLICIT INPUTS: 2306 ** 2307 ** sc->pIoctlAtr->atr data from card 2308 ** sc->pIoctlT0->sw1 command status from card 2309 ** sc->pIoctlT0->sw2 command status from card 2310 ** sc->status error status from this machine 2311 ** 2312 ** IMPLICIT OUTPUTS: 2313 ** 2314 ** sc->pIoctlOn->atrBuf data from ATR sequence 2315 ** sc->pIoctlOn->atrLen size of data from ATR sequence 2316 ** sc->status error status from this machine 2317 ** 2318 ** 2319 ** FUNCTION VALUE: 2320 ** 2321 ** nill 2322 ** 2323 ** SIDE EFFECTS: 2324 ** 2325 ** nill 2326 **-- 2327 */ 2328 static void ATRSM (struct scr_softc * sc,int cmd) 2329 { 2330 int lc; 2331 int tck; 2332 2333 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2334 2335 /* 2336 ** check for major failures that are common to most states 2337 */ 2338 if (cmd == atrcT3 || 2339 cmd == atrcTWorkWaiting || 2340 cmd == gcT0RecvByteErr 2341 ) 2342 { 2343 switch(cmd) 2344 { 2345 case atrcT3: 2346 scrUntimeout (ATRSM,sc,atrcTWorkWaiting); 2347 sc->status = ERROR_ATR_T3; 2348 t0RecvByteSM(sc,t0rbcAbort); 2349 break; 2350 2351 case atrcTWorkWaiting: 2352 scrUntimeout (ATRSM,sc,atrcT3); 2353 sc->status = ERROR_WORK_WAITING; 2354 t0RecvByteSM(sc,t0rbcAbort); 2355 break; 2356 2357 case gcT0RecvByteErr: 2358 scrUntimeout (ATRSM,sc,atrcT3); 2359 scrUntimeout (ATRSM,sc,atrcTWorkWaiting); 2360 /* done set status, its already set */ 2361 break; 2362 2363 default: 2364 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2365 break; 2366 } 2367 2368 /* change state */ 2369 sc->ATRS = atrsIdle; 2370 masterSM(sc,mcATR); 2371 return; 2372 } 2373 2374 switch (sc->ATRS) 2375 { 2376 case atrsIdle: 2377 switch (cmd) 2378 { 2379 case atrcStart: 2380 /* lets start looking */ 2381 sc->ATRS = atrsTS; 2382 sc->pIoctlOn->atrLen = 0; 2383 sc->t0ByteParent = ATRSM; 2384 scrTimeout(ATRSM,sc,atrcT3,T_t3 *2); /* by 2 to accommodate 1/2 freq cards */ 2385 t0RecvByteSM(sc,t0rbcStart); 2386 break; 2387 2388 default: 2389 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2390 break; 2391 } 2392 break; 2393 2394 case atrsTS: 2395 switch (cmd) 2396 { 2397 case gcT0RecvByte: 2398 scrUntimeout(ATRSM,sc,atrcT3); 2399 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2400 sc->pIoctlOn->atrLen++; 2401 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2402 { 2403 #ifdef SCR_DEBUG 2404 DEBUGGER; 2405 #endif 2406 sc->status = ERROR_ATR_TCK; 2407 sc->ATRS = atrsIdle; 2408 masterSM(sc,mcATR); 2409 } 2410 else 2411 { 2412 /* move onto recv T0 */ 2413 sc->ATRS = atrsT0; 2414 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2415 t0RecvByteSM(sc,t0rbcStart); 2416 } 2417 break; 2418 2419 default: 2420 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2421 break; 2422 } 2423 break; 2424 2425 case atrsT0: 2426 switch (cmd) 2427 { 2428 case gcT0RecvByte: 2429 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2430 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2431 sc->pIoctlOn->atrLen++; 2432 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2433 { 2434 #ifdef SCR_DEBUG 2435 printf("atrLen >= ATR_BUF_MAX\n"); 2436 DEBUGGER; 2437 #endif 2438 sc->status = ERROR_ATR_TCK; 2439 sc->ATRS = atrsIdle; 2440 masterSM(sc,mcATR); 2441 } 2442 else 2443 { 2444 /* store Y & K */ 2445 sc->atrY = sc->dataByte & 0xf0; 2446 sc->atrK = sc->dataByte & 0x0f; 2447 2448 sc->atrTABCDx = 1; 2449 sc->atrKCount = 1; 2450 2451 /* if there are no TDx following set T0 protocol */ 2452 if (!ISSET(sc->atrY,ATR_Y_TD)) 2453 { 2454 sc->protocolType = PROTOCOL_T0; 2455 } 2456 2457 2458 if (sc->atrY) 2459 { 2460 2461 sc->ATRS = atrsTABCD; 2462 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2463 t0RecvByteSM(sc,t0rbcStart); 2464 } 2465 2466 else if (sc->atrK) 2467 { 2468 sc->ATRS = atrsTK; 2469 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2470 t0RecvByteSM(sc,t0rbcStart); 2471 } 2472 2473 else if (sc->protocolType != PROTOCOL_T0) 2474 { 2475 sc->ATRS = atrsTCK; 2476 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2477 t0RecvByteSM(sc,t0rbcStart); 2478 } 2479 2480 else /* got all of ATR */ 2481 { 2482 sc->ATRS = atrsIdle; 2483 masterSM(sc,mcATR); 2484 } 2485 } 2486 break; 2487 2488 2489 default: 2490 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2491 break; 2492 } 2493 break; 2494 2495 2496 case atrsTABCD: 2497 switch (cmd) 2498 { 2499 case gcT0RecvByte: 2500 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2501 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2502 sc->pIoctlOn->atrLen++; 2503 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2504 { 2505 #ifdef SCR_DEBUG 2506 printf("atrLen >= ATR_BUF_MAX\n"); 2507 DEBUGGER; 2508 #endif 2509 sc->status = ERROR_ATR_TCK; 2510 sc->ATRS = atrsIdle; 2511 masterSM(sc,mcATR); 2512 } 2513 else 2514 { 2515 if (sc->atrY & ATR_Y_TA) 2516 { 2517 sc->atrY &= ~ATR_Y_TA; 2518 if (sc->atrTABCDx == 1) 2519 { 2520 sc->Fi = FI2Fi[((sc->dataByte >> 4) & 0x0f)]; 2521 if (sc->Fi == 0) 2522 { 2523 sc->status = ERROR_ATR_FI_INVALID; 2524 sc->Fi = Fi_DEFAULT; 2525 } 2526 2527 sc->Di = DI2Di[(sc->dataByte & 0x0f)]; 2528 if (sc->Di == 0) 2529 { 2530 sc->status = ERROR_ATR_DI_INVALID; 2531 sc->Di = Di_DEFAULT; 2532 } 2533 2534 } 2535 } 2536 2537 else if (sc->atrY & ATR_Y_TB) 2538 { 2539 sc->atrY &= ~ATR_Y_TB; 2540 } 2541 2542 else if (sc->atrY & ATR_Y_TC) 2543 { 2544 sc->atrY &= ~ATR_Y_TC; 2545 if (sc->atrTABCDx == 1) 2546 { 2547 sc->N = sc->dataByte; 2548 } 2549 2550 if (sc->atrTABCDx == 2) 2551 { 2552 sc->Wi = sc->dataByte; 2553 } 2554 } 2555 2556 else 2557 { 2558 ASSERT(sc->atrY & ATR_Y_TD); 2559 sc->atrY &= ~ATR_Y_TD; 2560 2561 /* copy across the y section of TD */ 2562 sc->atrY = sc->dataByte; 2563 sc->atrY &= 0xf0; 2564 2565 /* step to the next group of TABCD */ 2566 sc->atrTABCDx++; 2567 2568 /* store protocols */ 2569 sc->protocolType = (1 << (sc->dataByte &0x0f)); 2570 } 2571 2572 2573 /* see what we should do next */ 2574 if (sc->atrY) 2575 { 2576 /* just stay in the same state */ 2577 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2578 t0RecvByteSM(sc,t0rbcStart); 2579 } 2580 2581 else if (sc->atrK) 2582 { 2583 sc->ATRS = atrsTK; 2584 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2585 t0RecvByteSM(sc,t0rbcStart); 2586 } 2587 2588 else if (sc->protocolType != PROTOCOL_T0) 2589 { 2590 sc->ATRS = atrsTCK; 2591 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2592 t0RecvByteSM(sc,t0rbcStart); 2593 } 2594 2595 else /* got all of ATR */ 2596 { 2597 sc->ATRS = atrsIdle; 2598 masterSM(sc,mcATR); 2599 } 2600 } 2601 2602 break; 2603 2604 2605 default: 2606 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2607 break; 2608 } 2609 break; 2610 2611 case atrsTK: 2612 switch (cmd) 2613 { 2614 case gcT0RecvByte: 2615 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2616 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2617 sc->pIoctlOn->atrLen++; 2618 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2619 { 2620 #ifdef SCR_DEBUG 2621 printf("atrLen >= ATR_BUF_MAX\n"); 2622 DEBUGGER; 2623 #endif 2624 sc->status = ERROR_ATR_TCK; 2625 sc->ATRS = atrsIdle; 2626 masterSM(sc,mcATR); 2627 } 2628 else 2629 { 2630 2631 if (sc->atrKCount < sc->atrK) 2632 { 2633 sc->atrKCount++; 2634 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2635 t0RecvByteSM(sc,t0rbcStart); 2636 } 2637 2638 2639 else if (sc->protocolType != PROTOCOL_T0) 2640 { 2641 sc->ATRS = atrsTCK; 2642 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2643 t0RecvByteSM(sc,t0rbcStart); 2644 } 2645 2646 else /* got all of ATR */ 2647 { 2648 sc->ATRS = atrsIdle; 2649 masterSM(sc,mcATR); 2650 } 2651 } 2652 break; 2653 2654 default: 2655 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2656 break; 2657 } 2658 break; 2659 2660 case atrsTCK: 2661 switch (cmd) 2662 { 2663 case gcT0RecvByte: 2664 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2665 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2666 sc->pIoctlOn->atrLen++; 2667 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2668 { 2669 #ifdef SCR_DEBUG 2670 printf("atrLen >= ATR_BUF_MAX\n"); 2671 DEBUGGER; 2672 #endif 2673 sc->status = ERROR_ATR_TCK; 2674 sc->ATRS = atrsIdle; 2675 masterSM(sc,mcATR); 2676 } 2677 else 2678 { 2679 tck = 0; 2680 for (lc = 1; lc < sc->pIoctlOn->atrLen-1; lc++) 2681 { 2682 tck ^= sc->pIoctlOn->atrBuf[lc]; 2683 } 2684 2685 if (tck == sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen-1]) 2686 { 2687 sc->ATRS = atrsIdle; 2688 masterSM(sc,mcATR); 2689 } 2690 else 2691 { 2692 sc->status = ERROR_ATR_TCK; 2693 sc->ATRS = atrsIdle; 2694 masterSM(sc,mcATR); 2695 } 2696 } 2697 break; 2698 2699 default: 2700 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2701 break; 2702 } 2703 break; 2704 2705 2706 2707 default: 2708 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2709 break; 2710 } 2711 } 2712 2713 2714 2715 /* 2716 **++ 2717 ** FUNCTIONAL DESCRIPTION: 2718 ** 2719 ** t0RecvByteSM 2720 ** 2721 ** This state machine attempts to read 1 byte from a card. 2722 ** It is a low level bit-bashing state machine. 2723 ** 2724 ** Data from the card is async, so the machine scans at 2725 ** 5 times the data rate looking for a state bit. Once 2726 ** a start bit has been found, it waits for the middle of 2727 ** the bit and starts sampling at the bit rate. 2728 ** 2729 ** Several mid level machines can use this machine, so the value 2730 ** sc->t0ByteParent is used to point to back to the mid level machine 2731 ** 2732 ** 2733 ** FORMAL PARAMETERS: 2734 ** 2735 ** sc - Pointer to the softc structure. 2736 ** cmd - command to this machine 2737 ** 2738 ** IMPLICIT INPUTS: 2739 ** 2740 ** sc->t0RecvByteS state of this machine 2741 ** sc->t0ByteParent mid level machine that started this machine 2742 ** 2743 ** IMPLICIT OUTPUTS: 2744 ** 2745 ** sc->shiftByte byte read from the card 2746 ** sc->status error value if could not read byte 2747 ** 2748 ** FUNCTION VALUE: 2749 ** 2750 ** nill 2751 ** 2752 ** SIDE EFFECTS: 2753 ** 2754 ** nill 2755 **-- 2756 */ 2757 static void t0RecvByteSM(struct scr_softc* sc,int cmd) 2758 { 2759 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2760 2761 if (cmd == t0rbcAbort) 2762 { 2763 /* kill all the timers */ 2764 scrUntimeout(t0RecvByteSM, sc,t0rbcTFindStartEdge); 2765 scrUntimeout(t0RecvByteSM, sc,t0rbcTFindStartMid); 2766 scrUntimeout(t0RecvByteSM, sc,t0rbcTClockData); 2767 scrUntimeout(t0RecvByteSM, sc,t0rbcTErrorStart); 2768 scrUntimeout(t0RecvByteSM, sc,t0rbcTErrorStop); 2769 2770 scrSetDataHighZ(); 2771 sc->t0RecvByteS = t0rbsIdle; 2772 return; 2773 } 2774 2775 2776 switch (sc->t0RecvByteS) 2777 { 2778 case t0rbsIdle: 2779 switch (cmd) 2780 { 2781 case t0rbcStart: 2782 /* set initial conditions */ 2783 sc->shiftBits = 0; 2784 sc->shiftByte = 0; 2785 sc->shiftParity = 0; 2786 sc->shiftParityCount = 0; 2787 scrClkAdj(sc->clkCountStartRecv); /* recv data clock running at 5 times */ 2788 2789 /* check if start bit is already here */ 2790 //if (scrGetData()) 2791 if (1) 2792 { 2793 /* didn't find it, keep looking */ 2794 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 2795 sc->t0RecvByteS = t0rbsFindStartEdge; 2796 } 2797 else 2798 { 2799 /* found start bit, look for mid bit */ 2800 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartMid,sc->clkCountStartRecv); 2801 sc->t0RecvByteS = t0rbsFindStartMid; 2802 } 2803 break; 2804 2805 2806 2807 default: 2808 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 2809 break; 2810 } 2811 break; 2812 2813 2814 case t0rbsFindStartEdge: 2815 switch (cmd) 2816 { 2817 case t0rbcTFindStartEdge: 2818 if (scrGetData()) 2819 { 2820 /* didn't find it, keep looking */ 2821 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 2822 } 2823 else 2824 { 2825 /* found start bit, look for mid bit */ 2826 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartMid,sc->clkCountStartRecv * 2); 2827 sc->t0RecvByteS = t0rbsFindStartMid; 2828 } 2829 break; 2830 2831 2832 default: 2833 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 2834 break; 2835 } 2836 break; 2837 2838 case t0rbsFindStartMid: 2839 switch (cmd) 2840 { 2841 case t0rbcTFindStartMid: 2842 if (scrGetData()) 2843 { 2844 /* found glitch, so just go back to hunting */ 2845 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 2846 sc->t0RecvByteS = t0rbsFindStartEdge; 2847 } 2848 else 2849 { 2850 /* found start bit, start clocking in data */ 2851 TOGGLE_TEST_PIN(); 2852 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 2853 sc->t0RecvByteS = t0rbsClockData; 2854 } 2855 break; 2856 2857 2858 default: 2859 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 2860 break; 2861 } 2862 break; 2863 2864 2865 case t0rbsClockData: 2866 TOGGLE_TEST_PIN(); 2867 switch (cmd) 2868 { 2869 case t0rbcTClockData: 2870 if (sc->shiftBits < 8) 2871 { 2872 if (sc->convention == CONVENTION_INVERSE || 2873 sc->convention == CONVENTION_UNKNOWN) 2874 { 2875 /* logic 1 is low, msb is first */ 2876 sc->shiftByte <<= 1; 2877 sc->shiftByte &= 0xfe; 2878 if (!scrGetData()) 2879 { 2880 sc->shiftByte |= 0x01; 2881 sc->shiftParity++; 2882 } 2883 } 2884 else 2885 { 2886 ASSERT(sc->convention == CONVENTION_DIRECT); 2887 /* logic 1 is high, lsb is first */ 2888 sc->shiftByte = sc->shiftByte >> 1; 2889 sc->shiftByte &= 0x7f; 2890 if (scrGetData()) 2891 { 2892 sc->shiftParity++; 2893 sc->shiftByte |= 0x80; 2894 } 2895 } 2896 sc->shiftBits++; 2897 2898 2899 /* in TS byte, check if we have a card that works at 1/2 freq */ 2900 if (sc->convention == CONVENTION_UNKNOWN && /* in TS byte */ 2901 sc->shiftBits == 3 && /* test at bit 3 in word */ 2902 sc->shiftByte == 4 && /* check for 1/2 freq pattern */ 2903 sc->cardFreq == CARD_FREQ_DEF) /* only do this if at full freq */ 2904 { 2905 /* adjust counts down to 1/2 freq */ 2906 sc->cardFreq = CARD_FREQ_DEF / 2; 2907 sc->clkCountStartRecv = sc->clkCountStartRecv *2; 2908 sc->clkCountDataRecv = sc->clkCountDataRecv *2; 2909 sc->clkCountDataSend = sc->clkCountDataSend *2; 2910 2911 2912 /* adjust this so that we have clocked in only fist bit of TS */ 2913 sc->shiftParity = 0; 2914 sc->shiftByte = 0; 2915 sc->shiftBits = 1; 2916 2917 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,(sc->clkCountDataRecv * 3) /4); 2918 } 2919 else 2920 { 2921 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 2922 } 2923 } 2924 2925 /* clock in parity bit */ 2926 else if (sc->shiftBits == 8) 2927 { 2928 if (sc->convention == CONVENTION_INVERSE) 2929 { 2930 if (!scrGetData()) 2931 { 2932 sc->shiftParity++; 2933 } 2934 } 2935 else if (sc->convention == CONVENTION_DIRECT) 2936 { 2937 if (scrGetData()) 2938 { 2939 sc->shiftParity++; 2940 } 2941 } 2942 2943 2944 else 2945 { 2946 /* sc->convention not set so sort it out */ 2947 ASSERT(sc->convention == CONVENTION_UNKNOWN); 2948 if (sc->shiftByte == CONVENIONT_INVERSE_ID && scrGetData()) 2949 { 2950 sc->convention = CONVENTION_INVERSE; 2951 sc->shiftParity = 0; /* force good parity */ 2952 } 2953 2954 else if (sc->shiftByte == CONVENTION_DIRECT_ID && scrGetData()) 2955 { 2956 sc->shiftByte = CONVENTION_DIRECT_FIX; 2957 sc->convention = CONVENTION_DIRECT; 2958 sc->shiftParity = 0; /* force good parity */ 2959 } 2960 2961 else 2962 { 2963 sc->shiftParity = 1; /* force bad parity */ 2964 } 2965 } 2966 2967 2968 if ((sc->shiftParity & 01) == 0) 2969 { 2970 sc->shiftBits++; 2971 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 2972 } 2973 else 2974 { 2975 /* got parity error */ 2976 if (sc->shiftParityCount < PARITY_ERROR_MAX) 2977 { 2978 sc->shiftParityCount++; 2979 scrTimeout(t0RecvByteSM,sc,t0rbcTErrorStart,sc->clkCountDataRecv); 2980 sc->t0RecvByteS = t0rbsSendError; 2981 } 2982 else 2983 2984 { 2985 /* too many parity errors, just give up on this sc->dataByte */ 2986 sc->status = ERROR_PARITY; 2987 sc->t0RecvByteS = t0rbsIdle; 2988 sc->t0ByteParent(sc,gcT0RecvByteErr); 2989 } 2990 } 2991 } 2992 2993 else 2994 { 2995 sc->dataByte = sc->shiftByte; 2996 sc->t0RecvByteS = t0rbsIdle; 2997 sc->t0ByteParent(sc,gcT0RecvByte); 2998 } 2999 break; 3000 3001 default: 3002 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3003 break; 3004 } 3005 break; 3006 3007 3008 case t0rbsSendError: 3009 TOGGLE_TEST_PIN(); 3010 switch (cmd) 3011 { 3012 case t0rbcTErrorStart: 3013 /* start sending error bit */ 3014 scrSetData(false); 3015 scrTimeout(t0RecvByteSM,sc,t0rbcTErrorStop,sc->clkCountDataRecv * 2); 3016 break; 3017 3018 case t0rbcTErrorStop: 3019 /* stop sending parity error & reset information*/ 3020 scrSetData(true); 3021 sc->shiftBits = 0; 3022 sc->shiftByte = 0; 3023 sc->shiftParity = 0; 3024 3025 /* start looking for start bit */ 3026 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,1); 3027 sc->t0RecvByteS = t0rbsFindStartEdge; 3028 break; 3029 3030 default: 3031 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3032 break; 3033 } 3034 break; 3035 3036 3037 default: 3038 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3039 break; 3040 } 3041 } 3042 3043 /* 3044 **++ 3045 ** FUNCTIONAL DESCRIPTION: 3046 ** 3047 ** t0SendByteSM 3048 ** 3049 ** This state machine writes 1 byte to a card. 3050 ** It is a low level bit-bashing state machine. 3051 ** 3052 ** 3053 ** Several mid level machines can use this machine, so the value 3054 ** sc->t0ByteParent is used to point to back to the mid level machine 3055 ** 3056 ** FORMAL PARAMETERS: 3057 ** 3058 ** sc - Pointer to the softc structure. 3059 ** cmd - command to this machine 3060 ** 3061 ** IMPLICIT INPUTS: 3062 ** 3063 ** sc->t0SendByteS state of this machine 3064 ** sc->shiftByte byte to write to the card 3065 ** 3066 ** IMPLICIT OUTPUTS: 3067 ** 3068 ** sc->status error value if could not read byte 3069 ** 3070 ** FUNCTION VALUE: 3071 ** 3072 ** nill 3073 ** 3074 ** SIDE EFFECTS: 3075 ** 3076 ** nill 3077 **-- 3078 */ 3079 //int bigTroubleTest = 0; 3080 static void t0SendByteSM (struct scr_softc * sc,int cmd) 3081 { 3082 //if(bigTroubleTest == 2000) 3083 //{ 3084 // INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3085 // bigTroubleTest = 0; 3086 //} 3087 // 3088 //bigTroubleTest++; 3089 3090 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 3091 3092 if (cmd == t0sbcAbort) 3093 { 3094 /* kill all the timers */ 3095 scrUntimeout(t0SendByteSM, sc, t0sbcTGuardTime); 3096 scrUntimeout(t0SendByteSM, sc, t0sbcTClockData); 3097 scrUntimeout(t0SendByteSM, sc, t0sbcTError); 3098 3099 scrSetDataHighZ(); 3100 return; 3101 } 3102 3103 3104 switch (sc->t0SendByteS) 3105 { 3106 case t0sbsIdle: 3107 switch (cmd) 3108 { 3109 case t0sbcStart: 3110 /* set initial conditions */ 3111 sc->shiftBits = 0; 3112 sc->shiftParity = 0; 3113 sc->shiftParityCount = 0; 3114 sc->shiftByte = sc->dataByte; 3115 3116 scrClkAdj(sc->clkCountDataSend); /* send data clock running at 1 ETU */ 3117 3118 /* check if we have to wait for guard time */ 3119 if (0) /* possible optimization here */ 3120 { 3121 /* can send start bit now */ 3122 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3123 scrSetData(false); 3124 sc->t0SendByteS = t0sbsClockData; 3125 } 3126 else 3127 { 3128 /* need to wait for guard time */ 3129 scrTimeout(t0SendByteSM,sc,t0sbcTGuardTime,sc->clkCountDataSend * (12 + sc->N)); 3130 sc->t0SendByteS = t0sbsWaitGuardTime; 3131 3132 } 3133 break; 3134 3135 default: 3136 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3137 break; 3138 } 3139 break; 3140 3141 3142 case t0sbsWaitGuardTime: 3143 switch (cmd) 3144 { 3145 case t0sbcTGuardTime: 3146 TOGGLE_TEST_PIN(); 3147 /* set start bit */ 3148 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3149 scrSetData(false); 3150 sc->t0SendByteS = t0sbsClockData; 3151 break; 3152 3153 default: 3154 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3155 break; 3156 } 3157 break; 3158 3159 3160 case t0sbsClockData: 3161 switch (cmd) 3162 { 3163 case t0sbcTClockData: 3164 TOGGLE_TEST_PIN(); 3165 /* clock out data bit */ 3166 if (sc->shiftBits < 8) 3167 { 3168 if (sc->convention == CONVENTION_INVERSE) 3169 { 3170 if (sc->shiftByte & 0x80) 3171 { 3172 scrSetData(false); 3173 sc->shiftParity++; 3174 } 3175 else 3176 { 3177 scrSetData(true); 3178 } 3179 sc->shiftByte = sc->shiftByte << 1; 3180 } 3181 else 3182 { 3183 ASSERT(sc->convention == CONVENTION_DIRECT); 3184 if (sc->shiftByte & 0x01) 3185 { 3186 scrSetData(true); 3187 sc->shiftParity++; 3188 } 3189 else 3190 { 3191 scrSetData(false); 3192 } 3193 sc->shiftByte = sc->shiftByte >> 1; 3194 } 3195 sc->shiftBits++; 3196 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3197 } 3198 3199 /* clock out parity bit */ 3200 else if (sc->shiftBits == 8) 3201 { 3202 if ( ((sc->shiftParity & 0x01) && (sc->convention == CONVENTION_INVERSE)) || 3203 (!(sc->shiftParity & 0x01) && (sc->convention == CONVENTION_DIRECT)) ) 3204 { 3205 scrSetData(false); 3206 } 3207 else 3208 { 3209 scrSetData(true); 3210 } 3211 sc->shiftBits++; 3212 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3213 } 3214 3215 /* all data shifted out, move onto next state */ 3216 else 3217 { 3218 ASSERT(sc->shiftBits > 8); 3219 scrSetData(true); 3220 scrTimeout(t0SendByteSM,sc,t0sbcTError,sc->clkCountDataSend); 3221 sc->t0SendByteS = t0sbsWaitError; 3222 } 3223 break; 3224 3225 default: 3226 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3227 break; 3228 } 3229 break; 3230 3231 case t0sbsWaitError: 3232 switch (cmd) 3233 { 3234 case t0sbcTError: 3235 /* no error indicated*/ 3236 if (scrGetData()) 3237 { 3238 sc->t0SendByteS = t0sbsIdle; 3239 sc->t0ByteParent(sc,gcT0SendByte); 3240 } 3241 3242 /* got error */ 3243 else 3244 { 3245 /* got parity error */ 3246 if (sc->shiftParityCount < PARITY_ERROR_MAX) 3247 { 3248 sc->shiftParityCount++; 3249 scrTimeout(t0SendByteSM,sc,t0sbcTResend,sc->clkCountDataSend * 2); 3250 sc->t0SendByteS = t0sbsWaitResend; 3251 } 3252 else 3253 { 3254 /* too many parity errors, just give up on this sc->dataByte */ 3255 sc->status = ERROR_PARITY; 3256 sc->t0SendByteS = t0sbsIdle; 3257 sc->t0ByteParent(sc,gcT0SendByteErr); 3258 } 3259 } 3260 break; 3261 3262 default: 3263 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3264 break; 3265 } 3266 break; 3267 3268 case t0sbsWaitResend: 3269 switch (cmd) 3270 { 3271 case t0sbcTResend: 3272 sc->shiftBits = 0; 3273 sc->shiftParity = 0; 3274 sc->shiftByte = sc->dataByte; 3275 /* set start bit */ 3276 3277 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3278 scrSetData(false); 3279 sc->t0SendByteS = t0sbsClockData; 3280 break; 3281 3282 default: 3283 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3284 break; 3285 } 3286 break; 3287 3288 3289 default: 3290 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3291 break; 3292 } 3293 } 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 /* 3306 **++ 3307 ** FUNCTIONAL DESCRIPTION: 3308 ** 3309 ** cardOff 3310 ** 3311 ** Turn all signals to the card off 3312 ** 3313 ** FORMAL PARAMETERS: 3314 ** 3315 ** sc - Pointer to the softc structure. 3316 ** 3317 ** IMPLICIT INPUTS: 3318 ** 3319 ** nill 3320 ** 3321 ** IMPLICIT OUTPUTS: 3322 ** 3323 ** nill 3324 ** 3325 ** FUNCTION VALUE: 3326 ** 3327 ** nill 3328 ** 3329 ** SIDE EFFECTS: 3330 ** 3331 ** nill 3332 **-- 3333 */ 3334 static void cardOff (struct scr_softc * sc) 3335 { 3336 scrSetReset(true); 3337 scrSetDataHighZ(); 3338 scrSetClock(false); 3339 scrSetPower(false); 3340 } 3341 3342 3343 3344 3345 /* 3346 ** 3347 ** 3348 ** **************** timer routines *************** 3349 ** 3350 */ 3351 3352 /* 3353 **++ 3354 ** FUNCTIONAL DESCRIPTION: 3355 ** 3356 ** scrClkInit 3357 ** 3358 ** Init the callout queues. The callout queues are used 3359 ** by the timeout/untimeout queues 3360 ** 3361 ** FORMAL PARAMETERS: 3362 ** 3363 ** nill 3364 ** 3365 ** IMPLICIT INPUTS: 3366 ** 3367 ** nill 3368 ** 3369 ** IMPLICIT OUTPUTS: 3370 ** 3371 ** nill 3372 ** 3373 ** FUNCTION VALUE: 3374 ** 3375 ** nill 3376 ** 3377 ** SIDE EFFECTS: 3378 ** 3379 ** nill 3380 **-- 3381 */ 3382 static void scrClkInit(void) 3383 { 3384 3385 int lc; 3386 Callout *c; 3387 Callout *new; 3388 3389 scrClkCallTodo.c_next = NULL; 3390 scrClkCallFree = &scrClkCalloutArray[0]; 3391 c = scrClkCallFree; 3392 3393 for (lc = 1; lc < SCR_CLK_CALLOUT_COUNT; lc++) 3394 { 3395 new = &scrClkCalloutArray[lc]; 3396 c->c_next = new; 3397 c = new; 3398 } 3399 3400 c->c_next = NULL; 3401 } 3402 3403 3404 /* 3405 **++ 3406 ** FUNCTIONAL DESCRIPTION: 3407 ** 3408 ** scrClkStart 3409 ** 3410 ** This function starts the clock running. The clock is reall the 3411 ** HAT clock (High Available Timer) that is using a FIQ (fast interrupt 3412 ** request). 3413 ** 3414 ** FORMAL PARAMETERS: 3415 ** 3416 ** sc - Pointer to the softc structure. 3417 ** countPerTick - value for T2 timer that drives FIQ 3418 ** 3419 ** IMPLICIT INPUTS: 3420 ** 3421 ** nill 3422 ** 3423 ** IMPLICIT OUTPUTS: 3424 ** 3425 ** nill 3426 ** 3427 ** FUNCTION VALUE: 3428 ** 3429 ** nill 3430 ** 3431 ** SIDE EFFECTS: 3432 ** 3433 ** nill 3434 **-- 3435 */ 3436 static void scrClkStart(struct scr_softc * sc,int countPerTick) 3437 { 3438 u_int savedInts; 3439 3440 savedInts = disable_interrupts(I32_bit | F32_bit); 3441 3442 3443 3444 ASSERT(scrClkCallTodo.c_next == NULL); 3445 ASSERT(!scrClkEnable); 3446 scrClkEnable = 1; 3447 scrClkCount = countPerTick; 3448 3449 hatClkOn(countPerTick, 3450 hatClkIrq, 3451 0xdeadbeef, 3452 hatStack + HATSTACKSIZE - sizeof(unsigned), 3453 myHatWedge); 3454 3455 restore_interrupts(savedInts); 3456 } 3457 3458 /* 3459 **++ 3460 ** FUNCTIONAL DESCRIPTION: 3461 ** 3462 ** scrClkAdj 3463 ** 3464 ** Adjusts the frequence of the clock 3465 ** 3466 ** FORMAL PARAMETERS: 3467 ** 3468 ** count - new value for T2 timer that drives FIQ 3469 ** 3470 ** IMPLICIT INPUTS: 3471 ** 3472 ** nill 3473 ** 3474 ** IMPLICIT OUTPUTS: 3475 ** 3476 ** nill 3477 ** 3478 ** FUNCTION VALUE: 3479 ** 3480 ** nill 3481 ** 3482 ** SIDE EFFECTS: 3483 ** 3484 ** nill 3485 **-- 3486 */ 3487 static void scrClkAdj (int count) 3488 { 3489 u_int savedInts; 3490 3491 if (count != scrClkCount) 3492 { 3493 savedInts = disable_interrupts(I32_bit | F32_bit); 3494 3495 ASSERT(scrClkEnable); 3496 3497 scrClkCount = count; 3498 hatClkAdjust(count); 3499 3500 restore_interrupts(savedInts); 3501 } 3502 } 3503 3504 /* 3505 **++ 3506 ** FUNCTIONAL DESCRIPTION: 3507 ** 3508 ** scrClkStop 3509 ** 3510 ** Stops the clock 3511 ** 3512 ** FORMAL PARAMETERS: 3513 ** 3514 ** nill 3515 ** 3516 ** 3517 ** IMPLICIT INPUTS: 3518 ** 3519 ** nill 3520 ** 3521 ** IMPLICIT OUTPUTS: 3522 ** 3523 ** nill 3524 ** 3525 ** FUNCTION VALUE: 3526 ** 3527 ** nill 3528 ** 3529 ** SIDE EFFECTS: 3530 ** 3531 ** nill 3532 **-- 3533 */ 3534 static void scrClkStop(void) 3535 { 3536 u_int savedInts; 3537 savedInts = disable_interrupts(I32_bit | F32_bit); 3538 3539 ASSERT(scrClkEnable); 3540 scrClkEnable = 0; 3541 ASSERT(scrClkCallTodo.c_next == NULL); 3542 hatClkOff(); 3543 3544 restore_interrupts(savedInts); 3545 } 3546 3547 3548 3549 /* 3550 **++ 3551 ** FUNCTIONAL DESCRIPTION: 3552 ** 3553 ** hatClkIrq 3554 ** 3555 ** This is what the HAT clock calls. This call drives 3556 ** the timeout queues, which in turn drive the state machines 3557 ** 3558 ** Be very carefully when calling a timeout as the function 3559 ** that is called may in turn do timeout/untimeout calls 3560 ** before returning 3561 ** 3562 ** FORMAL PARAMETERS: 3563 ** 3564 ** int x - not used 3565 ** 3566 ** IMPLICIT INPUTS: 3567 ** 3568 ** nill 3569 ** 3570 ** IMPLICIT OUTPUTS: 3571 ** 3572 ** nill 3573 ** 3574 ** FUNCTION VALUE: 3575 ** 3576 ** nill 3577 ** 3578 ** SIDE EFFECTS: 3579 ** 3580 ** a timeout may be called if it is due 3581 **-- 3582 */ 3583 static void hatClkIrq(int x) 3584 { 3585 register Callout *p1; 3586 register int needsoft =0; 3587 register Callout *c; 3588 register int arg; 3589 register void (*func)(struct scr_softc*,int); 3590 struct scr_softc * sc; 3591 3592 ASSERT(scrClkEnable); 3593 for (p1 = scrClkCallTodo.c_next; p1 != NULL; p1 = p1->c_next) 3594 { 3595 p1->c_time -= scrClkCount; 3596 3597 if (p1->c_time > 0) 3598 { 3599 break; 3600 } 3601 needsoft = 1; 3602 if (p1->c_time == 0) 3603 { 3604 break; 3605 } 3606 } 3607 3608 3609 if (needsoft) 3610 { 3611 while ((c = scrClkCallTodo.c_next) != NULL && c->c_time <= 0) 3612 { 3613 func = c->c_func; 3614 sc = c->c_sc; 3615 arg = c->c_arg; 3616 scrClkCallTodo.c_next = c->c_next; 3617 c->c_next = scrClkCallFree; 3618 scrClkCallFree = c; 3619 (*func)(sc,arg); 3620 } 3621 } 3622 } 3623 3624 /* 3625 **++ 3626 ** FUNCTIONAL DESCRIPTION: 3627 ** 3628 ** myHatWedge 3629 ** 3630 ** Called if the HAT timer becomes clogged/wedged. Not 3631 ** used by this driver, we let upper layers recover 3632 ** from this condition 3633 ** 3634 ** FORMAL PARAMETERS: 3635 ** 3636 ** int nFIQs - not used 3637 ** 3638 ** IMPLICIT INPUTS: 3639 ** 3640 ** nill 3641 ** 3642 ** IMPLICIT OUTPUTS: 3643 ** 3644 ** nill 3645 ** 3646 ** FUNCTION VALUE: 3647 ** 3648 ** nill 3649 ** 3650 ** SIDE EFFECTS: 3651 ** 3652 ** nill 3653 **-- 3654 */ 3655 static void myHatWedge(int nFIQs) 3656 { 3657 #ifdef DEBUG 3658 printf("myHatWedge: nFIQ = %d\n",nFIQs); 3659 #endif 3660 } 3661 3662 3663 3664 /* 3665 **++ 3666 ** FUNCTIONAL DESCRIPTION: 3667 ** 3668 ** scrTimeout 3669 ** 3670 ** Execute a function after a specified length of time. 3671 ** 3672 ** 3673 ** FORMAL PARAMETERS: 3674 ** 3675 ** ftn - function to execute 3676 ** sc - pointer to soft c 3677 ** arg - argument passed to function 3678 ** count - number of T2 counts for timeout 3679 ** 3680 ** IMPLICIT INPUTS: 3681 ** 3682 ** nill 3683 ** 3684 ** IMPLICIT OUTPUTS: 3685 ** 3686 ** nill 3687 ** 3688 ** FUNCTION VALUE: 3689 ** 3690 ** nill 3691 ** 3692 ** SIDE EFFECTS: 3693 ** 3694 ** nill 3695 **-- 3696 */ 3697 3698 static void scrTimeout(ftn, sc, arg, count) 3699 void (*ftn)(struct scr_softc*,int); 3700 struct scr_softc* sc; 3701 int arg; 3702 register int count; 3703 { 3704 3705 register Callout *new, *p, *t; 3706 ASSERT(scrClkEnable); 3707 3708 3709 if (count <= 0) 3710 { 3711 count = 1; 3712 } 3713 3714 3715 /* Fill in the next free fcallout structure. */ 3716 if (scrClkCallFree == NULL) 3717 { 3718 panic("timeout table full"); 3719 } 3720 3721 new = scrClkCallFree; 3722 scrClkCallFree = new->c_next; 3723 new->c_sc = sc; 3724 new->c_arg = arg; 3725 new->c_func = ftn; 3726 3727 /* 3728 * The time for each event is stored as a difference from the time 3729 * of the previous event on the queue. Walk the queue, correcting 3730 * the counts argument for queue entries passed. Correct the counts 3731 * value for the queue entry immediately after the insertion point 3732 * as well. Watch out for negative c_time values; these represent 3733 * overdue events. 3734 */ 3735 for (p = &scrClkCallTodo; (t = p->c_next) != NULL && count > t->c_time; p = t) 3736 { 3737 if (t->c_time > 0) 3738 { 3739 count -= t->c_time; 3740 } 3741 } 3742 3743 3744 new->c_time = count; 3745 if (t != NULL) 3746 { 3747 t->c_time -= count; 3748 } 3749 3750 /* Insert the new entry into the queue. */ 3751 p->c_next = new; 3752 new->c_next = t; 3753 } 3754 3755 /* 3756 **++ 3757 ** FUNCTIONAL DESCRIPTION: 3758 ** 3759 ** scrUntimeout 3760 ** 3761 ** Cancel previous timeout function call. 3762 ** 3763 ** FORMAL PARAMETERS: 3764 ** 3765 ** ftn - function of timeout to cancel 3766 ** sc - sc of timeout to cancel 3767 ** arg - arg of timeout to cancel 3768 ** 3769 ** IMPLICIT INPUTS: 3770 ** 3771 ** nill 3772 ** 3773 ** IMPLICIT OUTPUTS: 3774 ** 3775 ** nill 3776 ** 3777 ** FUNCTION VALUE: 3778 ** 3779 ** nill 3780 ** 3781 ** SIDE EFFECTS: 3782 ** 3783 ** nill 3784 **-- 3785 */ 3786 static void scrUntimeout(ftn, sc, arg) 3787 void (*ftn)(struct scr_softc*,int); 3788 struct scr_softc* sc; 3789 int arg; 3790 { 3791 register Callout *p, *t; 3792 ASSERT(scrClkEnable); 3793 3794 for (p = &scrClkCallTodo; (t = p->c_next) != NULL; p = t) 3795 { 3796 if (t->c_func == ftn && t->c_sc == sc && t->c_arg == arg) 3797 { 3798 /* Increment next entry's count. */ 3799 if (t->c_next && t->c_time > 0) 3800 { 3801 t->c_next->c_time += t->c_time; 3802 } 3803 3804 /* Move entry from fcallout queue to scrClkCallFree queue. */ 3805 p->c_next = t->c_next; 3806 t->c_next = scrClkCallFree; 3807 scrClkCallFree = t; 3808 break; 3809 } 3810 } 3811 } 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 /******************* routines used only during debugging */ 3828 #ifdef SCR_DEBUG 3829 3830 /* 3831 **++ 3832 ** FUNCTIONAL DESCRIPTION: 3833 ** 3834 ** invalidStateCmd 3835 ** 3836 ** Debugging function. Printout information about problem 3837 ** and then kick in the debugger or panic 3838 ** 3839 ** FORMAL PARAMETERS: 3840 ** 3841 ** sc - pointer to soft c 3842 ** state - state of machine 3843 ** cmd - command of machine 3844 ** line - line that problem was detected 3845 ** 3846 ** 3847 ** IMPLICIT INPUTS: 3848 ** 3849 ** nill 3850 ** 3851 ** IMPLICIT OUTPUTS: 3852 ** 3853 ** nill 3854 ** 3855 ** FUNCTION VALUE: 3856 ** 3857 ** nill 3858 ** 3859 ** SIDE EFFECTS: 3860 ** 3861 ** nill 3862 **-- 3863 */ 3864 void invalidStateCmd (struct scr_softc* sc,int state,int cmd,int line) 3865 { 3866 printf("INVALID_STATE_CMD: sc = %X, state = %X, cmd = %X, line = %d\n",sc,state,cmd,line); 3867 DEBUGGER; 3868 } 3869 3870 /* 3871 **++ 3872 ** FUNCTIONAL DESCRIPTION: 3873 ** 3874 ** getText 3875 ** 3876 ** Get text representation of state or command 3877 ** 3878 ** FORMAL PARAMETERS: 3879 ** 3880 ** x - state or command 3881 ** 3882 ** IMPLICIT INPUTS: 3883 ** 3884 ** nill 3885 ** 3886 ** IMPLICIT OUTPUTS: 3887 ** 3888 ** nill 3889 ** 3890 ** FUNCTION VALUE: 3891 ** 3892 ** nill 3893 ** 3894 ** SIDE EFFECTS: 3895 ** 3896 ** nill 3897 **-- 3898 */ 3899 char * getText(int x) 3900 { 3901 switch (x) 3902 { 3903 /* commands to Master State Machine (mc = Master Command )*/ 3904 case mcOn: return "mcOn"; 3905 case mcT0DataSend: return "mcT0DataSend"; 3906 case mcT0DataRecv: return "mcT0DataRecv"; 3907 case mcColdReset: return "mcColdReset"; 3908 case mcATR: return "mcATR"; 3909 case mcT0Send: return "mcT0Send"; 3910 case mcT0Recv: return "mcT0Recv"; 3911 3912 /* states in Master state machine (ms = Master State) */ 3913 case msIdleOff: return "msIdleOff"; 3914 case msColdReset: return "msColdReset"; 3915 case msATR: return "msATR"; 3916 case msIdleOn: return "msIdleOn"; 3917 case msT0Send: return "msT0Send"; 3918 case msT0Recv: return "msT0Recv"; 3919 3920 3921 3922 /* commands to T0 send state machine */ 3923 case t0scStart: return "t0scStart"; 3924 case t0scTWorkWaiting: return "t0scTWorkWaiting"; 3925 3926 3927 /* states in T0 send state machine */ 3928 case t0ssIdle: return "t0ssIdle"; 3929 case t0ssSendHeader: return "t0ssSendHeader"; 3930 case t0ssRecvProcedure: return "t0ssRecvProcedu"; 3931 case t0ssSendByte: return "t0ssSendByte"; 3932 case t0ssSendData: return "t0ssSendData"; 3933 case t0ssRecvSW1: return "t0ssRecvSW1"; 3934 case t0ssRecvSW2: return "t0ssRecvSW2"; 3935 3936 3937 /* commands to T0 recv state machine */ 3938 case t0rcStart: return "t0rcStart"; 3939 case t0rcTWorkWaiting: return "t0rcTWorkWaiting"; 3940 3941 /* states in T0 recv state machine */ 3942 case t0rsIdle: return "t0rsIdle"; 3943 case t0rsSendHeader: return "t0rsSendHeader"; 3944 case t0rsRecvProcedure: return "t0rsRecvProcedure"; 3945 case t0rsRecvByte: return "t0rsRecvByte"; 3946 case t0rsRecvData: return "t0rsRecvData"; 3947 case t0rsRecvSW1: return "t0rsRecvSW1"; 3948 case t0rsRecvSW2: return "t0rsRecvSW2"; 3949 3950 3951 3952 3953 3954 /* commands to Answer To Reset (ATR) state machine */ 3955 case atrcStart: return "atrcStart"; 3956 case atrcT3: return "0x0b04"; 3957 case atrcTWorkWaiting: return "atrcTWorkWaiting"; 3958 3959 3960 /* states in in Anser To Reset (ATR) state machine */ 3961 case atrsIdle: return "atrsIdle"; 3962 case atrsTS: return "atrsTS"; 3963 case atrsT0: return "atrsT0"; 3964 case atrsTABCD: return "atrsTABCD"; 3965 case atrsTK: return "atrsTK"; 3966 case atrsTCK: return "atrsTCK"; 3967 3968 3969 3970 /* commands to T0 Recv Byte state machine */ 3971 case t0rbcStart: return "t0rbcStart"; 3972 case t0rbcAbort: return "t0rbcAbort"; 3973 3974 case t0rbcTFindStartEdge:return "t0rbcTFindStartEdge"; 3975 case t0rbcTFindStartMid: return "t0rbcTFindStartMid"; 3976 case t0rbcTClockData: return "t0rbcTClockData"; 3977 case t0rbcTErrorStart: return "t0rbcTErrorStart"; 3978 case t0rbcTErrorStop: return "t0rbcTErrorStop"; 3979 3980 /* states in in TO Recv Byte state machine */ 3981 case t0rbsIdle: return "t0rbsIdle"; 3982 case t0rbsFindStartEdge: return "t0rbcFindStartEdge"; 3983 case t0rbsFindStartMid: return "t0rbcFindStartMid"; 3984 case t0rbsClockData: return "t0rbcClockData"; 3985 case t0rbsSendError: return "t0rbcSendError"; 3986 3987 3988 /* commands to T0 Send Byte state machine */ 3989 case t0sbcStart: return "t0sbcStart"; 3990 case t0sbcAbort: return "t0sbcAbort"; 3991 case t0sbcTGuardTime: return "t0sbcTGuardTime"; 3992 case t0sbcTClockData: return "t0sbcTClockData"; 3993 case t0sbcTError: return "t0sbcTError"; 3994 case t0sbcTResend: return "t0sbcTResend"; 3995 3996 /* states in in T0 Send Byte state machine */ 3997 case t0sbsIdle: return "t0sbsIdle"; 3998 case t0sbsClockData: return "t0sbsClockData"; 3999 case t0sbsWaitError: return "t0sbsWaitError"; 4000 case t0sbsWaitResend: return "t0sbsWaitResend"; 4001 case t0sbsWaitGuardTime: return "t0sbsWaitGuardTime"; 4002 4003 4004 case gcT0RecvByte: return "gcT0RecvByte"; 4005 case gcT0RecvByteErr: return "gcT0RecvByteErr"; 4006 case gcT0SendByte: return "gcT0SendByte"; 4007 case gcT0SendByteErr: return "gcT0SendByteErr"; 4008 4009 4010 case crcStart: return "crcStart"; 4011 case crcT2: return "crcT2"; 4012 4013 4014 default: 4015 printf("unknown case, %x\n",x); 4016 break; 4017 } 4018 return "???"; 4019 } 4020 4021 #endif /* SCR_DEBUG */ 4022 4023 4024 4025