1 /* $NetBSD: scr.c,v 1.1 2002/02/10 01:58:08 thorpej Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 **++ 38 ** 39 ** FACILITY: 40 ** 41 ** Driver for smart card 42 ** 43 ** ABSTRACT: 44 ** 45 ** The driver provides access to a Smart Card for the DNARD. 46 ** 47 ** There is no Smart Card silicon. Several i/o pins 48 ** connect to the pads on the Smart Card, and the driver is 49 ** is responsible for driving the signals in accordance with 50 ** ISO 7816-3 (the Smart Card spec) 51 ** 52 ** This driver puts a high load on the system due to the need 53 ** to interrupt at a high rate (up to 50 Khz) during bit detection. 54 ** 55 ** 56 ** The driver is dived into the standard top half ioctl, and bottom 57 ** half interupt. The interrupt is FIQ, which requires its own stack. 58 ** disable_interrupts and restore_interrupts must be used to protect from 59 ** a FIQ. Since splxxx functions do not use this, the bottom half cannot 60 ** use any standard functions (ie like wakeup, timeout, etc. 61 ** Thus the communication from the bottom half 62 ** to the top half uses a "done" bit called masterDone. This bit 63 ** is set by the master state machine when all bottom half work is 64 ** complete. The top half checks/sleeps on this masterDone bit. 65 ** 66 ** The FIQ is driven by Timer 2 (T2)in the sequoia. All times are 67 ** referenced to T2 counts. 68 ** 69 ** The bottom half is done as a several linked state machines. 70 ** The top level machine is the maserSM (ie master State Machine). This 71 ** machine calls mid level protocol machines, ie ATRSM (Answer To Reset 72 ** State Machine), t0SendSM (T=0 Send State Machine), and t0RecvSM (T=0 Recv 73 ** State Machine). These mid level protocol machines in turn call low level 74 ** bit-bashing machines, ie coldResetSM, t0SendByteSM, T0RecvByteSM. 75 ** 76 ** Smart Cards are driven in a command/response mode. Ie you issue a command 77 ** to the Smart Card and it responds. This command/response mode is reflected 78 ** in the structure of the driver. Ie the ioctl gets a command, it 79 ** gives it to the bottom half to execute and goes to sleep. The bottom half 80 ** executes the command and gets the response to from the card and then 81 ** notifies the top half that it has completed. Commands usually complete 82 ** in under a second. 83 ** 84 ** 85 ** 86 ** AUTHORS: 87 ** 88 ** E. J. Grohn 89 ** Digital Equipment Corporation. 90 ** 91 ** CREATION DATE: 92 ** 93 ** 27-July-97 94 ** 95 **-- 96 */ 97 98 /* 99 ** 100 ** INCLUDE FILES 101 ** 102 */ 103 104 #include "opt_ddb.h" 105 106 #include <sys/param.h> 107 #include <sys/systm.h> 108 #include <sys/ioctl.h> 109 /* #include <sys/select.h> */ 110 /* #include <sys/tty.h> */ 111 #include <sys/proc.h> 112 /* #include <sys/user.h> */ 113 #include <sys/conf.h> 114 /* #include <sys/file.h> */ 115 /* #include <sys/uio.h> */ 116 #include <sys/kernel.h> 117 /* #include <sys/syslog.h> */ 118 #include <sys/types.h> 119 #include <sys/device.h> 120 #include <dev/isa/isavar.h> 121 #include <arm/cpufunc.h> 122 123 124 /* SCR_DEBUG is the master switch for turning on debugging */ 125 //#define SCR_DEBUG 1 126 #ifdef SCR_DEBUG 127 #define KERNEL_DEBUG 128 #ifdef DDB 129 #define DEBUGGER printf("file = %s, line = %d\n",__FILE__,__LINE__);Debugger() 130 #else 131 #define DEBUGGER panic("file = %s, line = %d\n",__FILE__,__LINE__); 132 #endif 133 #else 134 #define DEBUGGER 135 #endif 136 137 138 #include <machine/kerndebug.h> 139 //#include <machine/intr.h> 140 #include <dev/ic/i8253reg.h> 141 #include <shark/shark/hat.h> 142 #include <shark/shark/sequoia.h> 143 #include <machine/scrio.h> 144 145 146 147 148 /* 149 ** 150 ** MACRO DEFINITIONS 151 ** 152 */ 153 154 155 #define scr_lcr scr_cfcr 156 157 /* 158 ** Macro to extract the minor device number from the device Identifier 159 */ 160 #define SCRUNIT(x) (minor(x)) 161 162 /* 163 ** Macros to clear/set/test bit flags. 164 */ 165 #define SET(t, f) (t) |= (f) 166 #define CLR(t, f) (t) &= ~(f) 167 #define ISSET(t, f) ((t) & (f)) 168 #define ISCLR(t, f) ( ((t) & (f)) == 0) 169 170 171 /* 172 ** some macros to assist in debugging 173 */ 174 #ifdef SCR_DEBUG 175 #define KERNEL_DEBUG 176 #define ASSERT(f) do { if (!(f)) { DEBUGGER;} }while(0) 177 #define TOGGLE_TEST_PIN() scrToggleTestPin() 178 #define INVALID_STATE_CMD(sc,state,cmd) invalidStateCmd(sc,state,cmd,__LINE__); 179 #else 180 #define ASSERT(f) 181 #define TOGGLE_TEST_PIN() 182 //#define INVALID_STATE_CMD(sc,state,cmd) panic("scr: invalid state/cmd, sc = %X, state = %X, cmd = %X, line = %d\n",sc,state,cmd,__LINE__); 183 #define INVALID_STATE_CMD(sc,state,cmd) sc->bigTrouble = TRUE; 184 185 #endif 186 187 #ifndef FALSE 188 #define FALSE 0 189 #endif 190 191 #ifndef TRUE 192 #define TRUE 1 193 #endif 194 195 196 197 198 199 /* 200 ** The first and last bytes of the debug control variables is reserved for 201 ** the standard KERN_DEBUG_xxx macros, so we can tailor the middle two bytes 202 */ 203 #define SCRPROBE_DEBUG_INFO 0x00000100 204 #define SCRATTACH_DEBUG_INFO 0x00000200 205 #define SCROPEN_DEBUG_INFO 0x00000400 206 #define SCRCLOSE_DEBUG_INFO 0x00000800 207 #define SCRREAD_DEBUG_INFO 0x00001000 208 #define SCRWRITE_DEBUG_INFO 0x00002000 209 #define SCRIOCTL_DEBUG_INFO 0x00004000 210 #define MASTER_SM_DEBUG_INFO 0x00008000 211 #define COLD_RESET_SM_DEBUG_INFO 0x00010000 212 #define ATR_SM_DEBUG_INFO 0x00020000 213 #define T0_RECV_BYTE_SM_DEBUG_INFO 0x00040000 214 #define T0_SEND_BYTE_SM_DEBUG_INFO 0x00080000 215 #define T0_RECV_SM_DEBUG_INFO 0x00100000 216 #define T0_SEND_SM_DEBUG_INFO 0x00200000 217 218 219 int scrdebug = //SCRPROBE_DEBUG_INFO | 220 //SCRATTACH_DEBUG_INFO | 221 //SCROPEN_DEBUG_INFO | 222 //SCRCLOSE_DEBUG_INFO | 223 //SCRREAD_DEBUG_INFO | 224 //SCRWRITE_DEBUG_INFO | 225 //SCRIOCTL_DEBUG_INFO | 226 //MASTER_SM_DEBUG_INFO | 227 //COLD_RESET_SM_DEBUG_INFO| 228 //ATR_SM_DEBUG_INFO | 229 //T0_RECV_BYTE_SM_DEBUG_INFO | 230 //T0_SEND_BYTE_SM_DEBUG_INFO | 231 //T0_RECV_SM_DEBUG_INFO | 232 //T0_SEND_SM_DEBUG_INFO | 233 0; 234 235 236 237 238 239 240 /* 241 ** the bottom half of the driver is done as several linked state machines 242 ** below are all the states of the machines, and the commands that are 243 ** sent to each machine 244 */ 245 246 /* commands to Master State Machine from ioctl */ 247 #define mcOn 0x0100 /* ioctl on */ 248 #define mcT0DataSend 0x0102 /* ioctl send */ 249 #define mcT0DataRecv 0x0103 /* ioctl recv */ 250 251 /* commands to Master State Machine from lower state machines */ 252 #define mcColdReset 0x0105 /* cold reset finished */ 253 #define mcATR 0x0106 /* ATR has finished */ 254 #define mcT0Send 0x0108 /* T0 send finished */ 255 #define mcT0Recv 0x010a /* T0 recv finished */ 256 257 /* states in Master state machine (ms = Master State) */ 258 #define msIdleOff 0x0200 /* in idle state, card powered off */ 259 #define msColdReset 0x0201 /* turning on power, clock, reset */ 260 #define msATR 0x0202 /* getting ATR sequence from card */ 261 #define msIdleOn 0x0203 /* idle, put card powered on */ 262 #define msT0Send 0x0204 /* sending T0 data */ 263 #define msT0Recv 0x0205 /* recving T0 data */ 264 265 266 267 268 /* commands to T0 send state machine */ 269 #define t0scStart 0x0300 /* start */ 270 #define t0scTWorkWaiting 0x0301 /* work waiting timeout */ 271 272 /* states in T0 send state machine */ 273 #define t0ssIdle 0x0400 /* idle state */ 274 #define t0ssSendHeader 0x0401 /* send 5 header bytes */ 275 #define t0ssRecvProcedure 0x0402 /* wait for procedure byte */ 276 #define t0ssSendByte 0x0403 /* send 1 byte */ 277 #define t0ssSendData 0x0404 /* send all bytes */ 278 #define t0ssRecvSW1 0x0405 /* wait for sw1 */ 279 #define t0ssRecvSW2 0x0406 /* wait for sw2 */ 280 281 282 283 284 285 /* commands to T0 recv state machine */ 286 #define t0rcStart 0x0500 /* start */ 287 #define t0rcTWorkWaiting 0x0501 /* work waiting timeout */ 288 289 /* states in T0 recv state machine */ 290 #define t0rsIdle 0x0600 /* idle state */ 291 #define t0rsSendHeader 0x0601 /* send 5 header bytes */ 292 #define t0rsRecvProcedure 0x0602 /* wait for procedure byte */ 293 #define t0rsRecvByte 0x0603 /* recv 1 byte */ 294 #define t0rsRecvData 0x0604 /* recv all bytes */ 295 #define t0rsRecvSW1 0x0605 /* wait for sw1 */ 296 #define t0rsRecvSW2 0x0606 /* wait for sw2 */ 297 298 299 300 /* commands to Cold Reset state machine */ 301 #define crcStart 0x0900 /* start */ 302 #define crcT2 0x0902 /* timeout T2 ISO 7816-3, P6, Figure 2 */ 303 304 /* states in cold reset state machine */ 305 #define crsIdle 0x0a00 /* idle */ 306 #define crsT2Wait 0x0a01 /* wait for T2 ISO 7816-3.P6. Figure 2 */ 307 308 309 310 311 312 /* commands to Answer To Reset (ATR) state machine */ 313 #define atrcStart 0x0b00 /* start */ 314 #define atrcT3 0x0b04 /* got T3 timeout */ 315 #define atrcTWorkWaiting 0x0b05 /* work waiting timeout */ 316 317 /* states in Answer To Reset (ATR) state machine */ 318 #define atrsIdle 0x0c00 /* idle */ 319 #define atrsTS 0x0c01 /* looking for TS, (initial bytes) */ 320 #define atrsT0 0x0c02 /* looking for T0, (format bytes) */ 321 #define atrsTABCD 0x0c03 /* looking for TAx (interface bytes)*/ 322 #define atrsTK 0x0c04 /* looking for TK (history bytes) */ 323 #define atrsTCK 0x0c05 /* looking for TCK (check bytes */ 324 325 326 /* commands to T0 Recv Byte state machine */ 327 #define t0rbcStart 0x0d00 /* start */ 328 #define t0rbcAbort 0x0d01 /* abort */ 329 #define t0rbcTFindStartEdge 0x0d02 /* start bit edge search */ 330 #define t0rbcTFindStartMid 0x0d03 /* start bit mid search */ 331 #define t0rbcTClockData 0x0d04 /* data bit search */ 332 #define t0rbcTErrorStart 0x0d05 /* start to send error */ 333 #define t0rbcTErrorStop 0x0d06 /* stop sending error */ 334 335 /* states in T0 Recv Byte state machine */ 336 #define t0rbsIdle 0x0e00 /* idle */ 337 #define t0rbsFindStartEdge 0x0e01 /* looking for start bit */ 338 #define t0rbsFindStartMid 0x0e02 /* looking for start bit */ 339 #define t0rbsClockData 0x0e03 /* looking for data bits */ 340 #define t0rbsSendError 0x0e04 /* output error bit */ 341 342 343 344 345 /* commands to T0 Send Byte state machine */ 346 #define t0sbcStart 0x0f00 /* start the machine */ 347 #define t0sbcAbort 0x0f01 /* abort the machine */ 348 #define t0sbcTGuardTime 0x0f02 /* guard time finished */ 349 #define t0sbcTClockData 0x0f03 /* clock time finished */ 350 #define t0sbcTError 0x0f04 /* start to send error */ 351 #define t0sbcTResend 0x0f05 /* if parity error, then wait unfill we can re-send */ 352 353 354 355 /* states in T0 Send Byte state machine */ 356 #define t0sbsIdle 0x1000 /* idle */ 357 #define t0sbsWaitGuardTime 0x1001 /* wait for guard time to finish */ 358 #define t0sbsClockData 0x1002 /* clocking out data & parity */ 359 #define t0sbsWaitError 0x1003 /* waiting for error indicator */ 360 #define t0sbsWaitResend 0x1004 /* waiting to start re-send if error */ 361 362 363 364 365 /* 366 ** generic middle level state machine commands 367 ** sent by T0 Send Byte & T0 recv Byte to T0 Send and T0 Recv 368 */ 369 #define gcT0RecvByte 0x1100 /* receive finished */ 370 #define gcT0RecvByteErr 0x1101 /* receive got error */ 371 #define gcT0SendByte 0x1102 /* send finished */ 372 #define gcT0SendByteErr 0x1103 /* send got error */ 373 374 375 376 377 378 379 /* 380 ** 381 ** below are definitions associated with Smart Card 382 ** 383 */ 384 385 386 /* 387 ** Frequency of clock sent to card 388 ** NCI's card is running at 1/2 freq, so in debug we can make 389 ** use of this to toggle more debug signals and still be within 390 ** interrupt time budget 391 */ 392 #ifdef SCR_DEBUG 393 #define CARD_FREQ_DEF (3579000/2) 394 #else 395 #define CARD_FREQ_DEF (3579000) 396 #endif 397 398 399 400 /* byte logic level and msb/lsb coding */ 401 #define CONVENTION_UNKOWN 0 402 #define CONVENTION_INVERSE 1 403 #define CONVENTION_DIRECT 2 404 #define CONVENIONT_INVERSE_ID 0x3f 405 #define CONVENTION_DIRECT_FIX 0x3b 406 #define CONVENTION_DIRECT_ID 0x23 407 408 409 /* macros that help us set the T2 count for bit bashing */ 410 #define CLK_COUNT_START (((372 * TIMER_FREQ) / sc->cardFreq) /5) 411 #define CLK_COUNT_DATA (((372 * TIMER_FREQ) / sc->cardFreq) ) 412 #define START_2_DATA 5 413 414 /* default settings to use if not specified in ATR */ 415 #define N_DEFAULT 0 /* guard time default */ 416 #define Fi_DEFAULT 372 /* clock rate conversion default */ 417 #define Di_DEFAULT 1 /* bit rate adjustment factor */ 418 #define Wi_DEFAULT 10 /* waiting time */ 419 420 421 /* table for clock rate adjustment in ATR */ 422 int FI2Fi[16] = {372, 372, 558, 744,1116,1488,1860, 0, 423 0, 512, 768,1024,1536,2048, 0, 0}; 424 425 /* table for bit rate adjustment in ATR*/ 426 int DI2Di[16] = { 0, 1, 2, 4, 8, 16, 32, 0, 427 12, 20, 0, 0, 0, 0, 0, 0}; 428 429 /* values of atrY in the ATR sequence*/ 430 #define ATR_Y_TA 0x10 431 #define ATR_Y_TB 0x20 432 #define ATR_Y_TC 0x40 433 #define ATR_Y_TD 0x80 434 435 /* T0,T1,etc information in ATR sequence*/ 436 #define PROTOCOL_T0 0x0001 /* bit 0 for T0 */ 437 #define PROTOCOL_T1 0x0002 /* bit 1 for T1 */ 438 #define PROTOCOL_T2 0x0004 /* bit 2 for T2*/ 439 #define PROTOCOL_T3 0x0008 /* bit 3 for T3*/ 440 /* etc */ 441 442 443 /* timeouts for various places - see ISO 7816-3 */ 444 #define T_t2 ((300 * TIMER_FREQ) / sc->cardFreq) 445 #define T_t3 ((40000 * (TIMER_FREQ/1024)) / (sc->cardFreq/1024)) 446 #define T_WORK_WAITING (((960 * sc->Wi * sc->Fi ) / (sc->cardFreq/1024)) * (TIMER_FREQ/1024)) 447 #define PARITY_ERROR_MAX 3 /* maximum parity errors on 1 byte before giving up */ 448 449 /* 450 ** its possible for the HAT to wedge. If that happens, all timing is sick, so 451 ** we use timeout below (driven of system sleeps) as a "watchdog" 452 */ 453 #define MAX_FIQ_TIME 5 /* maximum time we are willing to run the FIQ */ 454 455 456 /* used to decode T0 commands */ 457 #define CMD_BUF_INS_OFF 1 /* offset to INS in header */ 458 #define CMD_BUF_DATA_LEN_OFF 4 /* offset to data length in header */ 459 460 461 /* 462 ** 463 ** DATA STRUCTURES 464 ** 465 */ 466 typedef unsigned char BYTE; 467 468 /* our soft c structure */ 469 struct scr_softc 470 { 471 struct device dev; 472 int open; 473 474 /* configuration information */ 475 int status; /* status to be returned */ 476 int cardFreq; /* freq supplied to card */ 477 int convention; /* ie direct or inverse */ 478 int protocolType; /* bit 0 indicates T0, bit 1 indicates T1,etc */ 479 int N; /* guard time */ 480 int Fi; /* clock rate */ 481 int Di; /* bit rate adjustment */ 482 int Wi; /* work waiting time */ 483 int clkCountStartRecv; /* count for clock start bits on recv */ 484 int clkCountDataRecv; /* count for clock data bits on recv*/ 485 int clkCountDataSend; /* count for clock data bits on send */ 486 487 /* state machines */ 488 int masterS ; 489 int t0RecvS; 490 int t0SendS; 491 int coldResetS; 492 int ATRS; 493 int t0RecvByteS; 494 int t0SendByteS; 495 496 /* extra stuff kept for t0send state machine */ 497 int commandCount; /* number of command bytes sent */ 498 int dataCount; /* number of data bytes send/recv */ 499 int dataMax; /* max number of data bytes to send/recv */ 500 501 /* extra stuff kept for t0RecvByteS, t0SendByteS machines */ 502 void (*t0ByteParent) __P((struct scr_softc *,int)); /* state machine that is controlling this SM */ 503 int shiftBits; /* number of bits shifted */ 504 BYTE shiftByte; /* intermediate value of bit being shifted */ 505 BYTE dataByte; /* actual value of byte */ 506 int shiftParity; /* value of parity */ 507 int shiftParityCount; /* number of retries due to parity error */ 508 509 /* extra stuff kept for ATR machine */ 510 int atrY; /* indicates if TA,TB,TC,TD is to follow */ 511 int atrK; /* number of historical characters*/ 512 int atrKCount; /* progressive could of historical characters*/ 513 int atrTABCDx; /* the 'i' in TA(i), TB(i), TC(i) and TD(i) */ 514 int atrFi; /* value of Fi */ 515 int atrDi; /* value of Di */ 516 517 int masterDone; /* flag used by bottom half to tell top half its done */ 518 int bigTrouble; /* david/jim, remove this when the dust settles */ 519 520 /* pointers used by ioctl */ 521 ScrOn * pIoctlOn; /* pointer to on ioctl data */ 522 ScrT0 * pIoctlT0; /* pointer to T0 ioctl data */ 523 }; 524 525 /* number of devices */ 526 static int devices = 0; 527 528 /* used as reference for tsleep */ 529 static int tsleepIdent; 530 531 532 /* 533 ** only 1 device is using the hat at any one time 534 ** variable below must be acquired using splhigh before using the hat 535 */ 536 static int hatLock = FALSE; 537 538 539 540 541 /* 542 ** data structures associated with our timeout queue that we run for the 543 ** bottom half of the driver 544 */ 545 546 /* timeout callout structure */ 547 typedef struct callout_t 548 { 549 struct callout_t *c_next; /* next callout in queue */ 550 struct scr_softc *c_sc; /* soft c */ 551 int c_arg; /* function argument */ 552 void (*c_func) __P((struct scr_softc*,int)); /* function to call */ 553 int c_time; /* ticks to the event */ 554 }Callout; 555 556 /* actual callout array */ 557 #define SCR_CLK_CALLOUT_COUNT 10 558 static Callout scrClkCalloutArray[SCR_CLK_CALLOUT_COUNT]; 559 560 /* callout lists */ 561 static Callout *scrClkCallFree; /* free queue */ 562 static Callout scrClkCallTodo; /* todo queue */ 563 564 /* 565 ** information kept for the clock/FIQ that drives our timeout queue 566 */ 567 static int scrClkEnable = 0; /* true if clock enabled */ 568 static void myHatWedge(int nFIQs); /* callback that informs us if FIQ has wedged */ 569 static int scrClkCount; /* number used to set t2 that drives FIQ */ 570 571 #define HATSTACKSIZE 1024 /* size of stack used during a FIQ */ 572 static unsigned char hatStack[HATSTACKSIZE]; /* actual stack used during a FIQ */ 573 574 575 576 577 578 579 580 581 582 583 584 585 /* 586 ** 587 ** FUNCTIONAL PROTOTYPES 588 ** 589 */ 590 591 /* 592 ** 593 ** functions in top half of driver 594 ** 595 */ 596 597 /* configure routines */ 598 int scrprobe __P((struct device *, void *, void *)); 599 void scrattach __P((struct device *, struct device *, void *)); 600 601 /* driver entry points routines */ 602 int scropen __P((dev_t dev, int flag, int mode, struct proc *p)); 603 int scrclose __P((dev_t dev, int flag, int mode, struct proc *p)); 604 int scrread __P((dev_t dev, struct uio *uio, int flag)); 605 int scrwrite __P((dev_t dev, struct uio *uio, int flag)); 606 int scrioctl __P((dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)); 607 void scrstop __P((struct tty *tp, int flag)); 608 609 static void initStates __P((struct scr_softc * sc)); 610 611 612 613 614 /* 615 ** 616 ** functions in bottom half of driver 617 ** 618 */ 619 620 /* top level state machine */ 621 static void masterSM __P((struct scr_softc * sc,int cmd)); 622 623 /* mid level state machines, ie protocols */ 624 static void t0SendSM __P((struct scr_softc * sc,int cnd)); 625 static void t0RecvSM __P((struct scr_softc * sc,int cnd)); 626 static void ATRSM __P((struct scr_softc * sc,int cnd)); 627 628 /* low level state machines, ie bash hardware bits */ 629 static void coldResetSM __P((struct scr_softc * sc,int cnd)); 630 631 static void t0SendByteSM __P((struct scr_softc * sc,int cnd)); 632 static void t0RecvByteSM __P((struct scr_softc * sc,int cnd)); 633 634 static void cardOff __P((struct scr_softc * sc)); 635 636 /* 637 ** functions used for our own timeout routines. 638 ** we cannot use system ones as we are running at a spl level 639 ** that can interrupt the system timeout routines 640 */ 641 static void scrClkInit __P((void)); 642 static void scrClkStart __P((struct scr_softc* sc,int countPerTick)); 643 static void scrClkAdj __P((int count)); 644 static void scrClkStop __P((void)); 645 static void hatClkIrq __P((int count)); 646 647 static void scrTimeout __P((void (*func)(struct scr_softc*,int), struct scr_softc*, int arg, int count)); 648 static void scrUntimeout __P((void (*func)(struct scr_softc*,int), struct scr_softc*, int arg)); 649 650 651 /* debug functions */ 652 #ifdef SCR_DEBUG 653 static void invalidStateCmd __P((struct scr_softc* sc,int state,int cmd, int line)); 654 static char * getText __P((int x)); 655 #endif 656 657 658 659 /* Declare the cdevsw and bdevsw entrypoint routines 660 */ 661 cdev_decl(scr); 662 bdev_decl(scr); 663 664 665 struct cfattach scr_ca = 666 { 667 sizeof(struct scr_softc), (cfmatch_t)scrprobe, scrattach 668 }; 669 670 extern struct cfdriver scr_cd; 671 672 673 /* 674 **++ 675 ** FUNCTIONAL DESCRIPTION: 676 ** 677 ** scrProbe 678 ** 679 ** This is the probe routine for the Smart Card. Because the 680 ** Smart Card is hard wired, there is no probing to peform. The 681 ** function ensures that a succesfull problem occurs only once. 682 ** 683 ** FORMAL PARAMETERS: 684 ** 685 ** parent - input : pointer to the parent device 686 ** match - not used 687 ** aux - output : pointer to an isa_attach_args structure. 688 ** 689 ** IMPLICIT INPUTS: 690 ** 691 ** none. 692 ** 693 ** IMPLICIT OUTPUTS: 694 ** 695 ** none. 696 ** 697 ** FUNCTION VALUE: 698 ** 699 ** 0 - Probe failed to find the requested device. 700 ** 1 - Probe successfully talked to the device. 701 ** 702 ** SIDE EFFECTS: 703 ** 704 ** none. 705 **-- 706 */ 707 int scrprobe(parent, match, aux) 708 struct device *parent; 709 void *match; 710 void *aux; 711 { 712 struct isa_attach_args *ia = aux; 713 int rv = 0; 714 715 KERN_DEBUG (scrdebug, SCRPROBE_DEBUG_INFO,("scrprobe: called, name = %s\n", 716 parent->dv_cfdata->cf_driver->cd_name)); 717 718 if (strcmp(parent->dv_cfdata->cf_driver->cd_name, "ofisascr") == 0 && 719 devices == 0) 720 { 721 /* set "devices" to ensure that we respond only once */ 722 devices++; 723 724 /* tell the caller that we are not using any resource */ 725 ia->ia_nio = 0; 726 ia->ia_niomem = 0; 727 ia->ia_nirq = 0; 728 ia->ia_ndrq = 0; 729 rv = 1; 730 731 732 KERN_DEBUG (scrdebug, SCRPROBE_DEBUG_INFO,("scrprobe: successful \n")); 733 734 } 735 736 737 return (rv); 738 739 } /* End scrprobe() */ 740 741 742 /* 743 **++ 744 ** FUNCTIONAL DESCRIPTION: 745 ** 746 ** scrattach 747 ** 748 ** Initialize the clock and state machines 749 ** 750 ** FORMAL PARAMETERS: 751 ** 752 ** parent - input : pointer to my parents device structure. 753 ** self - output : pointer to my softc with device structure at front. 754 ** aux - input : pointer to the isa_attach_args structure. 755 ** 756 ** IMPLICIT INPUTS: 757 ** 758 ** nill 759 ** 760 ** IMPLICIT OUTPUTS: 761 ** 762 ** scrconsinit - clock callout functions set 763 ** state machines all at idle 764 ** 765 ** FUNCTION VALUE: 766 ** 767 ** none. 768 ** 769 ** SIDE EFFECTS: 770 ** 771 ** none. 772 **-- 773 */ 774 void scrattach(parent, self, aux) 775 struct device *parent; 776 struct device *self; 777 void *aux; 778 { 779 struct scr_softc *sc = (void *)self; 780 781 printf("\n"); 782 if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "ofisascr")) 783 { 784 KERN_DEBUG (scrdebug, SCRATTACH_DEBUG_INFO,("scrattach: called \n")); 785 786 /* set initial state machine values */ 787 scrClkInit(); 788 initStates(sc); 789 sc->open = FALSE; 790 } 791 792 else 793 { 794 panic("scrattach: not on an ISA bus, attach impossible"); 795 } /* End else we aren't on ISA and we can't handle it */ 796 797 798 return; 799 } /* End scrattach() */ 800 801 802 /* 803 **++ 804 ** FUNCTIONAL DESCRIPTION: 805 ** 806 ** initStates 807 ** 808 ** sets the state of all machines to idle 809 ** 810 ** FORMAL PARAMETERS: 811 ** 812 ** sc - Pointer to the softc structure. 813 ** 814 ** IMPLICIT INPUTS: 815 ** 816 ** nill 817 ** 818 ** IMPLICIT OUTPUTS: 819 ** 820 ** nill 821 ** 822 ** FUNCTION VALUE: 823 ** 824 ** nill 825 ** 826 ** SIDE EFFECTS: 827 ** 828 ** nill 829 **-- 830 */ 831 static void initStates(struct scr_softc * sc) 832 { 833 sc->masterS = msIdleOff; 834 sc->t0RecvS = t0rsIdle; 835 sc->t0SendS = t0ssIdle; 836 sc->coldResetS = crsIdle; 837 sc->ATRS = atrsIdle; 838 sc->t0RecvByteS = t0rbsIdle; 839 sc->t0SendByteS = t0sbsIdle; 840 } 841 842 843 844 /* 845 **++ 846 ** FUNCTIONAL DESCRIPTION: 847 ** 848 ** scrOpen 849 ** 850 ** Opens the driver. We only let the device be opened 851 ** once for security reasons 852 ** 853 ** FORMAL PARAMETERS: 854 ** 855 ** dev - input : Device identifier consisting of major and minor numbers. 856 ** flag - input : Indicates if this is a blocking I/O call. 857 ** mode - not used. 858 ** p - input : Pointer to the proc structure of the process 859 ** performing the open. 860 ** 861 ** IMPLICIT INPUTS: 862 ** 863 ** none. 864 ** 865 ** IMPLICIT OUTPUTS: 866 ** 867 ** none. 868 ** 869 ** FUNCTION VALUE: 870 ** 871 ** ENXIO - invalid device specified for open. 872 ** EBUSY - The unit is already open 873 ** 874 ** SIDE EFFECTS: 875 ** 876 ** none. 877 **-- 878 */ 879 int scropen(dev, flag, mode, p) 880 dev_t dev; 881 int flag; 882 int mode; 883 struct proc *p; 884 { 885 int unit = SCRUNIT(dev); 886 struct scr_softc *sc; 887 888 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO, 889 ("scropen: called with minor device %d and flag 0x%x\n", 890 unit, flag)); 891 892 /* Sanity check the minor device number we have been instructed 893 ** to open and set up our softc structure pointer. 894 */ 895 if (unit >= scr_cd.cd_ndevs) 896 { 897 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return ENXIO\n")); 898 return (ENXIO); 899 } 900 sc = scr_cd.cd_devs[unit]; 901 if (!sc) 902 { 903 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return ENXIO\n")); 904 return (ENXIO); 905 } 906 907 908 // david,jim - remove ifdef this when NCI can cope with only 1 open 909 #if 0 910 if (sc->open) 911 { 912 913 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("\t scropen, return EBUSY\n")); 914 return (EBUSY); 915 } 916 917 918 /* set all initial conditions */ 919 sc->open = TRUE; 920 #endif 921 922 KERN_DEBUG (scrdebug, SCROPEN_DEBUG_INFO,("scropen: success \n")); 923 /* Now invoke the line discipline open routine 924 */ 925 926 return 0; 927 928 } /* End scropen() */ 929 930 931 /* 932 **++ 933 ** FUNCTIONAL DESCRIPTION: 934 ** 935 ** This function closed the driver 936 ** 937 ** FORMAL PARAMETERS: 938 ** 939 ** dev - input : Device identifier consisting of major and minor numbers. 940 ** flag - Not used. 941 ** mode - Not used. 942 ** p - Not used. 943 ** 944 ** IMPLICIT INPUTS: 945 ** 946 ** scr_cd - used to locate the softc structure for the device unit 947 ** identified by dev. 948 ** 949 ** IMPLICIT OUTPUTS: 950 ** 951 ** The device is put into an idle state. 952 ** 953 ** FUNCTION VALUE: 954 ** 955 ** 0 - Always returns success. 956 ** 957 ** SIDE EFFECTS: 958 ** 959 ** none. 960 **-- 961 */ 962 int scrclose(dev, flag, mode, p) 963 dev_t dev; 964 int flag; 965 int mode; 966 struct proc *p; 967 { 968 #if 0 969 int unit = SCRUNIT(dev); 970 struct scr_softc *sc = scr_cd.cd_devs[unit]; 971 #endif 972 973 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO, 974 ("scrclose: called for minor device %d flag 0x%x\n", 975 SCRUNIT(dev), flag)); 976 977 // david,jim - remove ifdef this when NCI can cope with only 1 open 978 #if 0 979 /* Check we are open in the first place 980 */ 981 if (sc->open) 982 { 983 /* put everything in the idle state */ 984 scrClkInit(); 985 initStates(sc); 986 sc->open = FALSE; 987 988 } 989 990 991 else 992 { 993 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO,("\t scrclose, device not open\n")); 994 } 995 #endif 996 997 KERN_DEBUG (scrdebug, SCRCLOSE_DEBUG_INFO,("scrclose exiting\n")); 998 return(0); 999 } 1000 1001 1002 1003 /* 1004 **++ 1005 ** FUNCTIONAL DESCRIPTION: 1006 ** 1007 ** scrwrite 1008 ** 1009 ** not supported 1010 ** 1011 ** FORMAL PARAMETERS: 1012 ** 1013 ** dev - input : Device identifier consisting of major and minor numbers. 1014 ** uio - input : Pointer to the user I/O information (ie. write data). 1015 ** flag - input : Information on how the I/O should be done (eg. blocking 1016 ** or non-blocking). 1017 ** 1018 ** IMPLICIT INPUTS: 1019 ** 1020 ** 1021 ** IMPLICIT OUTPUTS: 1022 ** 1023 ** none 1024 ** 1025 ** FUNCTION VALUE: 1026 ** 1027 ** Returns ENODEV 1028 ** 1029 ** SIDE EFFECTS: 1030 ** 1031 ** none 1032 **-- 1033 */ 1034 int 1035 scrwrite(dev, uio, flag) 1036 dev_t dev; 1037 struct uio *uio; 1038 int flag; 1039 { 1040 return ENODEV; 1041 } 1042 1043 1044 1045 /* 1046 **++ 1047 ** FUNCTIONAL DESCRIPTION: 1048 ** 1049 ** scrread 1050 ** 1051 ** not supported 1052 ** 1053 ** FORMAL PARAMETERS: 1054 ** 1055 ** dev - input : Device identifier consisting of major and minor numbers. 1056 ** uio - input : Pointer to the user I/O information (ie. read buffer). 1057 ** flag - input : Information on how the I/O should be done (eg. blocking 1058 ** or non-blocking). 1059 ** 1060 ** IMPLICIT INPUTS: 1061 ** 1062 ** 1063 ** IMPLICIT OUTPUTS: 1064 ** 1065 ** none 1066 ** 1067 ** FUNCTION VALUE: 1068 ** 1069 ** Returns ENODEV 1070 ** 1071 ** SIDE EFFECTS: 1072 ** 1073 ** none 1074 **-- 1075 */ 1076 int 1077 scrread(dev, uio, flag) 1078 dev_t dev; 1079 struct uio *uio; 1080 int flag; 1081 { 1082 return ENODEV; 1083 } 1084 1085 1086 1087 1088 /* 1089 **++ 1090 ** FUNCTIONAL DESCRIPTION: 1091 ** 1092 ** scrpoll 1093 ** 1094 ** not supported 1095 ** 1096 ** FORMAL PARAMETERS: 1097 ** 1098 ** dev - input : Device identifier consisting of major and minor numbers. 1099 ** events -input: Events to poll for 1100 ** p - input : Process requesting the poll. 1101 ** 1102 ** IMPLICIT INPUTS: 1103 ** 1104 ** 1105 ** IMPLICIT OUTPUTS: 1106 ** 1107 ** none 1108 ** 1109 ** FUNCTION VALUE: 1110 ** 1111 ** Returns ENODEV 1112 ** 1113 ** SIDE EFFECTS: 1114 ** 1115 ** none 1116 **-- 1117 */ 1118 int 1119 scrpoll(dev, events, p) 1120 dev_t dev; 1121 int events; 1122 struct proc *p; 1123 { 1124 return ENODEV; 1125 } 1126 1127 1128 1129 1130 /* 1131 **++ 1132 ** FUNCTIONAL DESCRIPTION: 1133 ** 1134 ** scrstop 1135 ** 1136 ** should not be called 1137 ** 1138 ** FORMAL PARAMETERS: 1139 ** 1140 ** tp - Pointer to our tty structure. 1141 ** flag - Ignored. 1142 ** 1143 ** IMPLICIT INPUTS: 1144 ** 1145 ** none. 1146 ** 1147 ** IMPLICIT OUTPUTS: 1148 ** 1149 ** none. 1150 ** 1151 ** FUNCTION VALUE: 1152 ** 1153 ** none. 1154 ** 1155 ** SIDE EFFECTS: 1156 ** 1157 ** none. 1158 **-- 1159 */ 1160 void scrstop(tp, flag) 1161 struct tty *tp; 1162 int flag; 1163 { 1164 panic("scrstop: not implemented"); 1165 } 1166 1167 1168 1169 1170 /* 1171 **++ 1172 ** FUNCTIONAL DESCRIPTION: 1173 ** 1174 ** tty 1175 ** 1176 ** should not be called 1177 ** 1178 ** FORMAL PARAMETERS: 1179 ** 1180 ** dev - input : Device identifier consisting of major and minor numbers. 1181 ** 1182 ** IMPLICIT INPUTS: 1183 ** 1184 ** 1185 ** IMPLICIT OUTPUTS: 1186 ** 1187 ** none 1188 ** 1189 ** FUNCTION VALUE: 1190 ** 1191 ** null 1192 ** 1193 ** SIDE EFFECTS: 1194 ** 1195 ** none. 1196 **-- 1197 */ 1198 struct tty * scrtty(dev) 1199 dev_t dev; 1200 { 1201 panic("scrtty: not implemented"); 1202 return NULL; 1203 } 1204 1205 1206 1207 1208 1209 /* 1210 **++ 1211 ** FUNCTIONAL DESCRIPTION: 1212 ** 1213 ** This routine is responsible for performing I/O controls. 1214 ** 1215 ** There are 4 commands. Status, On, T0 and Off. 1216 ** 1217 ** Status checks to see if the card is inserted. This command 1218 ** does not use the state machines 1219 ** 1220 ** On turns the card on and gets the ATR sequence from the card. 1221 ** This command does use the state machines 1222 ** 1223 ** T0 is used to read and write the card. This command does use 1224 ** the state machines 1225 ** 1226 ** Off turns the card off. This command does not use the state 1227 ** machines. 1228 ** 1229 ** 1230 ** FORMAL PARAMETERS: 1231 ** 1232 ** dev - input : Device identifier consisting of major and minor numbers. 1233 ** cmd - input : The requested IOCTL command to be performed. 1234 ** See scrio.h for details 1235 ** 1236 ** 1237 ** Bit Position { 3322222222221111111111 1238 ** { 10987654321098765432109876543210 1239 ** Meaning | DDDLLLLLLLLLLLLLGGGGGGGGCCCCCCCC 1240 ** 1241 ** D - Command direction, in/out/both. 1242 ** L - Command argument length. 1243 ** G - Command group, 't' used for tty. 1244 ** C - Actual command enumeration. 1245 ** 1246 ** data - input/output : Direction depends on the command. 1247 ** flag - input : Not used by us but passed to line discipline and ttioctl 1248 ** p - input : pointer to proc structure of user. 1249 ** 1250 ** IMPLICIT INPUTS: 1251 ** 1252 ** none. 1253 ** 1254 ** IMPLICIT OUTPUTS: 1255 ** 1256 ** sc->masterS state of master state machine 1257 ** 1258 ** 1259 ** FUNCTION VALUE: 1260 ** 1261 ** ENOTTY if not correct ioctl 1262 ** 1263 ** 1264 ** SIDE EFFECTS: 1265 ** 1266 **-- 1267 */ 1268 int 1269 scrioctl(dev, cmd, data, flag, p) 1270 dev_t dev; 1271 u_long cmd; 1272 caddr_t data; 1273 int flag; 1274 struct proc *p; 1275 { 1276 int unit = SCRUNIT(dev); 1277 struct scr_softc* sc = scr_cd.cd_devs[unit]; 1278 1279 int error = 0; /* error value returned */ 1280 int masterDoneRetries= 0; /* nuber of times we looked at masterDone */ 1281 int done; /* local copy of masterDone */ 1282 1283 ScrStatus * pIoctlStatus; /* pointer to status ioctl */ 1284 ScrOff * pIoctlOff; /* pointer to off ioctl */ 1285 1286 u_int savedInts; /* saved interrupts */ 1287 int s; /* saved spl value */ 1288 1289 1290 1291 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO, 1292 ("scrioctl: called for device 0x%x, command 0x%lx, " 1293 "flag 0x%x\n", 1294 unit, cmd, flag)); 1295 1296 1297 1298 switch (cmd) 1299 { 1300 /* 1301 ** get the status of the card, ie is it in, in but off, in and on 1302 */ 1303 case SCRIOSTATUS: 1304 pIoctlStatus = (ScrStatus*)data; 1305 if (scrGetDetect()) 1306 { 1307 savedInts = disable_interrupts(I32_bit | F32_bit); 1308 if (sc->masterS == msIdleOn) 1309 { 1310 pIoctlStatus->status = CARD_ON; 1311 } 1312 else 1313 { 1314 ASSERT(sc->masterS == msIdleOff); 1315 pIoctlStatus->status = CARD_INSERTED; 1316 } 1317 restore_interrupts(savedInts); 1318 } 1319 1320 else 1321 { 1322 pIoctlStatus->status = CARD_REMOVED; 1323 } 1324 break; 1325 1326 1327 1328 /* 1329 ** turn the card on and get the ATR sequence 1330 */ 1331 case SCRIOON: 1332 sc->pIoctlOn = (ScrOn*)data; 1333 // acquire the hat lock. 1334 while (1) 1335 { 1336 s = splhigh(); 1337 if(!hatLock) 1338 { 1339 hatLock = TRUE; 1340 splx(s); 1341 break; 1342 } 1343 splx(s); 1344 1345 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1346 } 1347 1348 1349 // check to see if the card is in 1350 if(!scrGetDetect()) 1351 { 1352 initStates(sc); 1353 cardOff(sc); 1354 // do not call scrClkInit() as it is idle already 1355 sc->pIoctlOn->status = ERROR_CARD_REMOVED; 1356 } 1357 1358 1359 // check to see if we are already on 1360 else if(sc->masterS == msIdleOn) 1361 { 1362 sc->pIoctlOn->status = ERROR_CARD_ON; 1363 } 1364 1365 // card was in, card is off, so lets start it 1366 else 1367 { 1368 // set up the top half 1369 sc->masterDone = FALSE; 1370 sc->bigTrouble = FALSE; /* david/jim, remove this when the dust settles */ 1371 1372 1373 1374 // start bottom half 1375 scrClkStart (sc,400); 1376 savedInts = disable_interrupts(I32_bit | F32_bit); 1377 masterSM(sc,mcOn); 1378 restore_interrupts(savedInts); 1379 1380 1381 1382 // see if bottom half done 1383 while (1) 1384 { 1385 // check that we have not looped too many times 1386 if(masterDoneRetries >= MAX_FIQ_TIME * hz) 1387 { 1388 //printf("MAX_FIQ_TIME reached \n"); 1389 // big problems, so reset bottom 1390 savedInts = disable_interrupts(I32_bit | F32_bit); 1391 scrClkInit(); 1392 initStates(sc); 1393 cardOff(sc); 1394 sc->status = ERROR_CARD_REMOVED; 1395 sc->masterDone = TRUE; 1396 restore_interrupts(savedInts); 1397 // dont stop clock, done at bottom of case 1398 } 1399 masterDoneRetries ++; 1400 1401 // get done bit 1402 savedInts = disable_interrupts(I32_bit | F32_bit); 1403 done = sc->masterDone; 1404 restore_interrupts(savedInts); 1405 1406 // see if all done 1407 if(done) 1408 { 1409 break; 1410 } 1411 1412 1413 // wait for a while 1414 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1415 } 1416 1417 1418 // stop bottom half 1419 scrClkStop(); 1420 1421 1422 /* need to fix up count bits in non hat interrupt time, so */ 1423 if (sc->status == ERROR_OK) 1424 { 1425 sc->clkCountStartRecv = CLK_COUNT_START; 1426 sc->clkCountDataRecv = sc->clkCountStartRecv * START_2_DATA; 1427 sc->clkCountDataSend = CLK_COUNT_DATA; 1428 } 1429 1430 1431 1432 /* takes while to turn off all lines, so keep out of hat */ 1433 if (sc->masterS != msIdleOn) 1434 { 1435 cardOff(sc); 1436 } 1437 // get the status back from the state machine 1438 sc->pIoctlOn->status = sc->status; 1439 1440 1441 } 1442 1443 1444 // release the hat lock. 1445 s = splhigh(); 1446 ASSERT(hatlock); 1447 hatLock = FALSE; 1448 splx(s); 1449 1450 // david,jim hack to stop ioctl memcpy problem, to be removed when problem fixed ejg 1451 if (sc->pIoctlOn->status != ERROR_OK) 1452 { 1453 sc->pIoctlOn->atrLen = 0; 1454 } 1455 break; 1456 1457 1458 /* 1459 ** turn the card off 1460 */ 1461 case SCRIOOFF: 1462 pIoctlOff = (ScrOff*)data; 1463 // card off does not requires any state processing, so do work here 1464 initStates(sc); 1465 cardOff(sc); 1466 // do not call scrClkInit() as it is idle already 1467 pIoctlOff->status = ERROR_OK; 1468 break; 1469 1470 1471 /* 1472 ** do a T0 read or write 1473 */ 1474 case SCRIOT0: 1475 sc->pIoctlT0 = (ScrT0*)data; 1476 1477 // acquire the hat lock. 1478 while (1) 1479 { 1480 s = splhigh(); 1481 if(!hatLock) 1482 { 1483 hatLock = TRUE; 1484 splx(s); 1485 break; 1486 } 1487 splx(s); 1488 1489 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1490 } 1491 1492 // check to see if the card is in 1493 if(!scrGetDetect()) 1494 { 1495 initStates(sc); 1496 cardOff(sc); 1497 // do not call scrClkInit() as it is idle already 1498 sc->pIoctlT0->status = ERROR_CARD_REMOVED; 1499 } 1500 1501 1502 // check to see if card is off 1503 else if(sc->masterS == msIdleOff) 1504 { 1505 sc->pIoctlT0->status = ERROR_CARD_OFF; 1506 } 1507 1508 // card was in, card is on, lets do command 1509 else 1510 1511 { 1512 // set up the top half 1513 sc->masterDone = FALSE; 1514 sc->bigTrouble = FALSE; /* david/jim, remove this when the dust settles */ 1515 1516 // start bottom half 1517 scrClkStart (sc,sc->clkCountDataSend); 1518 savedInts = disable_interrupts(I32_bit | F32_bit); 1519 if (sc->pIoctlT0->writeBuffer) 1520 { 1521 masterSM(sc,mcT0DataSend); 1522 } 1523 else 1524 { 1525 masterSM(sc,mcT0DataRecv); 1526 } 1527 restore_interrupts(savedInts); 1528 1529 1530 // see if bottom half done 1531 while (1) 1532 { 1533 // check that we have not looped too many times 1534 if(masterDoneRetries >= MAX_FIQ_TIME * hz) 1535 { 1536 //printf("MAX_FIQ_TIME reached \n"); 1537 // big problems, so reset bottom 1538 savedInts = disable_interrupts(I32_bit | F32_bit); 1539 scrClkInit(); 1540 initStates(sc); 1541 cardOff(sc); 1542 sc->status = ERROR_CARD_REMOVED; 1543 sc->masterDone = TRUE; 1544 restore_interrupts(savedInts); 1545 } 1546 masterDoneRetries ++; 1547 1548 1549 // get done bit 1550 savedInts = disable_interrupts(I32_bit | F32_bit); 1551 done = sc->masterDone; 1552 restore_interrupts(savedInts); 1553 1554 1555 // see if all done 1556 if(done) 1557 { 1558 break; 1559 } 1560 1561 1562 // wait for a while 1563 tsleep(&tsleepIdent ,PZERO,"hat", 1); 1564 } 1565 1566 // stop bottom half 1567 scrClkStop(); 1568 1569 1570 1571 // get the status back from the state machine 1572 sc->pIoctlT0->status = sc->status; 1573 } 1574 1575 1576 // release the hat lock. 1577 s = splhigh(); 1578 hatLock = FALSE; 1579 splx(s); 1580 1581 1582 1583 // david, jim hack to stop ioctl memcpy problem, to be removed when problem fixed ejg 1584 if (sc->pIoctlT0->status != ERROR_OK) 1585 { 1586 sc->pIoctlT0->dataLen = 0; 1587 } 1588 break; 1589 1590 default: 1591 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO,("\t scrioctl: unknown command, ENOTTY \n")); 1592 error = ENOTTY; 1593 break; 1594 } 1595 1596 1597 1598 KERN_DEBUG (scrdebug, SCRIOCTL_DEBUG_INFO, 1599 ("scrioctl: exiting with sc->status %d\n", error)); 1600 return (error); 1601 } /* End scrioctl */ 1602 1603 1604 1605 1606 1607 1608 /* 1609 ** 1610 ** All functions below this point are the bottom half of the driver 1611 ** 1612 ** All are called during a FIQ, except for some functions in masterSM which 1613 ** provides the interface between the bottom half and top half of 1614 ** the driver (nb masterDone() helps masterSM() out with this interface 1615 ** between top and bottom parts of the driver. 1616 ** 1617 */ 1618 1619 1620 /* 1621 **++ 1622 ** FUNCTIONAL DESCRIPTION: 1623 ** 1624 ** masterSM 1625 ** 1626 ** This state machine implements the top level state control It 1627 ** receives commands to turn the card on, and do T0 reads and T0 writes 1628 ** from the scrioctl. It then calls mid level state machine to action 1629 ** these commands. 1630 ** 1631 ** This machine is the only machine to keep state between scrioctl calls. 1632 ** Between calls, the state will be either msIdleOff, or msIdleOn. msIdleOff 1633 ** indicates that no signals are applied to the card. msidleOn indicates that 1634 ** power and clock are supplied to the card, and that the card has performed 1635 ** a successful ATR sequence. 1636 ** 1637 ** This routine gets called during FIQ interrupts and from scrioctl. It is a 1638 ** requirement that the scrioctl disables interrupts before calling this function. 1639 ** 1640 ** NB:- there is no way for the machine to get from msIdleOn to msIdleOff. Since 1641 ** this is just a mater of turning all signals off and resetting state machines, 1642 ** scrioctl takes a shortcut and resets everything itself. Ie it hits everything 1643 ** with a big hammer!! 1644 ** 1645 ** FORMAL PARAMETERS: 1646 ** 1647 ** sc - Pointer to the softc structure. 1648 ** cmd - command to the state machine, can be from ioctl, or mid level SM 1649 ** 1650 ** IMPLICIT INPUTS: 1651 ** 1652 ** sc->masterS state of this machine 1653 ** sc->pIoctlT0 pointer to T0 ioctl 1654 ** 1655 ** IMPLICIT OUTPUTS: 1656 ** 1657 ** 1658 ** FUNCTION VALUE: 1659 ** 1660 ** nill 1661 ** 1662 ** SIDE EFFECTS: 1663 ** 1664 ** power and clock applied to card if successful ATR 1665 **-- 1666 */ 1667 static void masterSM(struct scr_softc * sc,int cmd) 1668 { 1669 1670 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1671 1672 switch (sc->masterS) 1673 { 1674 case msIdleOff: 1675 switch (cmd) 1676 { 1677 case mcOn: 1678 if (scrGetDetect()) 1679 { 1680 /* 1681 ** the card is off, and we want it on 1682 */ 1683 1684 /* set initial values */ 1685 sc->status = 0; 1686 sc->convention = CONVENTION_UNKOWN; 1687 sc->protocolType = 0; 1688 sc->N = N_DEFAULT; 1689 sc->Fi = Fi_DEFAULT; 1690 sc->Di = Di_DEFAULT; 1691 sc->Wi = Wi_DEFAULT; 1692 sc->cardFreq = CARD_FREQ_DEF; 1693 sc->clkCountStartRecv = CLK_COUNT_START; 1694 sc->clkCountDataRecv = sc->clkCountStartRecv * START_2_DATA; 1695 sc->clkCountDataSend = CLK_COUNT_DATA; 1696 1697 /* get coldResetSM to turn on power, clock, reset */ 1698 sc->masterS = msColdReset; 1699 coldResetSM(sc,crcStart); 1700 } 1701 else 1702 { 1703 /* card not inserted, so just set status and give up */ 1704 sc->status = ERROR_CARD_REMOVED; 1705 sc->masterDone = TRUE; 1706 } 1707 break; 1708 1709 default: 1710 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1711 break; 1712 } 1713 break; 1714 1715 case msColdReset: 1716 switch (cmd) 1717 { 1718 case mcColdReset: 1719 /* 1720 ** coldResetSM has turned on power, clock , reset 1721 ** tell ATRSM to get the ATR sequence from the card 1722 */ 1723 sc->masterS = msATR; 1724 ATRSM(sc,atrcStart); 1725 break; 1726 1727 default: 1728 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1729 break; 1730 } 1731 break; 1732 1733 case msATR: 1734 switch (cmd) 1735 { 1736 case mcATR: 1737 /* 1738 ** ATRSM has tried to get ATR sequence, so give 1739 ** back results to scrioctl. ATR sequence data 1740 ** was copied directly into ioctl data area, so 1741 ** no need to copy data 1742 */ 1743 if(sc->status == ERROR_OK) 1744 { 1745 sc->masterS = msIdleOn; 1746 } 1747 else 1748 { 1749 sc->masterS = msIdleOff; 1750 } 1751 sc->masterDone = TRUE; 1752 break; 1753 1754 1755 default: 1756 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1757 break; 1758 } 1759 break; 1760 1761 case msIdleOn: 1762 switch (cmd) 1763 { 1764 // nb there is no command to go to the IdleOff state. This 1765 // is a reset of the state machine, so is done in ioctl 1766 1767 case mcT0DataSend: 1768 /* 1769 ** card is on, and we want to T0 Send, so 1770 ** as t0SendSM to do work 1771 */ 1772 sc->status = ERROR_OK; 1773 sc->masterS = msT0Send; 1774 t0SendSM(sc,t0scStart); 1775 break; 1776 1777 case mcT0DataRecv: 1778 /* 1779 ** card is on, and we want to T0 Recv, so 1780 ** as t0RecvSM to do work 1781 */ 1782 sc->status = ERROR_OK; 1783 sc->masterS = msT0Recv; 1784 t0RecvSM(sc,t0rcStart); 1785 break; 1786 1787 default: 1788 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1789 break; 1790 } 1791 1792 break; 1793 1794 case msT0Send: 1795 switch (cmd) 1796 { 1797 case mcT0Send: 1798 /* 1799 ** t0SendSM has tried to send , so lets give back results 1800 */ 1801 sc->masterS = msIdleOn; 1802 sc->masterDone = TRUE; 1803 break; 1804 1805 default: 1806 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1807 break; 1808 } 1809 break; 1810 1811 case msT0Recv: 1812 switch (cmd) 1813 { 1814 case mcT0Recv: 1815 /* 1816 ** t0RecvSM has tried to recv , so lets give back results 1817 ** data was written directly into ioctl data area, so we 1818 ** do not need to copy any data 1819 */ 1820 sc->pIoctlT0->dataLen = sc->dataCount; 1821 sc->masterS = msIdleOn; 1822 sc->masterDone = TRUE; 1823 break; 1824 1825 default: 1826 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1827 break; 1828 } 1829 break; 1830 1831 default: 1832 INVALID_STATE_CMD(sc,sc->masterS,cmd); 1833 break; 1834 1835 } 1836 } 1837 1838 1839 1840 1841 /* 1842 **++ 1843 ** FUNCTIONAL DESCRIPTION: 1844 ** 1845 ** t0SendSM 1846 ** 1847 ** This is the T=0 Send State Machine. It is responsible 1848 ** for performing the send part of the ISO 7816-3 T=0 1849 ** protocol. It is mid level protocol state machine. 1850 ** 1851 ** Once started, this machine is driven entirely via the 1852 ** FIQ/timeout structure . 1853 ** 1854 ** 1855 ** 1856 ** FORMAL PARAMETERS: 1857 ** 1858 ** sc - Pointer to the softc structure. 1859 ** cmd - command to this machine 1860 ** 1861 ** IMPLICIT INPUTS: 1862 ** 1863 ** sc->t0SendS state of this machine 1864 ** sc->pIoctlT0->command command to send to card 1865 ** sc->pIoctlT0->data data to send to card 1866 ** 1867 ** IMPLICIT OUTPUTS: 1868 ** 1869 ** sc->status error status from this machine 1870 ** sc->pIoctlT0->sw1 command status from card 1871 ** sc->pIoctlT0->sw2 command status from card 1872 ** sc->status error status from this machine 1873 ** 1874 ** FUNCTION VALUE: 1875 ** 1876 ** nill 1877 ** 1878 ** SIDE EFFECTS: 1879 ** 1880 ** nill 1881 **-- 1882 */ 1883 static void t0SendSM (struct scr_softc * sc, int cmd) 1884 { 1885 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 1886 /* 1887 ** check for major failures that are common to most states 1888 */ 1889 if (cmd == t0scTWorkWaiting || 1890 cmd == gcT0RecvByteErr || 1891 cmd == gcT0SendByteErr 1892 ) 1893 { 1894 switch(cmd) 1895 { 1896 case t0scTWorkWaiting: 1897 ASSERT(sc->t0SendS != t0ssIdle); 1898 1899 /* kill all lower machines */ 1900 t0SendByteSM(sc,t0sbcAbort); 1901 t0RecvByteSM(sc,t0rbcAbort); 1902 1903 /* set status */ 1904 sc->status = ERROR_WORK_WAITING; 1905 break; 1906 1907 case gcT0RecvByteErr: // fall through 1908 case gcT0SendByteErr: 1909 scrUntimeout(t0SendSM, sc, t0scTWorkWaiting); 1910 // done set status, already set in lower machine 1911 break; 1912 1913 default: 1914 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1915 break; 1916 } 1917 1918 /* change states */ 1919 sc->t0SendS = t0ssIdle; 1920 masterSM(sc,mcT0Send); 1921 return; 1922 } 1923 1924 switch (sc->t0SendS) 1925 { 1926 case t0ssIdle: 1927 switch (cmd) 1928 { 1929 case t0scStart: 1930 /* set initial values */ 1931 sc->t0SendS = t0ssSendHeader; 1932 sc->t0ByteParent = t0SendSM; 1933 sc->commandCount = 0; 1934 sc->dataCount = 0; 1935 sc->dataMax = sc->pIoctlT0->command[CMD_BUF_DATA_LEN_OFF]; 1936 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1937 1938 // get a byte 1939 t0SendByteSM(sc,t0sbcStart); 1940 break; 1941 1942 default: 1943 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1944 break; 1945 } 1946 break; 1947 1948 case t0ssSendHeader: 1949 switch (cmd) 1950 { 1951 case gcT0SendByte: 1952 sc->commandCount++; 1953 if (sc->commandCount < CMD_BUF_LEN) 1954 { 1955 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 1956 t0SendByteSM(sc,t0sbcStart); 1957 } 1958 else 1959 { 1960 ASSERT(sc->commandCount == CMD_BUF_LEN); 1961 1962 sc->t0SendS = t0ssRecvProcedure; 1963 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 1964 t0RecvByteSM(sc,t0rbcStart); 1965 } 1966 break; 1967 1968 default: 1969 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 1970 break; 1971 } 1972 break; 1973 1974 case t0ssRecvProcedure: 1975 switch (cmd) 1976 { 1977 case gcT0RecvByte: 1978 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 1979 /* see if we should send all remaining bytes */ 1980 if ( (sc->dataByte == sc->pIoctlT0->command[CMD_BUF_INS_OFF]) || 1981 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0x01)) ) 1982 { 1983 ASSERT(sc->dataCount < sc->dataMax); 1984 sc->t0SendS = t0ssSendData; 1985 sc->dataByte = sc->pIoctlT0->data[sc->dataCount]; 1986 t0SendByteSM(sc,t0sbcStart); 1987 sc->dataCount++; 1988 } 1989 1990 /* see if we should send one data byte */ 1991 else if ((sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFF)) || 1992 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFE)) ) 1993 { 1994 ASSERT(sc->dataCount < sc->dataMax); 1995 sc->t0SendS = t0ssSendByte; 1996 sc->dataByte = sc->pIoctlT0->data[ sc->dataCount]; 1997 t0SendByteSM(sc,t0sbcStart); 1998 sc->dataCount++; 1999 } 2000 2001 /* see if we should extend the work waiting period */ 2002 else if (sc->dataByte == 0x60) 2003 { 2004 t0RecvByteSM(sc,t0rbcStart); 2005 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 2006 } 2007 2008 #ifdef ORIGINAL_SW1_CODE /* XXX XXX XXX cgd */ 2009 /* see if we have a SW1 byte */ 2010 else if ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) 2011 && 2012 sc->dataByte != 0x60) 2013 #else /* XXX XXX XXX cgd */ 2014 /* see if we have a SW1 byte */ 2015 else if ( ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) ) 2016 && 2017 sc->dataByte != 0x60) 2018 #endif /* XXX XXX XXX cgd */ 2019 { 2020 sc->pIoctlT0->sw1 = sc->dataByte; 2021 sc->t0SendS = t0ssRecvSW2; 2022 t0RecvByteSM(sc,t0rbcStart); 2023 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 2024 } 2025 2026 /* got bad data byte, log error and get out */ 2027 else 2028 { 2029 sc->status = ERROR_BAD_PROCEDURE_BYTE; 2030 2031 /* change state */ 2032 sc->t0SendS = t0ssIdle; 2033 masterSM(sc,mcT0Send); 2034 } 2035 break; 2036 2037 default: 2038 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 2039 break; 2040 } 2041 break; 2042 2043 case t0ssSendByte: 2044 switch (cmd) 2045 { 2046 case gcT0SendByte: 2047 if (sc->dataCount < sc->dataMax) 2048 { 2049 sc->t0SendS = t0ssRecvProcedure; 2050 } 2051 2052 /* wait for sw1 byte */ 2053 else 2054 { 2055 ASSERT(sc->dataCount == sc->dataMax); 2056 sc->t0SendS = t0ssRecvSW1; 2057 } 2058 2059 // ask for another byte 2060 t0RecvByteSM(sc,t0rbcStart); 2061 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 2062 break; 2063 2064 default: 2065 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 2066 break; 2067 } 2068 break; 2069 2070 case t0ssSendData: 2071 switch (cmd) 2072 { 2073 case gcT0SendByte: 2074 /* send data */ 2075 if (sc->dataCount < sc->dataMax) 2076 { 2077 sc->t0SendS = t0ssSendData; 2078 sc->dataByte = sc->pIoctlT0->data[ sc->dataCount]; 2079 t0SendByteSM(sc,t0sbcStart); 2080 sc->dataCount++; 2081 } 2082 2083 /* wait for sw1 byte */ 2084 else 2085 { 2086 ASSERT(sc->dataCount == sc->dataMax); 2087 sc->t0SendS = t0ssRecvSW1; 2088 t0RecvByteSM(sc,t0rbcStart); 2089 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 2090 } 2091 break; 2092 2093 default: 2094 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 2095 break; 2096 } 2097 break; 2098 2099 case t0ssRecvSW1: 2100 switch (cmd) 2101 { 2102 case gcT0RecvByte: 2103 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 2104 sc->pIoctlT0->sw1 = sc->dataByte; 2105 sc->t0SendS = t0ssRecvSW2; 2106 t0RecvByteSM(sc,t0rbcStart); 2107 scrTimeout(t0SendSM,sc,t0scTWorkWaiting,T_WORK_WAITING); 2108 break; 2109 default: 2110 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 2111 break; 2112 } 2113 break; 2114 2115 case t0ssRecvSW2: 2116 switch (cmd) 2117 { 2118 case gcT0RecvByte: 2119 scrUntimeout(t0SendSM, sc,t0scTWorkWaiting); 2120 sc->pIoctlT0->sw2 = sc->dataByte; 2121 sc->t0SendS = t0ssIdle; 2122 masterSM(sc,mcT0Send); 2123 break; 2124 2125 default: 2126 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 2127 break; 2128 } 2129 break; 2130 2131 default: 2132 INVALID_STATE_CMD(sc, sc->t0SendS,cmd); 2133 break; 2134 } 2135 } 2136 2137 2138 2139 /* 2140 **++ 2141 ** FUNCTIONAL DESCRIPTION: 2142 ** 2143 ** t0RecvSM 2144 ** 2145 ** This is the T=0 Recv State Machine. It is responsible 2146 ** for performing the recv part of the ISO 7816-3 T=0 2147 ** protocol. It is mid level protocol state machine. 2148 ** 2149 ** Once started, this machine is driven entirely via the 2150 ** FIQ/timeout structure . 2151 ** 2152 ** FORMAL PARAMETERS: 2153 ** 2154 ** sc - Pointer to the softc structure. 2155 ** cmd - command to this machine 2156 ** 2157 ** IMPLICIT INPUTS: 2158 ** 2159 ** sc->t0RecvS state of this machine 2160 ** sc->pIoctlT0->command command to send to card 2161 ** 2162 ** IMPLICIT OUTPUTS: 2163 ** 2164 ** sc->pIoctlT0->data data from card 2165 ** sc->pIoctlT0->dataLen size of data from card 2166 ** sc->pIoctlT0->sw1 command status from card 2167 ** sc->pIoctlT0->sw2 command status from card 2168 ** sc->status error status from this machine 2169 ** 2170 ** FUNCTION VALUE: 2171 ** 2172 ** nill 2173 ** 2174 ** SIDE EFFECTS: 2175 ** 2176 ** nill 2177 **-- 2178 */ 2179 static void t0RecvSM (struct scr_softc * sc,int cmd) 2180 { 2181 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2182 2183 /* 2184 ** check for major failures that are common to most states 2185 */ 2186 if (cmd == t0rcTWorkWaiting || 2187 cmd == gcT0RecvByteErr || 2188 cmd == gcT0SendByteErr ) 2189 2190 { 2191 switch(cmd) 2192 { 2193 2194 case t0rcTWorkWaiting: 2195 ASSERT(sc->t0RecvS != t0rsIdle); 2196 2197 /* kill all lower level machines */ 2198 t0SendByteSM(sc,t0sbcAbort); 2199 t0RecvByteSM(sc,t0rbcAbort); 2200 2201 /* set status */ 2202 sc->status = ERROR_WORK_WAITING; 2203 break; 2204 2205 case gcT0RecvByteErr: // fall through 2206 case gcT0SendByteErr: 2207 /* kill all the timers */ 2208 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2209 break; 2210 2211 default: 2212 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2213 break; 2214 2215 } 2216 2217 2218 2219 /* change state */ 2220 sc->t0RecvS = t0rsIdle; 2221 masterSM(sc,mcT0Recv); 2222 2223 /* all done */ 2224 return; 2225 } 2226 2227 switch (sc->t0RecvS) 2228 { 2229 case t0rsIdle: 2230 switch (cmd) 2231 { 2232 case t0rcStart: 2233 /* set initial values */ 2234 sc->t0RecvS = t0rsSendHeader; 2235 sc->t0ByteParent = t0RecvSM; 2236 sc->commandCount = 0; 2237 sc->dataCount = 0; 2238 sc->dataMax = sc->pIoctlT0->command[CMD_BUF_DATA_LEN_OFF]; 2239 if (sc->dataMax == 0) 2240 { 2241 sc->dataMax = 256; 2242 } 2243 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 2244 t0SendByteSM(sc,t0sbcStart); 2245 break; 2246 2247 default: 2248 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2249 break; 2250 } 2251 break; 2252 2253 case t0rsSendHeader: 2254 switch (cmd) 2255 { 2256 case gcT0SendByte: 2257 sc->commandCount++; 2258 if (sc->commandCount < CMD_BUF_LEN) 2259 { 2260 sc->dataByte = sc->pIoctlT0->command[sc->commandCount]; 2261 t0SendByteSM(sc,t0sbcStart); 2262 } 2263 else 2264 { 2265 ASSERT(sc->commandCount == CMD_BUF_LEN); 2266 2267 sc->t0RecvS = t0rsRecvProcedure; 2268 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2269 t0RecvByteSM(sc,t0rbcStart); 2270 } 2271 break; 2272 2273 default: 2274 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2275 break; 2276 } 2277 break; 2278 2279 case t0rsRecvProcedure: 2280 switch (cmd) 2281 { 2282 case gcT0RecvByte: 2283 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2284 2285 /* see if we should recv all remaining bytes */ 2286 if ( (sc->dataByte == sc->pIoctlT0->command[CMD_BUF_INS_OFF]) || 2287 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0x01)) ) 2288 { 2289 ASSERT(sc->dataCount < sc->dataMax); 2290 2291 sc->t0RecvS = t0rsRecvData; 2292 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2293 t0RecvByteSM(sc,t0rbcStart); 2294 } 2295 2296 /* see if we should send one data byte */ 2297 else if ((sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFF)) || 2298 (sc->dataByte == (sc->pIoctlT0->command[CMD_BUF_INS_OFF] ^ 0xFE)) ) 2299 { 2300 ASSERT(sc->dataCount < sc->dataMax); 2301 sc->t0RecvS = t0rsRecvByte; 2302 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2303 t0RecvByteSM(sc,t0rbcStart); 2304 } 2305 2306 /* see if we should extend the work waiting period */ 2307 else if (sc->dataByte == 0x60) 2308 { 2309 t0RecvByteSM(sc,t0rbcStart); 2310 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2311 } 2312 2313 #ifdef ORIGINAL_SW1_CODE /* XXX XXX XXX cgd */ 2314 /* see if we have a SW1 byte */ 2315 else if ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) 2316 && 2317 sc->dataByte != 0x60) 2318 #else /* XXX XXX XXX cgd */ 2319 /* see if we have a SW1 byte */ 2320 else if ( ( ((sc->dataByte & 0xf0) == 0x60) || ((sc->dataByte & 0xf0) == 0x90) ) 2321 && 2322 sc->dataByte != 0x60) 2323 #endif /* XXX XXX XXX cgd */ 2324 { 2325 sc->pIoctlT0->sw1 = sc->dataByte; 2326 sc->t0RecvS = t0rsRecvSW2; 2327 t0RecvByteSM(sc,t0rbcStart); 2328 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2329 } 2330 2331 /* got bad data byte, log error and get out */ 2332 else 2333 { 2334 sc->status = ERROR_BAD_PROCEDURE_BYTE; 2335 2336 /* change state */ 2337 sc->t0RecvS = t0rsIdle; 2338 masterSM(sc,mcT0Recv); 2339 } 2340 break; 2341 2342 default: 2343 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2344 break; 2345 } 2346 break; 2347 2348 case t0rsRecvByte: 2349 switch (cmd) 2350 { 2351 case gcT0RecvByte: 2352 /* clock in byte */ 2353 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2354 sc->pIoctlT0->data[sc->dataCount] = sc->dataByte; 2355 sc->dataCount++; 2356 2357 2358 if (sc->dataCount < sc->dataMax) 2359 { 2360 /* get procedure byte */ 2361 sc->t0RecvS = t0rsRecvProcedure; 2362 } 2363 2364 else 2365 { 2366 ASSERT(sc->dataCount == sc->dataMax); 2367 sc->t0RecvS = t0rsRecvSW1; 2368 } 2369 2370 // ask for another byte 2371 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2372 t0RecvByteSM(sc,t0rbcStart); 2373 break; 2374 2375 default: 2376 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2377 break; 2378 } 2379 break; 2380 2381 case t0rsRecvData: 2382 switch (cmd) 2383 { 2384 case gcT0RecvByte: 2385 /* clock in data */ 2386 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2387 sc->pIoctlT0->data[sc->dataCount] = sc->dataByte; 2388 sc->dataCount++; 2389 2390 /* decide if we have all data */ 2391 if (sc->dataCount >= sc->dataMax) 2392 { 2393 KERN_DEBUG (scrdebug, T0_RECV_SM_DEBUG_INFO,("\t\tt0RecvSM: changing state to t0rsRecvSW1\n",sc->dataByte)); 2394 ASSERT(sc->dataCount == sc->dataMax); 2395 sc->t0RecvS = t0rsRecvSW1; 2396 } 2397 2398 /* ask for another byte */ 2399 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2400 t0RecvByteSM(sc,t0rbcStart); 2401 break; 2402 2403 default: 2404 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2405 break; 2406 } 2407 break; 2408 2409 case t0rsRecvSW1: 2410 switch (cmd) 2411 { 2412 case gcT0RecvByte: 2413 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2414 sc->pIoctlT0->sw1 = sc->dataByte; 2415 2416 sc->t0RecvS = t0rsRecvSW2; 2417 t0RecvByteSM(sc,t0rbcStart); 2418 scrTimeout(t0RecvSM,sc,t0rcTWorkWaiting,T_WORK_WAITING); 2419 break; 2420 default: 2421 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2422 break; 2423 } 2424 break; 2425 2426 case t0rsRecvSW2: 2427 switch (cmd) 2428 { 2429 case gcT0RecvByte: 2430 scrUntimeout(t0RecvSM, sc,t0rcTWorkWaiting); 2431 sc->pIoctlT0->sw2 = sc->dataByte; 2432 2433 sc->t0RecvS = t0rsIdle; 2434 masterSM(sc,mcT0Recv); 2435 break; 2436 2437 default: 2438 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2439 break; 2440 } 2441 break; 2442 2443 default: 2444 INVALID_STATE_CMD(sc, sc->t0RecvS,cmd); 2445 break; 2446 } 2447 } 2448 2449 2450 /* 2451 **++ 2452 ** FUNCTIONAL DESCRIPTION: 2453 ** 2454 ** coldResetSM 2455 ** 2456 ** This state machine switches on the power, clock and reset pins 2457 ** in the correct order/timing. 2458 ** It is a low level bit-bashing state machine. 2459 ** 2460 ** 2461 ** FORMAL PARAMETERS: 2462 ** 2463 ** sc - Pointer to the softc structure. 2464 ** cmd - command to this machine 2465 ** 2466 ** IMPLICIT INPUTS: 2467 ** 2468 ** sc->coldResetS state of this machine 2469 ** 2470 ** IMPLICIT OUTPUTS: 2471 ** 2472 ** nill 2473 ** 2474 ** FUNCTION VALUE: 2475 ** 2476 ** nill 2477 ** 2478 ** SIDE EFFECTS: 2479 ** 2480 ** signals to card are on 2481 **-- 2482 */ 2483 static void coldResetSM(struct scr_softc * sc,int cmd) 2484 { 2485 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2486 2487 switch (sc->coldResetS) 2488 { 2489 case crsIdle: 2490 switch (cmd) 2491 { 2492 case crcStart: 2493 scrSetReset(TRUE); 2494 scrSetClock(TRUE); 2495 scrSetDataHighZ(); 2496 scrSetPower(TRUE); 2497 2498 /* start a t2 timer */ 2499 scrTimeout(coldResetSM,sc,crcT2,T_t2); 2500 sc->coldResetS = crsT2Wait; 2501 break; 2502 2503 default: 2504 INVALID_STATE_CMD(sc,sc->masterS,cmd); 2505 break; 2506 } 2507 break; 2508 2509 case crsT2Wait: 2510 switch (cmd) 2511 { 2512 case crcT2: 2513 /* turn off rst */ 2514 scrSetReset(FALSE); 2515 2516 /* tell master state machine that we are all done */ 2517 sc->coldResetS = crsIdle; 2518 masterSM(sc,mcColdReset); 2519 break; 2520 2521 default: 2522 INVALID_STATE_CMD(sc,sc->masterS,cmd); 2523 break; 2524 } 2525 break; 2526 2527 2528 default: 2529 INVALID_STATE_CMD(sc,sc->coldResetS,cmd); 2530 break; 2531 } 2532 } 2533 2534 /* 2535 **++ 2536 ** FUNCTIONAL DESCRIPTION: 2537 ** 2538 ** ATRSM 2539 ** 2540 ** This is the Answer To Reset State Machine. It is responsible 2541 ** for performing the Answer To Reset as specified in ISO 7816-3. 2542 ** It is mid level protocol state machine. 2543 ** 2544 ** Once started, this machine is driven entirely via the 2545 ** FIQ/timeout structure. 2546 ** 2547 ** 2548 ** During the first byte, we have to check if the card is operating 2549 ** at full speed or half speed. The first couple of bits are 2550 ** checked to see if it is 1/2 speed, and if so, the clock is changed 2551 ** and the state adjustes 2552 ** 2553 ** At the end of the first byte we have to determin the logic being 2554 ** used by the card, ie is it active high/low and msb/lsb. 2555 ** 2556 ** 2557 ** FORMAL PARAMETERS: 2558 ** 2559 ** sc - Pointer to the softc structure. 2560 ** cmd - command to this machine 2561 ** 2562 ** IMPLICIT INPUTS: 2563 ** 2564 ** sc->pIoctlAtr->atr data from card 2565 ** sc->pIoctlT0->sw1 command status from card 2566 ** sc->pIoctlT0->sw2 command status from card 2567 ** sc->status error status from this machine 2568 ** 2569 ** IMPLICIT OUTPUTS: 2570 ** 2571 ** sc->pIoctlOn->atrBuf data from ATR sequence 2572 ** sc->pIoctlOn->atrLen size of data from ATR sequence 2573 ** sc->status error status from this machine 2574 ** 2575 ** 2576 ** FUNCTION VALUE: 2577 ** 2578 ** nill 2579 ** 2580 ** SIDE EFFECTS: 2581 ** 2582 ** nill 2583 **-- 2584 */ 2585 static void ATRSM (struct scr_softc * sc,int cmd) 2586 { 2587 int lc; 2588 int tck; 2589 2590 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 2591 2592 /* 2593 ** check for major failures that are common to most states 2594 */ 2595 if (cmd == atrcT3 || 2596 cmd == atrcTWorkWaiting || 2597 cmd == gcT0RecvByteErr 2598 ) 2599 { 2600 switch(cmd) 2601 { 2602 case atrcT3: 2603 scrUntimeout (ATRSM,sc,atrcTWorkWaiting); 2604 sc->status = ERROR_ATR_T3; 2605 t0RecvByteSM(sc,t0rbcAbort); 2606 break; 2607 2608 case atrcTWorkWaiting: 2609 scrUntimeout (ATRSM,sc,atrcT3); 2610 sc->status = ERROR_WORK_WAITING; 2611 t0RecvByteSM(sc,t0rbcAbort); 2612 break; 2613 2614 case gcT0RecvByteErr: 2615 scrUntimeout (ATRSM,sc,atrcT3); 2616 scrUntimeout (ATRSM,sc,atrcTWorkWaiting); 2617 /* done set status, its already set */ 2618 break; 2619 2620 default: 2621 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2622 break; 2623 } 2624 2625 /* change state */ 2626 sc->ATRS = atrsIdle; 2627 masterSM(sc,mcATR); 2628 return; 2629 } 2630 2631 switch (sc->ATRS) 2632 { 2633 case atrsIdle: 2634 switch (cmd) 2635 { 2636 case atrcStart: 2637 /* lets start looking */ 2638 sc->ATRS = atrsTS; 2639 sc->pIoctlOn->atrLen = 0; 2640 sc->t0ByteParent = ATRSM; 2641 scrTimeout(ATRSM,sc,atrcT3,T_t3 *2); /* by 2 to accomodate 1/2 freq cards */ 2642 t0RecvByteSM(sc,t0rbcStart); 2643 break; 2644 2645 default: 2646 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2647 break; 2648 } 2649 break; 2650 2651 case atrsTS: 2652 switch (cmd) 2653 { 2654 case gcT0RecvByte: 2655 scrUntimeout(ATRSM,sc,atrcT3); 2656 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2657 sc->pIoctlOn->atrLen++; 2658 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2659 { 2660 #ifdef SCR_DEBUG 2661 DEBUGGER; 2662 #endif 2663 sc->status = ERROR_ATR_TCK; 2664 sc->ATRS = atrsIdle; 2665 masterSM(sc,mcATR); 2666 } 2667 else 2668 { 2669 /* move onto recv T0 */ 2670 sc->ATRS = atrsT0; 2671 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2672 t0RecvByteSM(sc,t0rbcStart); 2673 } 2674 break; 2675 2676 default: 2677 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2678 break; 2679 } 2680 break; 2681 2682 case atrsT0: 2683 switch (cmd) 2684 { 2685 case gcT0RecvByte: 2686 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2687 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2688 sc->pIoctlOn->atrLen++; 2689 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2690 { 2691 #ifdef SCR_DEBUG 2692 printf("atrLen >= ATR_BUF_MAX\n"); 2693 DEBUGGER; 2694 #endif 2695 sc->status = ERROR_ATR_TCK; 2696 sc->ATRS = atrsIdle; 2697 masterSM(sc,mcATR); 2698 } 2699 else 2700 { 2701 /* store Y & K */ 2702 sc->atrY = sc->dataByte & 0xf0; 2703 sc->atrK = sc->dataByte & 0x0f; 2704 2705 sc->atrTABCDx = 1; 2706 sc->atrKCount = 1; 2707 2708 /* if there are no TDx following set T0 protocol */ 2709 if (ISCLR(sc->atrY,ATR_Y_TD)) 2710 { 2711 sc->protocolType = PROTOCOL_T0; 2712 } 2713 2714 2715 if (sc->atrY) 2716 { 2717 2718 sc->ATRS = atrsTABCD; 2719 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2720 t0RecvByteSM(sc,t0rbcStart); 2721 } 2722 2723 else if (sc->atrK) 2724 { 2725 sc->ATRS = atrsTK; 2726 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2727 t0RecvByteSM(sc,t0rbcStart); 2728 } 2729 2730 else if (sc->protocolType != PROTOCOL_T0) 2731 { 2732 sc->ATRS = atrsTCK; 2733 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2734 t0RecvByteSM(sc,t0rbcStart); 2735 } 2736 2737 else /* got all of ATR */ 2738 { 2739 sc->ATRS = atrsIdle; 2740 masterSM(sc,mcATR); 2741 } 2742 } 2743 break; 2744 2745 2746 default: 2747 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2748 break; 2749 } 2750 break; 2751 2752 2753 case atrsTABCD: 2754 switch (cmd) 2755 { 2756 case gcT0RecvByte: 2757 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2758 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2759 sc->pIoctlOn->atrLen++; 2760 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2761 { 2762 #ifdef SCR_DEBUG 2763 printf("atrLen >= ATR_BUF_MAX\n"); 2764 DEBUGGER; 2765 #endif 2766 sc->status = ERROR_ATR_TCK; 2767 sc->ATRS = atrsIdle; 2768 masterSM(sc,mcATR); 2769 } 2770 else 2771 { 2772 if (sc->atrY & ATR_Y_TA) 2773 { 2774 sc->atrY &= ~ATR_Y_TA; 2775 if (sc->atrTABCDx == 1) 2776 { 2777 sc->Fi = FI2Fi[((sc->dataByte >> 4) & 0x0f)]; 2778 if (sc->Fi == 0) 2779 { 2780 sc->status = ERROR_ATR_FI_INVALID; 2781 sc->Fi = Fi_DEFAULT; 2782 } 2783 2784 sc->Di = DI2Di[(sc->dataByte & 0x0f)]; 2785 if (sc->Di == 0) 2786 { 2787 sc->status = ERROR_ATR_DI_INVALID; 2788 sc->Di = Di_DEFAULT; 2789 } 2790 2791 } 2792 } 2793 2794 else if (sc->atrY & ATR_Y_TB) 2795 { 2796 sc->atrY &= ~ATR_Y_TB; 2797 } 2798 2799 else if (sc->atrY & ATR_Y_TC) 2800 { 2801 sc->atrY &= ~ATR_Y_TC; 2802 if (sc->atrTABCDx == 1) 2803 { 2804 sc->N = sc->dataByte; 2805 } 2806 2807 if (sc->atrTABCDx == 2) 2808 { 2809 sc->Wi = sc->dataByte; 2810 } 2811 } 2812 2813 else 2814 { 2815 ASSERT(sc->atrY & ATR_Y_TD); 2816 sc->atrY &= ~ATR_Y_TD; 2817 2818 /* copy across the y section of TD */ 2819 sc->atrY = sc->dataByte; 2820 sc->atrY &= 0xf0; 2821 2822 /* step to the next group of TABCD */ 2823 sc->atrTABCDx++; 2824 2825 /* store protocols */ 2826 sc->protocolType = (1 << (sc->dataByte &0x0f)); 2827 } 2828 2829 2830 /* see what we should do next */ 2831 if (sc->atrY) 2832 { 2833 /* just stay in the same state */ 2834 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2835 t0RecvByteSM(sc,t0rbcStart); 2836 } 2837 2838 else if (sc->atrK) 2839 { 2840 sc->ATRS = atrsTK; 2841 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2842 t0RecvByteSM(sc,t0rbcStart); 2843 } 2844 2845 else if (sc->protocolType != PROTOCOL_T0) 2846 { 2847 sc->ATRS = atrsTCK; 2848 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2849 t0RecvByteSM(sc,t0rbcStart); 2850 } 2851 2852 else /* got all of ATR */ 2853 { 2854 sc->ATRS = atrsIdle; 2855 masterSM(sc,mcATR); 2856 } 2857 } 2858 2859 break; 2860 2861 2862 default: 2863 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2864 break; 2865 } 2866 break; 2867 2868 case atrsTK: 2869 switch (cmd) 2870 { 2871 case gcT0RecvByte: 2872 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2873 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2874 sc->pIoctlOn->atrLen++; 2875 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2876 { 2877 #ifdef SCR_DEBUG 2878 printf("atrLen >= ATR_BUF_MAX\n"); 2879 DEBUGGER; 2880 #endif 2881 sc->status = ERROR_ATR_TCK; 2882 sc->ATRS = atrsIdle; 2883 masterSM(sc,mcATR); 2884 } 2885 else 2886 { 2887 2888 if (sc->atrKCount < sc->atrK) 2889 { 2890 sc->atrKCount++; 2891 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2892 t0RecvByteSM(sc,t0rbcStart); 2893 } 2894 2895 2896 else if (sc->protocolType != PROTOCOL_T0) 2897 { 2898 sc->ATRS = atrsTCK; 2899 scrTimeout(ATRSM,sc,atrcTWorkWaiting,T_WORK_WAITING); 2900 t0RecvByteSM(sc,t0rbcStart); 2901 } 2902 2903 else /* got all of ATR */ 2904 { 2905 sc->ATRS = atrsIdle; 2906 masterSM(sc,mcATR); 2907 } 2908 } 2909 break; 2910 2911 default: 2912 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2913 break; 2914 } 2915 break; 2916 2917 case atrsTCK: 2918 switch (cmd) 2919 { 2920 case gcT0RecvByte: 2921 scrUntimeout(ATRSM,sc,atrcTWorkWaiting); 2922 sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen] = sc->dataByte; 2923 sc->pIoctlOn->atrLen++; 2924 if(sc->pIoctlOn->atrLen >= ATR_BUF_MAX) 2925 { 2926 #ifdef SCR_DEBUG 2927 printf("atrLen >= ATR_BUF_MAX\n"); 2928 DEBUGGER; 2929 #endif 2930 sc->status = ERROR_ATR_TCK; 2931 sc->ATRS = atrsIdle; 2932 masterSM(sc,mcATR); 2933 } 2934 else 2935 { 2936 tck = 0; 2937 for (lc = 1; lc < sc->pIoctlOn->atrLen-1; lc++) 2938 { 2939 tck ^= sc->pIoctlOn->atrBuf[lc]; 2940 } 2941 2942 if (tck == sc->pIoctlOn->atrBuf[sc->pIoctlOn->atrLen-1]) 2943 { 2944 sc->ATRS = atrsIdle; 2945 masterSM(sc,mcATR); 2946 } 2947 else 2948 { 2949 sc->status = ERROR_ATR_TCK; 2950 sc->ATRS = atrsIdle; 2951 masterSM(sc,mcATR); 2952 } 2953 } 2954 break; 2955 2956 default: 2957 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2958 break; 2959 } 2960 break; 2961 2962 2963 2964 default: 2965 INVALID_STATE_CMD(sc,sc->ATRS,cmd); 2966 break; 2967 } 2968 } 2969 2970 2971 2972 /* 2973 **++ 2974 ** FUNCTIONAL DESCRIPTION: 2975 ** 2976 ** t0RecvByteSM 2977 ** 2978 ** This state machine attempts to read 1 byte from a card. 2979 ** It is a low level bit-bashing state machine. 2980 ** 2981 ** Data from the card is async, so the machine scans at 2982 ** 5 times the data rate looking for a state bit. Once 2983 ** a start bit has been found, it waits for the middle of 2984 ** the bit and starts sampling at the bit rate. 2985 ** 2986 ** Several mid level machines can use this machine, so the value 2987 ** sc->t0ByteParent is used to point to back to the mid level machine 2988 ** 2989 ** 2990 ** FORMAL PARAMETERS: 2991 ** 2992 ** sc - Pointer to the softc structure. 2993 ** cmd - command to this machine 2994 ** 2995 ** IMPLICIT INPUTS: 2996 ** 2997 ** sc->t0RecvByteS state of this machine 2998 ** sc->t0ByteParent mid level machine that started this machine 2999 ** 3000 ** IMPLICIT OUTPUTS: 3001 ** 3002 ** sc->shiftByte byte read from the card 3003 ** sc->status error value if could not read byte 3004 ** 3005 ** FUNCTION VALUE: 3006 ** 3007 ** nill 3008 ** 3009 ** SIDE EFFECTS: 3010 ** 3011 ** nill 3012 **-- 3013 */ 3014 static void t0RecvByteSM(struct scr_softc* sc,int cmd) 3015 { 3016 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 3017 3018 if (cmd == t0rbcAbort) 3019 { 3020 /* kill all the timers */ 3021 scrUntimeout(t0RecvByteSM, sc,t0rbcTFindStartEdge); 3022 scrUntimeout(t0RecvByteSM, sc,t0rbcTFindStartMid); 3023 scrUntimeout(t0RecvByteSM, sc,t0rbcTClockData); 3024 scrUntimeout(t0RecvByteSM, sc,t0rbcTErrorStart); 3025 scrUntimeout(t0RecvByteSM, sc,t0rbcTErrorStop); 3026 3027 scrSetDataHighZ(); 3028 sc->t0RecvByteS = t0rbsIdle; 3029 return; 3030 } 3031 3032 3033 switch (sc->t0RecvByteS) 3034 { 3035 case t0rbsIdle: 3036 switch (cmd) 3037 { 3038 case t0rbcStart: 3039 /* set initial conditions */ 3040 sc->shiftBits = 0; 3041 sc->shiftByte = 0; 3042 sc->shiftParity = 0; 3043 sc->shiftParityCount = 0; 3044 scrClkAdj(sc->clkCountStartRecv); /* recv data clock running at 5 times */ 3045 3046 /* check if start bit is already here */ 3047 //if (scrGetData()) 3048 if (1) 3049 { 3050 /* didn't find it, keep looking */ 3051 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 3052 sc->t0RecvByteS = t0rbsFindStartEdge; 3053 } 3054 else 3055 { 3056 /* found start bit, look for mid bit */ 3057 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartMid,sc->clkCountStartRecv); 3058 sc->t0RecvByteS = t0rbsFindStartMid; 3059 } 3060 break; 3061 3062 3063 3064 default: 3065 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3066 break; 3067 } 3068 break; 3069 3070 3071 case t0rbsFindStartEdge: 3072 switch (cmd) 3073 { 3074 case t0rbcTFindStartEdge: 3075 if (scrGetData()) 3076 { 3077 /* didn't find it, keep looking */ 3078 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 3079 } 3080 else 3081 { 3082 /* found start bit, look for mid bit */ 3083 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartMid,sc->clkCountStartRecv * 2); 3084 sc->t0RecvByteS = t0rbsFindStartMid; 3085 } 3086 break; 3087 3088 3089 default: 3090 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3091 break; 3092 } 3093 break; 3094 3095 case t0rbsFindStartMid: 3096 switch (cmd) 3097 { 3098 case t0rbcTFindStartMid: 3099 if (scrGetData()) 3100 { 3101 /* found glitch, so just go back to hunting */ 3102 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,sc->clkCountStartRecv); 3103 sc->t0RecvByteS = t0rbsFindStartEdge; 3104 } 3105 else 3106 { 3107 /* found start bit, start clocking in data */ 3108 TOGGLE_TEST_PIN(); 3109 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 3110 sc->t0RecvByteS = t0rbsClockData; 3111 } 3112 break; 3113 3114 3115 default: 3116 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3117 break; 3118 } 3119 break; 3120 3121 3122 case t0rbsClockData: 3123 TOGGLE_TEST_PIN(); 3124 switch (cmd) 3125 { 3126 case t0rbcTClockData: 3127 if (sc->shiftBits < 8) 3128 { 3129 if (sc->convention == CONVENTION_INVERSE || 3130 sc->convention == CONVENTION_UNKOWN) 3131 { 3132 /* logic 1 is low, msb is first */ 3133 sc->shiftByte <<= 1; 3134 sc->shiftByte &= 0xfe; 3135 if (!scrGetData()) 3136 { 3137 sc->shiftByte |= 0x01; 3138 sc->shiftParity++; 3139 } 3140 } 3141 else 3142 { 3143 ASSERT(sc->convention == CONVENTION_DIRECT); 3144 /* logic 1 is high, lsb is first */ 3145 sc->shiftByte = sc->shiftByte >> 1; 3146 sc->shiftByte &= 0x7f; 3147 if (scrGetData()) 3148 { 3149 sc->shiftParity++; 3150 sc->shiftByte |= 0x80; 3151 } 3152 } 3153 sc->shiftBits++; 3154 3155 3156 /* in TS byte, check if we have a card that works at 1/2 freq */ 3157 if (sc->convention == CONVENTION_UNKOWN && /* in TS byte */ 3158 sc->shiftBits == 3 && /* test at bit 3 in word */ 3159 sc->shiftByte == 4 && /* check for 1/2 freq pattern */ 3160 sc->cardFreq == CARD_FREQ_DEF) /* only do this if at full freq */ 3161 { 3162 /* adjust counts down to 1/2 freq */ 3163 sc->cardFreq = CARD_FREQ_DEF / 2; 3164 sc->clkCountStartRecv = sc->clkCountStartRecv *2; 3165 sc->clkCountDataRecv = sc->clkCountDataRecv *2; 3166 sc->clkCountDataSend = sc->clkCountDataSend *2; 3167 3168 3169 /* adjust this so that we have clocked in only fist bit of TS */ 3170 sc->shiftParity = 0; 3171 sc->shiftByte = 0; 3172 sc->shiftBits = 1; 3173 3174 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,(sc->clkCountDataRecv * 3) /4); 3175 } 3176 else 3177 { 3178 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 3179 } 3180 } 3181 3182 /* clock in parity bit */ 3183 else if (sc->shiftBits == 8) 3184 { 3185 if (sc->convention == CONVENTION_INVERSE) 3186 { 3187 if (!scrGetData()) 3188 { 3189 sc->shiftParity++; 3190 } 3191 } 3192 else if (sc->convention == CONVENTION_DIRECT) 3193 { 3194 if (scrGetData()) 3195 { 3196 sc->shiftParity++; 3197 } 3198 } 3199 3200 3201 else 3202 { 3203 /* sc->convention not set so sort it out */ 3204 ASSERT(sc->convention == CONVENTION_UNKOWN); 3205 if (sc->shiftByte == CONVENIONT_INVERSE_ID && scrGetData()) 3206 { 3207 sc->convention = CONVENTION_INVERSE; 3208 sc->shiftParity = 0; /* force good parity */ 3209 } 3210 3211 else if (sc->shiftByte == CONVENTION_DIRECT_ID && scrGetData()) 3212 { 3213 sc->shiftByte = CONVENTION_DIRECT_FIX; 3214 sc->convention = CONVENTION_DIRECT; 3215 sc->shiftParity = 0; /* force good parity */ 3216 } 3217 3218 else 3219 { 3220 sc->shiftParity = 1; /* force bad parity */ 3221 } 3222 } 3223 3224 3225 if ((sc->shiftParity & 01) == 0) 3226 { 3227 sc->shiftBits++; 3228 scrTimeout(t0RecvByteSM,sc,t0rbcTClockData,sc->clkCountDataRecv); 3229 } 3230 else 3231 { 3232 /* got parity error */ 3233 if (sc->shiftParityCount < PARITY_ERROR_MAX) 3234 { 3235 sc->shiftParityCount++; 3236 scrTimeout(t0RecvByteSM,sc,t0rbcTErrorStart,sc->clkCountDataRecv); 3237 sc->t0RecvByteS = t0rbsSendError; 3238 } 3239 else 3240 3241 { 3242 /* too many parity errors, just give up on this sc->dataByte */ 3243 sc->status = ERROR_PARITY; 3244 sc->t0RecvByteS = t0rbsIdle; 3245 sc->t0ByteParent(sc,gcT0RecvByteErr); 3246 } 3247 } 3248 } 3249 3250 else 3251 { 3252 sc->dataByte = sc->shiftByte; 3253 sc->t0RecvByteS = t0rbsIdle; 3254 sc->t0ByteParent(sc,gcT0RecvByte); 3255 } 3256 break; 3257 3258 default: 3259 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3260 break; 3261 } 3262 break; 3263 3264 3265 case t0rbsSendError: 3266 TOGGLE_TEST_PIN(); 3267 switch (cmd) 3268 { 3269 case t0rbcTErrorStart: 3270 /* start sending error bit */ 3271 scrSetData(FALSE); 3272 scrTimeout(t0RecvByteSM,sc,t0rbcTErrorStop,sc->clkCountDataRecv * 2); 3273 break; 3274 3275 case t0rbcTErrorStop: 3276 /* stop sending parity error & reset information*/ 3277 scrSetData(TRUE); 3278 sc->shiftBits = 0; 3279 sc->shiftByte = 0; 3280 sc->shiftParity = 0; 3281 3282 /* start looking for start bit */ 3283 scrTimeout(t0RecvByteSM,sc,t0rbcTFindStartEdge,1); 3284 sc->t0RecvByteS = t0rbsFindStartEdge; 3285 break; 3286 3287 default: 3288 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3289 break; 3290 } 3291 break; 3292 3293 3294 default: 3295 INVALID_STATE_CMD(sc, sc->t0RecvByteS,cmd); 3296 break; 3297 } 3298 } 3299 3300 /* 3301 **++ 3302 ** FUNCTIONAL DESCRIPTION: 3303 ** 3304 ** t0SendByteSM 3305 ** 3306 ** This state machine writes 1 byte to a card. 3307 ** It is a low level bit-bashing state machine. 3308 ** 3309 ** 3310 ** Several mid level machines can use this machine, so the value 3311 ** sc->t0ByteParent is used to point to back to the mid level machine 3312 ** 3313 ** FORMAL PARAMETERS: 3314 ** 3315 ** sc - Pointer to the softc structure. 3316 ** cmd - command to this machine 3317 ** 3318 ** IMPLICIT INPUTS: 3319 ** 3320 ** sc->t0SendByteS state of this machine 3321 ** sc->shiftByte byte to write to the card 3322 ** 3323 ** IMPLICIT OUTPUTS: 3324 ** 3325 ** sc->status error value if could not read byte 3326 ** 3327 ** FUNCTION VALUE: 3328 ** 3329 ** nill 3330 ** 3331 ** SIDE EFFECTS: 3332 ** 3333 ** nill 3334 **-- 3335 */ 3336 //int bigTroubleTest = 0; 3337 static void t0SendByteSM (struct scr_softc * sc,int cmd) 3338 { 3339 //if(bigTroubleTest == 2000) 3340 //{ 3341 // INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3342 // bigTroubleTest = 0; 3343 //} 3344 // 3345 //bigTroubleTest++; 3346 3347 if (sc->bigTrouble) return; // david,jim , remove this when dust settles 3348 3349 if (cmd == t0sbcAbort) 3350 { 3351 /* kill all the timers */ 3352 scrUntimeout(t0SendByteSM, sc, t0sbcTGuardTime); 3353 scrUntimeout(t0SendByteSM, sc, t0sbcTClockData); 3354 scrUntimeout(t0SendByteSM, sc, t0sbcTError); 3355 3356 scrSetDataHighZ(); 3357 return; 3358 } 3359 3360 3361 switch (sc->t0SendByteS) 3362 { 3363 case t0sbsIdle: 3364 switch (cmd) 3365 { 3366 case t0sbcStart: 3367 /* set initial conditions */ 3368 sc->shiftBits = 0; 3369 sc->shiftParity = 0; 3370 sc->shiftParityCount = 0; 3371 sc->shiftByte = sc->dataByte; 3372 3373 scrClkAdj(sc->clkCountDataSend); /* send data clock running at 1 ETU */ 3374 3375 /* check if we have to wait for guard time */ 3376 if (0) /* possible optimization here */ 3377 { 3378 /* can send start bit now */ 3379 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3380 scrSetData(FALSE); 3381 sc->t0SendByteS = t0sbsClockData; 3382 } 3383 else 3384 { 3385 /* need to wait for guard time */ 3386 scrTimeout(t0SendByteSM,sc,t0sbcTGuardTime,sc->clkCountDataSend * (12 + sc->N)); 3387 sc->t0SendByteS = t0sbsWaitGuardTime; 3388 3389 } 3390 break; 3391 3392 default: 3393 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3394 break; 3395 } 3396 break; 3397 3398 3399 case t0sbsWaitGuardTime: 3400 switch (cmd) 3401 { 3402 case t0sbcTGuardTime: 3403 TOGGLE_TEST_PIN(); 3404 /* set start bit */ 3405 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3406 scrSetData(FALSE); 3407 sc->t0SendByteS = t0sbsClockData; 3408 break; 3409 3410 default: 3411 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3412 break; 3413 } 3414 break; 3415 3416 3417 case t0sbsClockData: 3418 switch (cmd) 3419 { 3420 case t0sbcTClockData: 3421 TOGGLE_TEST_PIN(); 3422 /* clock out data bit */ 3423 if (sc->shiftBits < 8) 3424 { 3425 if (sc->convention == CONVENTION_INVERSE) 3426 { 3427 if (sc->shiftByte & 0x80) 3428 { 3429 scrSetData(FALSE); 3430 sc->shiftParity++; 3431 } 3432 else 3433 { 3434 scrSetData(TRUE); 3435 } 3436 sc->shiftByte = sc->shiftByte << 1; 3437 } 3438 else 3439 { 3440 ASSERT(sc->convention == CONVENTION_DIRECT); 3441 if (sc->shiftByte & 0x01) 3442 { 3443 scrSetData(TRUE); 3444 sc->shiftParity++; 3445 } 3446 else 3447 { 3448 scrSetData(FALSE); 3449 } 3450 sc->shiftByte = sc->shiftByte >> 1; 3451 } 3452 sc->shiftBits++; 3453 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3454 } 3455 3456 /* clock out parity bit */ 3457 else if (sc->shiftBits == 8) 3458 { 3459 if ( ((sc->shiftParity & 0x01) && (sc->convention == CONVENTION_INVERSE)) || 3460 (!(sc->shiftParity & 0x01) && (sc->convention == CONVENTION_DIRECT)) ) 3461 { 3462 scrSetData(FALSE); 3463 } 3464 else 3465 { 3466 scrSetData(TRUE); 3467 } 3468 sc->shiftBits++; 3469 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3470 } 3471 3472 /* all data shifted out, move onto next state */ 3473 else 3474 { 3475 ASSERT(sc->shiftBits > 8); 3476 scrSetData(TRUE); 3477 scrTimeout(t0SendByteSM,sc,t0sbcTError,sc->clkCountDataSend); 3478 sc->t0SendByteS = t0sbsWaitError; 3479 } 3480 break; 3481 3482 default: 3483 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3484 break; 3485 } 3486 break; 3487 3488 case t0sbsWaitError: 3489 switch (cmd) 3490 { 3491 case t0sbcTError: 3492 /* no error indicated*/ 3493 if (scrGetData()) 3494 { 3495 sc->t0SendByteS = t0sbsIdle; 3496 sc->t0ByteParent(sc,gcT0SendByte); 3497 } 3498 3499 /* got error */ 3500 else 3501 { 3502 /* got parity error */ 3503 if (sc->shiftParityCount < PARITY_ERROR_MAX) 3504 { 3505 sc->shiftParityCount++; 3506 scrTimeout(t0SendByteSM,sc,t0sbcTResend,sc->clkCountDataSend * 2); 3507 sc->t0SendByteS = t0sbsWaitResend; 3508 } 3509 else 3510 { 3511 /* too many parity errors, just give up on this sc->dataByte */ 3512 sc->status = ERROR_PARITY; 3513 sc->t0SendByteS = t0sbsIdle; 3514 sc->t0ByteParent(sc,gcT0SendByteErr); 3515 } 3516 } 3517 break; 3518 3519 default: 3520 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3521 break; 3522 } 3523 break; 3524 3525 case t0sbsWaitResend: 3526 switch (cmd) 3527 { 3528 case t0sbcTResend: 3529 sc->shiftBits = 0; 3530 sc->shiftParity = 0; 3531 sc->shiftByte = sc->dataByte; 3532 /* set start bit */ 3533 3534 scrTimeout(t0SendByteSM,sc,t0sbcTClockData,sc->clkCountDataSend); 3535 scrSetData(FALSE); 3536 sc->t0SendByteS = t0sbsClockData; 3537 break; 3538 3539 default: 3540 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3541 break; 3542 } 3543 break; 3544 3545 3546 default: 3547 INVALID_STATE_CMD(sc, sc->t0SendByteS,cmd); 3548 break; 3549 } 3550 } 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 /* 3563 **++ 3564 ** FUNCTIONAL DESCRIPTION: 3565 ** 3566 ** cardOff 3567 ** 3568 ** Turn all signals to the card off 3569 ** 3570 ** FORMAL PARAMETERS: 3571 ** 3572 ** sc - Pointer to the softc structure. 3573 ** 3574 ** IMPLICIT INPUTS: 3575 ** 3576 ** nill 3577 ** 3578 ** IMPLICIT OUTPUTS: 3579 ** 3580 ** nill 3581 ** 3582 ** FUNCTION VALUE: 3583 ** 3584 ** nill 3585 ** 3586 ** SIDE EFFECTS: 3587 ** 3588 ** nill 3589 **-- 3590 */ 3591 static void cardOff (struct scr_softc * sc) 3592 { 3593 scrSetReset(TRUE); 3594 scrSetDataHighZ(); 3595 scrSetClock(FALSE); 3596 scrSetPower(FALSE); 3597 } 3598 3599 3600 3601 3602 /* 3603 ** 3604 ** 3605 ** **************** timer routines *************** 3606 ** 3607 */ 3608 3609 /* 3610 **++ 3611 ** FUNCTIONAL DESCRIPTION: 3612 ** 3613 ** scrClkInit 3614 ** 3615 ** Init the callout queues. The callout queues are used 3616 ** by the timeout/untimeout queues 3617 ** 3618 ** FORMAL PARAMETERS: 3619 ** 3620 ** nill 3621 ** 3622 ** IMPLICIT INPUTS: 3623 ** 3624 ** nill 3625 ** 3626 ** IMPLICIT OUTPUTS: 3627 ** 3628 ** nill 3629 ** 3630 ** FUNCTION VALUE: 3631 ** 3632 ** nill 3633 ** 3634 ** SIDE EFFECTS: 3635 ** 3636 ** nill 3637 **-- 3638 */ 3639 static void scrClkInit(void) 3640 { 3641 3642 int lc; 3643 Callout *c; 3644 Callout *new; 3645 3646 scrClkCallTodo.c_next = NULL; 3647 scrClkCallFree = &scrClkCalloutArray[0]; 3648 c = scrClkCallFree; 3649 3650 for (lc = 1; lc < SCR_CLK_CALLOUT_COUNT; lc++) 3651 { 3652 new = &scrClkCalloutArray[lc]; 3653 c->c_next = new; 3654 c = new; 3655 } 3656 3657 c->c_next = NULL; 3658 } 3659 3660 3661 /* 3662 **++ 3663 ** FUNCTIONAL DESCRIPTION: 3664 ** 3665 ** scrClkStart 3666 ** 3667 ** This function starts the clock running. The clock is reall the 3668 ** HAT clock (High Available Timer) that is using a FIQ (fast interrupt 3669 ** request). 3670 ** 3671 ** FORMAL PARAMETERS: 3672 ** 3673 ** sc - Pointer to the softc structure. 3674 ** countPerTick - value for T2 timer that drives FIQ 3675 ** 3676 ** IMPLICIT INPUTS: 3677 ** 3678 ** nill 3679 ** 3680 ** IMPLICIT OUTPUTS: 3681 ** 3682 ** nill 3683 ** 3684 ** FUNCTION VALUE: 3685 ** 3686 ** nill 3687 ** 3688 ** SIDE EFFECTS: 3689 ** 3690 ** nill 3691 **-- 3692 */ 3693 static void scrClkStart(struct scr_softc * sc,int countPerTick) 3694 { 3695 u_int savedInts; 3696 3697 savedInts = disable_interrupts(I32_bit | F32_bit); 3698 3699 3700 3701 ASSERT(scrClkCallTodo.c_next == NULL); 3702 ASSERT(!scrClkEnable); 3703 scrClkEnable = 1; 3704 scrClkCount = countPerTick; 3705 3706 hatClkOn(countPerTick, 3707 hatClkIrq, 3708 0xdeadbeef, 3709 hatStack + HATSTACKSIZE - sizeof(unsigned), 3710 myHatWedge); 3711 3712 restore_interrupts(savedInts); 3713 } 3714 3715 /* 3716 **++ 3717 ** FUNCTIONAL DESCRIPTION: 3718 ** 3719 ** scrClkAdj 3720 ** 3721 ** Adjusts the frequence of the clock 3722 ** 3723 ** FORMAL PARAMETERS: 3724 ** 3725 ** count - new value for T2 timer that drives FIQ 3726 ** 3727 ** IMPLICIT INPUTS: 3728 ** 3729 ** nill 3730 ** 3731 ** IMPLICIT OUTPUTS: 3732 ** 3733 ** nill 3734 ** 3735 ** FUNCTION VALUE: 3736 ** 3737 ** nill 3738 ** 3739 ** SIDE EFFECTS: 3740 ** 3741 ** nill 3742 **-- 3743 */ 3744 static void scrClkAdj (int count) 3745 { 3746 u_int savedInts; 3747 3748 if (count != scrClkCount) 3749 { 3750 savedInts = disable_interrupts(I32_bit | F32_bit); 3751 3752 ASSERT(scrClkEnable); 3753 3754 scrClkCount = count; 3755 hatClkAdjust(count); 3756 3757 restore_interrupts(savedInts); 3758 } 3759 } 3760 3761 /* 3762 **++ 3763 ** FUNCTIONAL DESCRIPTION: 3764 ** 3765 ** scrClkStop 3766 ** 3767 ** Stops the clock 3768 ** 3769 ** FORMAL PARAMETERS: 3770 ** 3771 ** nill 3772 ** 3773 ** 3774 ** IMPLICIT INPUTS: 3775 ** 3776 ** nill 3777 ** 3778 ** IMPLICIT OUTPUTS: 3779 ** 3780 ** nill 3781 ** 3782 ** FUNCTION VALUE: 3783 ** 3784 ** nill 3785 ** 3786 ** SIDE EFFECTS: 3787 ** 3788 ** nill 3789 **-- 3790 */ 3791 static void scrClkStop(void) 3792 { 3793 u_int savedInts; 3794 savedInts = disable_interrupts(I32_bit | F32_bit); 3795 3796 ASSERT(scrClkEnable); 3797 scrClkEnable = 0; 3798 ASSERT(scrClkCallTodo.c_next == NULL); 3799 hatClkOff(); 3800 3801 restore_interrupts(savedInts); 3802 } 3803 3804 3805 3806 /* 3807 **++ 3808 ** FUNCTIONAL DESCRIPTION: 3809 ** 3810 ** hatClkIrq 3811 ** 3812 ** This is what the HAT clock calls. This call drives 3813 ** the timeout queues, which in turn drive the state machines 3814 ** 3815 ** Be very carefully when calling a timeout as the function 3816 ** that is called may in turn do timeout/untimeout calls 3817 ** before returning 3818 ** 3819 ** FORMAL PARAMETERS: 3820 ** 3821 ** int x - not used 3822 ** 3823 ** IMPLICIT INPUTS: 3824 ** 3825 ** nill 3826 ** 3827 ** IMPLICIT OUTPUTS: 3828 ** 3829 ** nill 3830 ** 3831 ** FUNCTION VALUE: 3832 ** 3833 ** nill 3834 ** 3835 ** SIDE EFFECTS: 3836 ** 3837 ** a timeout may be called if it is due 3838 **-- 3839 */ 3840 static void hatClkIrq(int x) 3841 { 3842 register Callout *p1; 3843 register int needsoft =0; 3844 register Callout *c; 3845 register int arg; 3846 register void (*func) __P((struct scr_softc*,int)); 3847 struct scr_softc * sc; 3848 3849 ASSERT(scrClkEnable); 3850 for (p1 = scrClkCallTodo.c_next; p1 != NULL; p1 = p1->c_next) 3851 { 3852 p1->c_time -= scrClkCount; 3853 3854 if (p1->c_time > 0) 3855 { 3856 break; 3857 } 3858 needsoft = 1; 3859 if (p1->c_time == 0) 3860 { 3861 break; 3862 } 3863 } 3864 3865 3866 if (needsoft) 3867 { 3868 while ((c = scrClkCallTodo.c_next) != NULL && c->c_time <= 0) 3869 { 3870 func = c->c_func; 3871 sc = c->c_sc; 3872 arg = c->c_arg; 3873 scrClkCallTodo.c_next = c->c_next; 3874 c->c_next = scrClkCallFree; 3875 scrClkCallFree = c; 3876 (*func)(sc,arg); 3877 } 3878 } 3879 } 3880 3881 /* 3882 **++ 3883 ** FUNCTIONAL DESCRIPTION: 3884 ** 3885 ** myHatWedge 3886 ** 3887 ** Called if the HAT timer becomes clogged/wedged. Not 3888 ** used by this driver, we let upper layers recover 3889 ** from this condition 3890 ** 3891 ** FORMAL PARAMETERS: 3892 ** 3893 ** int nFIQs - not used 3894 ** 3895 ** IMPLICIT INPUTS: 3896 ** 3897 ** nill 3898 ** 3899 ** IMPLICIT OUTPUTS: 3900 ** 3901 ** nill 3902 ** 3903 ** FUNCTION VALUE: 3904 ** 3905 ** nill 3906 ** 3907 ** SIDE EFFECTS: 3908 ** 3909 ** nill 3910 **-- 3911 */ 3912 static void myHatWedge(int nFIQs) 3913 { 3914 #ifdef DEBUG 3915 printf("myHatWedge: nFIQ = %d\n",nFIQs); 3916 #endif 3917 } 3918 3919 3920 3921 /* 3922 **++ 3923 ** FUNCTIONAL DESCRIPTION: 3924 ** 3925 ** scrTimeout 3926 ** 3927 ** Execute a function after a specified length of time. 3928 ** 3929 ** 3930 ** FORMAL PARAMETERS: 3931 ** 3932 ** ftn - function to execute 3933 ** sc - pointer to soft c 3934 ** arg - argument passed to function 3935 ** count - number of T2 counts for timeout 3936 ** 3937 ** IMPLICIT INPUTS: 3938 ** 3939 ** nill 3940 ** 3941 ** IMPLICIT OUTPUTS: 3942 ** 3943 ** nill 3944 ** 3945 ** FUNCTION VALUE: 3946 ** 3947 ** nill 3948 ** 3949 ** SIDE EFFECTS: 3950 ** 3951 ** nill 3952 **-- 3953 */ 3954 3955 static void scrTimeout(ftn, sc, arg, count) 3956 void (*ftn) __P((struct scr_softc*,int)); 3957 struct scr_softc* sc; 3958 int arg; 3959 register int count; 3960 { 3961 3962 register Callout *new, *p, *t; 3963 ASSERT(scrClkEnable); 3964 3965 3966 if (count <= 0) 3967 { 3968 count = 1; 3969 } 3970 3971 3972 /* Fill in the next free fcallout structure. */ 3973 if (scrClkCallFree == NULL) 3974 { 3975 panic("timeout table full"); 3976 } 3977 3978 new = scrClkCallFree; 3979 scrClkCallFree = new->c_next; 3980 new->c_sc = sc; 3981 new->c_arg = arg; 3982 new->c_func = ftn; 3983 3984 /* 3985 * The time for each event is stored as a difference from the time 3986 * of the previous event on the queue. Walk the queue, correcting 3987 * the counts argument for queue entries passed. Correct the counts 3988 * value for the queue entry immediately after the insertion point 3989 * as well. Watch out for negative c_time values; these represent 3990 * overdue events. 3991 */ 3992 for (p = &scrClkCallTodo; (t = p->c_next) != NULL && count > t->c_time; p = t) 3993 { 3994 if (t->c_time > 0) 3995 { 3996 count -= t->c_time; 3997 } 3998 } 3999 4000 4001 new->c_time = count; 4002 if (t != NULL) 4003 { 4004 t->c_time -= count; 4005 } 4006 4007 /* Insert the new entry into the queue. */ 4008 p->c_next = new; 4009 new->c_next = t; 4010 } 4011 4012 /* 4013 **++ 4014 ** FUNCTIONAL DESCRIPTION: 4015 ** 4016 ** scrUntimeout 4017 ** 4018 ** Cancel previous timeout function call. 4019 ** 4020 ** FORMAL PARAMETERS: 4021 ** 4022 ** ftn - function of timeout to cancel 4023 ** sc - sc of timeout to cancel 4024 ** arg - arg of timeout to cancel 4025 ** 4026 ** IMPLICIT INPUTS: 4027 ** 4028 ** nill 4029 ** 4030 ** IMPLICIT OUTPUTS: 4031 ** 4032 ** nill 4033 ** 4034 ** FUNCTION VALUE: 4035 ** 4036 ** nill 4037 ** 4038 ** SIDE EFFECTS: 4039 ** 4040 ** nill 4041 **-- 4042 */ 4043 static void scrUntimeout(ftn, sc, arg) 4044 void (*ftn) __P((struct scr_softc*,int)); 4045 struct scr_softc* sc; 4046 int arg; 4047 { 4048 register Callout *p, *t; 4049 ASSERT(scrClkEnable); 4050 4051 for (p = &scrClkCallTodo; (t = p->c_next) != NULL; p = t) 4052 { 4053 if (t->c_func == ftn && t->c_sc == sc && t->c_arg == arg) 4054 { 4055 /* Increment next entry's count. */ 4056 if (t->c_next && t->c_time > 0) 4057 { 4058 t->c_next->c_time += t->c_time; 4059 } 4060 4061 /* Move entry from fcallout queue to scrClkCallFree queue. */ 4062 p->c_next = t->c_next; 4063 t->c_next = scrClkCallFree; 4064 scrClkCallFree = t; 4065 break; 4066 } 4067 } 4068 } 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 /******************* routines used only during debugging */ 4085 #ifdef SCR_DEBUG 4086 4087 /* 4088 **++ 4089 ** FUNCTIONAL DESCRIPTION: 4090 ** 4091 ** invalidStateCmd 4092 ** 4093 ** Debugging function. Printout information about problem 4094 ** and then kick in the debugger or panic 4095 ** 4096 ** FORMAL PARAMETERS: 4097 ** 4098 ** sc - pointer to soft c 4099 ** state - state of machine 4100 ** cmd - command of machine 4101 ** line - line that problem was detected 4102 ** 4103 ** 4104 ** IMPLICIT INPUTS: 4105 ** 4106 ** nill 4107 ** 4108 ** IMPLICIT OUTPUTS: 4109 ** 4110 ** nill 4111 ** 4112 ** FUNCTION VALUE: 4113 ** 4114 ** nill 4115 ** 4116 ** SIDE EFFECTS: 4117 ** 4118 ** nill 4119 **-- 4120 */ 4121 void invalidStateCmd (struct scr_softc* sc,int state,int cmd,int line) 4122 { 4123 printf("INVALID_STATE_CMD: sc = %X, state = %X, cmd = %X, line = %d\n",sc,state,cmd,line); 4124 DEBUGGER; 4125 } 4126 4127 /* 4128 **++ 4129 ** FUNCTIONAL DESCRIPTION: 4130 ** 4131 ** getText 4132 ** 4133 ** Get text representation of state or command 4134 ** 4135 ** FORMAL PARAMETERS: 4136 ** 4137 ** x - state or command 4138 ** 4139 ** IMPLICIT INPUTS: 4140 ** 4141 ** nill 4142 ** 4143 ** IMPLICIT OUTPUTS: 4144 ** 4145 ** nill 4146 ** 4147 ** FUNCTION VALUE: 4148 ** 4149 ** nill 4150 ** 4151 ** SIDE EFFECTS: 4152 ** 4153 ** nill 4154 **-- 4155 */ 4156 char * getText(int x) 4157 { 4158 switch (x) 4159 { 4160 /* commands to Master State Machine (mc = Master Command )*/ 4161 case mcOn: return "mcOn"; 4162 case mcT0DataSend: return "mcT0DataSend"; 4163 case mcT0DataRecv: return "mcT0DataRecv"; 4164 case mcColdReset: return "mcColdReset"; 4165 case mcATR: return "mcATR"; 4166 case mcT0Send: return "mcT0Send"; 4167 case mcT0Recv: return "mcT0Recv"; 4168 4169 /* states in Master state machine (ms = Master State) */ 4170 case msIdleOff: return "msIdleOff"; 4171 case msColdReset: return "msColdReset"; 4172 case msATR: return "msATR"; 4173 case msIdleOn: return "msIdleOn"; 4174 case msT0Send: return "msT0Send"; 4175 case msT0Recv: return "msT0Recv"; 4176 4177 4178 4179 /* commands to T0 send state machine */ 4180 case t0scStart: return "t0scStart"; 4181 case t0scTWorkWaiting: return "t0scTWorkWaiting"; 4182 4183 4184 /* states in T0 send state machine */ 4185 case t0ssIdle: return "t0ssIdle"; 4186 case t0ssSendHeader: return "t0ssSendHeader"; 4187 case t0ssRecvProcedure: return "t0ssRecvProcedu"; 4188 case t0ssSendByte: return "t0ssSendByte"; 4189 case t0ssSendData: return "t0ssSendData"; 4190 case t0ssRecvSW1: return "t0ssRecvSW1"; 4191 case t0ssRecvSW2: return "t0ssRecvSW2"; 4192 4193 4194 /* commands to T0 recv state machine */ 4195 case t0rcStart: return "t0rcStart"; 4196 case t0rcTWorkWaiting: return "t0rcTWorkWaiting"; 4197 4198 /* states in T0 recv state machine */ 4199 case t0rsIdle: return "t0rsIdle"; 4200 case t0rsSendHeader: return "t0rsSendHeader"; 4201 case t0rsRecvProcedure: return "t0rsRecvProcedure"; 4202 case t0rsRecvByte: return "t0rsRecvByte"; 4203 case t0rsRecvData: return "t0rsRecvData"; 4204 case t0rsRecvSW1: return "t0rsRecvSW1"; 4205 case t0rsRecvSW2: return "t0rsRecvSW2"; 4206 4207 4208 4209 4210 4211 /* commands to Answer To Reset (ATR) state machine */ 4212 case atrcStart: return "atrcStart"; 4213 case atrcT3: return "0x0b04"; 4214 case atrcTWorkWaiting: return "atrcTWorkWaiting"; 4215 4216 4217 /* states in in Anser To Reset (ATR) state machine */ 4218 case atrsIdle: return "atrsIdle"; 4219 case atrsTS: return "atrsTS"; 4220 case atrsT0: return "atrsT0"; 4221 case atrsTABCD: return "atrsTABCD"; 4222 case atrsTK: return "atrsTK"; 4223 case atrsTCK: return "atrsTCK"; 4224 4225 4226 4227 /* commands to T0 Recv Byte state machine */ 4228 case t0rbcStart: return "t0rbcStart"; 4229 case t0rbcAbort: return "t0rbcAbort"; 4230 4231 case t0rbcTFindStartEdge:return "t0rbcTFindStartEdge"; 4232 case t0rbcTFindStartMid: return "t0rbcTFindStartMid"; 4233 case t0rbcTClockData: return "t0rbcTClockData"; 4234 case t0rbcTErrorStart: return "t0rbcTErrorStart"; 4235 case t0rbcTErrorStop: return "t0rbcTErrorStop"; 4236 4237 /* states in in TO Recv Byte state machine */ 4238 case t0rbsIdle: return "t0rbsIdle"; 4239 case t0rbsFindStartEdge: return "t0rbcFindStartEdge"; 4240 case t0rbsFindStartMid: return "t0rbcFindStartMid"; 4241 case t0rbsClockData: return "t0rbcClockData"; 4242 case t0rbsSendError: return "t0rbcSendError"; 4243 4244 4245 /* commands to T0 Send Byte state machine */ 4246 case t0sbcStart: return "t0sbcStart"; 4247 case t0sbcAbort: return "t0sbcAbort"; 4248 case t0sbcTGuardTime: return "t0sbcTGuardTime"; 4249 case t0sbcTClockData: return "t0sbcTClockData"; 4250 case t0sbcTError: return "t0sbcTError"; 4251 case t0sbcTResend: return "t0sbcTResend"; 4252 4253 /* states in in T0 Send Byte state machine */ 4254 case t0sbsIdle: return "t0sbsIdle"; 4255 case t0sbsClockData: return "t0sbsClockData"; 4256 case t0sbsWaitError: return "t0sbsWaitError"; 4257 case t0sbsWaitResend: return "t0sbsWaitResend"; 4258 case t0sbsWaitGuardTime: return "t0sbsWaitGuardTime"; 4259 4260 4261 case gcT0RecvByte: return "gcT0RecvByte"; 4262 case gcT0RecvByteErr: return "gcT0RecvByteErr"; 4263 case gcT0SendByte: return "gcT0SendByte"; 4264 case gcT0SendByteErr: return "gcT0SendByteErr"; 4265 4266 4267 case crcStart: return "crcStart"; 4268 case crcT2: return "crcT2"; 4269 4270 4271 default: 4272 printf("unkown case, %x\n",x); 4273 break; 4274 } 4275 return "???"; 4276 } 4277 4278 #endif /* SCR_DEBUG */ 4279 4280 4281 4282