1 /* $NetBSD: sbus.c,v 1.45 2002/03/11 16:27:02 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This software was developed by the Computer Systems Engineering group 44 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 45 * contributed to Berkeley. 46 * 47 * All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the University of 50 * California, Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by the University of 63 * California, Berkeley and its contributors. 64 * 4. Neither the name of the University nor the names of its contributors 65 * may be used to endorse or promote products derived from this software 66 * without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 69 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 71 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 74 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 75 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 76 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 77 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 * SUCH DAMAGE. 79 * 80 * @(#)sbus.c 8.1 (Berkeley) 6/11/93 81 */ 82 83 /* 84 * Sbus stuff. 85 */ 86 87 #include <sys/param.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/systm.h> 91 #include <sys/device.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #include <machine/bus.h> 96 #include <sparc/dev/sbusreg.h> 97 #include <dev/sbus/sbusvar.h> 98 #include <dev/sbus/xboxvar.h> 99 100 #include <sparc/sparc/iommuvar.h> 101 #include <machine/autoconf.h> 102 103 104 void sbusreset __P((int)); 105 106 static bus_space_tag_t sbus_alloc_bustag __P((struct sbus_softc *)); 107 static int sbus_get_intr __P((struct sbus_softc *, int, 108 struct sbus_intr **, int *)); 109 static paddr_t sbus_bus_mmap __P((bus_space_tag_t, bus_addr_t, off_t, 110 int, int)); 111 static int _sbus_bus_map __P(( 112 bus_space_tag_t, 113 bus_addr_t, /*coded slot+offset*/ 114 bus_size_t, /*size*/ 115 int, /*flags*/ 116 vaddr_t, /*preferred virtual address */ 117 bus_space_handle_t *)); 118 static void *sbus_intr_establish __P(( 119 bus_space_tag_t, 120 int, /*Sbus interrupt level*/ 121 int, /*`device class' priority*/ 122 int, /*flags*/ 123 int (*) __P((void *)), /*handler*/ 124 void *)); /*handler arg*/ 125 126 127 /* autoconfiguration driver */ 128 int sbus_match_mainbus __P((struct device *, struct cfdata *, void *)); 129 int sbus_match_iommu __P((struct device *, struct cfdata *, void *)); 130 int sbus_match_xbox __P((struct device *, struct cfdata *, void *)); 131 void sbus_attach_mainbus __P((struct device *, struct device *, void *)); 132 void sbus_attach_iommu __P((struct device *, struct device *, void *)); 133 void sbus_attach_xbox __P((struct device *, struct device *, void *)); 134 135 static int sbus_error __P((void)); 136 int (*sbuserr_handler) __P((void)); 137 138 struct cfattach sbus_mainbus_ca = { 139 sizeof(struct sbus_softc), sbus_match_mainbus, sbus_attach_mainbus 140 }; 141 struct cfattach sbus_iommu_ca = { 142 sizeof(struct sbus_softc), sbus_match_iommu, sbus_attach_iommu 143 }; 144 struct cfattach sbus_xbox_ca = { 145 sizeof(struct sbus_softc), sbus_match_xbox, sbus_attach_xbox 146 }; 147 148 extern struct cfdriver sbus_cd; 149 150 /* The "primary" Sbus */ 151 struct sbus_softc *sbus_sc; 152 153 /* If the PROM does not provide the `ranges' property, we make up our own */ 154 struct sbus_range sbus_translations[] = { 155 /* Assume a maximum of 4 Sbus slots, all mapped to on-board io space */ 156 { 0, 0, PMAP_OBIO, SBUS_ADDR(0,0), 1 << 25 }, 157 { 1, 0, PMAP_OBIO, SBUS_ADDR(1,0), 1 << 25 }, 158 { 2, 0, PMAP_OBIO, SBUS_ADDR(2,0), 1 << 25 }, 159 { 3, 0, PMAP_OBIO, SBUS_ADDR(3,0), 1 << 25 } 160 }; 161 162 /* 163 * Child devices receive the Sbus interrupt level in their attach 164 * arguments. We translate these to CPU IPLs using the following 165 * tables. Note: obio bus interrupt levels are identical to the 166 * processor IPL. 167 * 168 * The second set of tables is used when the Sbus interrupt level 169 * cannot be had from the PROM as an `interrupt' property. We then 170 * fall back on the `intr' property which contains the CPU IPL. 171 */ 172 173 /* Translate Sbus interrupt level to processor IPL */ 174 static int intr_sbus2ipl_4c[] = { 175 0, 1, 2, 3, 5, 7, 8, 9 176 }; 177 static int intr_sbus2ipl_4m[] = { 178 0, 2, 3, 5, 7, 9, 11, 13 179 }; 180 181 /* 182 * This value is or'ed into the attach args' interrupt level cookie 183 * if the interrupt level comes from an `intr' property, i.e. it is 184 * not an Sbus interrupt level. 185 */ 186 #define SBUS_INTR_COMPAT 0x80000000 187 188 189 /* 190 * Print the location of some sbus-attached device (called just 191 * before attaching that device). If `sbus' is not NULL, the 192 * device was found but not configured; print the sbus as well. 193 * Return UNCONF (config_find ignores this if the device was configured). 194 */ 195 int 196 sbus_print(args, busname) 197 void *args; 198 const char *busname; 199 { 200 struct sbus_attach_args *sa = args; 201 int i; 202 203 if (busname) 204 printf("%s at %s", sa->sa_name, busname); 205 printf(" slot %d offset 0x%x", sa->sa_slot, sa->sa_offset); 206 for (i = 0; i < sa->sa_nintr; i++) { 207 u_int32_t level = sa->sa_intr[i].sbi_pri; 208 struct sbus_softc *sc = 209 (struct sbus_softc *) sa->sa_bustag->cookie; 210 211 printf(" level %d", level & ~SBUS_INTR_COMPAT); 212 if ((level & SBUS_INTR_COMPAT) == 0) { 213 int ipl = sc->sc_intr2ipl[level]; 214 if (ipl != level) 215 printf(" (ipl %d)", ipl); 216 } 217 } 218 return (UNCONF); 219 } 220 221 int 222 sbus_match_mainbus(parent, cf, aux) 223 struct device *parent; 224 struct cfdata *cf; 225 void *aux; 226 { 227 struct mainbus_attach_args *ma = aux; 228 229 if (CPU_ISSUN4) 230 return (0); 231 232 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 233 } 234 235 int 236 sbus_match_iommu(parent, cf, aux) 237 struct device *parent; 238 struct cfdata *cf; 239 void *aux; 240 { 241 struct iommu_attach_args *ia = aux; 242 243 if (CPU_ISSUN4) 244 return (0); 245 246 return (strcmp(cf->cf_driver->cd_name, ia->iom_name) == 0); 247 } 248 249 int 250 sbus_match_xbox(parent, cf, aux) 251 struct device *parent; 252 struct cfdata *cf; 253 void *aux; 254 { 255 struct xbox_attach_args *xa = aux; 256 257 if (CPU_ISSUN4) 258 return (0); 259 260 return (strcmp(cf->cf_driver->cd_name, xa->xa_name) == 0); 261 } 262 263 /* 264 * Attach an Sbus. 265 */ 266 void 267 sbus_attach_mainbus(parent, self, aux) 268 struct device *parent; 269 struct device *self; 270 void *aux; 271 { 272 struct sbus_softc *sc = (struct sbus_softc *)self; 273 struct mainbus_attach_args *ma = aux; 274 int node = ma->ma_node; 275 276 /* 277 * XXX there is only one Sbus, for now -- do not know how to 278 * address children on others 279 */ 280 if (sc->sc_dev.dv_unit > 0) { 281 printf(" unsupported\n"); 282 return; 283 } 284 285 sc->sc_bustag = ma->ma_bustag; 286 sc->sc_dmatag = ma->ma_dmatag; 287 288 #if 0 /* sbus at mainbus (sun4c): `reg' prop is not control space */ 289 if (ma->ma_size == 0) 290 printf("%s: no Sbus registers", self->dv_xname); 291 292 if (bus_space_map(ma->ma_bustag, 293 ma->ma_paddr, 294 ma->ma_size, 295 BUS_SPACE_MAP_LINEAR, 296 &sc->sc_bh) != 0) { 297 panic("%s: can't map sbusbusreg", self->dv_xname); 298 } 299 #endif 300 301 /* Setup interrupt translation tables */ 302 sc->sc_intr2ipl = CPU_ISSUN4C 303 ? intr_sbus2ipl_4c 304 : intr_sbus2ipl_4m; 305 306 /* 307 * Record clock frequency for synchronous SCSI. 308 * IS THIS THE CORRECT DEFAULT?? 309 */ 310 sc->sc_clockfreq = PROM_getpropint(node, "clock-frequency", 25*1000*1000); 311 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 312 313 sbus_sc = sc; 314 sbus_attach_common(sc, "sbus", node, NULL); 315 } 316 317 318 void 319 sbus_attach_iommu(parent, self, aux) 320 struct device *parent; 321 struct device *self; 322 void *aux; 323 { 324 struct sbus_softc *sc = (struct sbus_softc *)self; 325 struct iommu_attach_args *ia = aux; 326 int node = ia->iom_node; 327 328 sc->sc_bustag = ia->iom_bustag; 329 sc->sc_dmatag = ia->iom_dmatag; 330 331 if (ia->iom_nreg == 0) 332 panic("%s: no Sbus registers", self->dv_xname); 333 334 if (bus_space_map(ia->iom_bustag, 335 BUS_ADDR(ia->iom_reg[0].ior_iospace, 336 ia->iom_reg[0].ior_pa), 337 (bus_size_t)ia->iom_reg[0].ior_size, 338 BUS_SPACE_MAP_LINEAR, 339 &sc->sc_bh) != 0) { 340 panic("%s: can't map sbusbusreg", self->dv_xname); 341 } 342 343 /* Setup interrupt translation tables */ 344 sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m; 345 346 /* 347 * Record clock frequency for synchronous SCSI. 348 * IS THIS THE CORRECT DEFAULT?? 349 */ 350 sc->sc_clockfreq = PROM_getpropint(node, "clock-frequency", 25*1000*1000); 351 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 352 353 sbus_sc = sc; 354 sbuserr_handler = sbus_error; 355 sbus_attach_common(sc, "sbus", node, NULL); 356 } 357 358 void 359 sbus_attach_xbox(parent, self, aux) 360 struct device *parent; 361 struct device *self; 362 void *aux; 363 { 364 struct sbus_softc *sc = (struct sbus_softc *)self; 365 struct xbox_attach_args *xa = aux; 366 int node = xa->xa_node; 367 368 sc->sc_bustag = xa->xa_bustag; 369 sc->sc_dmatag = xa->xa_dmatag; 370 371 /* Setup interrupt translation tables */ 372 sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m; 373 374 /* 375 * Record clock frequency for synchronous SCSI. 376 * IS THIS THE CORRECT DEFAULT?? 377 */ 378 sc->sc_clockfreq = PROM_getpropint(node, "clock-frequency", 25*1000*1000); 379 printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq)); 380 381 sbus_attach_common(sc, "sbus", node, NULL); 382 } 383 384 void 385 sbus_attach_common(sc, busname, busnode, specials) 386 struct sbus_softc *sc; 387 char *busname; 388 int busnode; 389 const char * const *specials; 390 { 391 int node0, node, error; 392 const char *sp; 393 const char *const *ssp; 394 bus_space_tag_t sbt; 395 struct sbus_attach_args sa; 396 397 sbt = sbus_alloc_bustag(sc); 398 399 /* 400 * Get the SBus burst transfer size if burst transfers are supported 401 */ 402 sc->sc_burst = PROM_getpropint(busnode, "burst-sizes", 0); 403 404 405 if (CPU_ISSUN4M) { 406 /* 407 * Some models (e.g. SS20) erroneously report 64-bit 408 * burst capability. We mask it out here for all SUN4Ms, 409 * since probably no member of that class supports 410 * 64-bit Sbus bursts. 411 */ 412 sc->sc_burst &= ~SBUS_BURST_64; 413 } 414 415 /* 416 * Collect address translations from the OBP. 417 */ 418 error = PROM_getprop(busnode, "ranges", sizeof(struct rom_range), 419 &sc->sc_nrange, (void **)&sc->sc_range); 420 switch (error) { 421 case 0: 422 break; 423 case ENOENT: 424 /* Fall back to our own `range' construction */ 425 sc->sc_range = sbus_translations; 426 sc->sc_nrange = 427 sizeof(sbus_translations)/sizeof(sbus_translations[0]); 428 break; 429 default: 430 panic("%s: error getting ranges property", sc->sc_dev.dv_xname); 431 } 432 433 /* 434 * Loop through ROM children, fixing any relative addresses 435 * and then configuring each device. 436 * `specials' is an array of device names that are treated 437 * specially: 438 */ 439 node0 = firstchild(busnode); 440 for (ssp = specials ; ssp != NULL && *(sp = *ssp) != 0; ssp++) { 441 if ((node = findnode(node0, sp)) == 0) { 442 panic("could not find %s amongst %s devices", 443 sp, busname); 444 } 445 446 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 447 node, &sa) != 0) { 448 panic("sbus_attach: %s: incomplete", sp); 449 } 450 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 451 sbus_destroy_attach_args(&sa); 452 } 453 454 for (node = node0; node; node = nextsibling(node)) { 455 char *name = PROM_getpropstring(node, "name"); 456 for (ssp = specials, sp = NULL; 457 ssp != NULL && (sp = *ssp) != NULL; 458 ssp++) 459 if (strcmp(name, sp) == 0) 460 break; 461 462 if (sp != NULL) 463 /* Already configured as an "early" device */ 464 continue; 465 466 if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag, 467 node, &sa) != 0) { 468 printf("sbus_attach: %s: incomplete\n", name); 469 continue; 470 } 471 (void) config_found(&sc->sc_dev, (void *)&sa, sbus_print); 472 sbus_destroy_attach_args(&sa); 473 } 474 } 475 476 int 477 sbus_setup_attach_args(sc, bustag, dmatag, node, sa) 478 struct sbus_softc *sc; 479 bus_space_tag_t bustag; 480 bus_dma_tag_t dmatag; 481 int node; 482 struct sbus_attach_args *sa; 483 { 484 int n, error; 485 486 bzero(sa, sizeof(struct sbus_attach_args)); 487 error = PROM_getprop(node, "name", 1, &n, (void **)&sa->sa_name); 488 if (error != 0) 489 return (error); 490 sa->sa_name[n] = '\0'; 491 492 sa->sa_bustag = bustag; 493 sa->sa_dmatag = dmatag; 494 sa->sa_node = node; 495 sa->sa_frequency = sc->sc_clockfreq; 496 497 error = PROM_getprop(node, "reg", sizeof(struct sbus_reg), 498 &sa->sa_nreg, (void **)&sa->sa_reg); 499 if (error != 0) { 500 char buf[32]; 501 if (error != ENOENT || 502 !node_has_property(node, "device_type") || 503 strcmp(PROM_getpropstringA(node, "device_type", buf, sizeof buf), 504 "hierarchical") != 0) 505 return (error); 506 } 507 for (n = 0; n < sa->sa_nreg; n++) { 508 /* Convert to relative addressing, if necessary */ 509 u_int32_t base = sa->sa_reg[n].sbr_offset; 510 if (SBUS_ABS(base)) { 511 sa->sa_reg[n].sbr_slot = SBUS_ABS_TO_SLOT(base); 512 sa->sa_reg[n].sbr_offset = SBUS_ABS_TO_OFFSET(base); 513 } 514 } 515 516 if ((error = sbus_get_intr(sc, node, &sa->sa_intr, &sa->sa_nintr)) != 0) 517 return (error); 518 519 error = PROM_getprop(node, "address", sizeof(u_int32_t), 520 &sa->sa_npromvaddrs, (void **)&sa->sa_promvaddrs); 521 if (error != 0 && error != ENOENT) 522 return (error); 523 524 return (0); 525 } 526 527 void 528 sbus_destroy_attach_args(sa) 529 struct sbus_attach_args *sa; 530 { 531 if (sa->sa_name != NULL) 532 free(sa->sa_name, M_DEVBUF); 533 534 if (sa->sa_nreg != 0) 535 free(sa->sa_reg, M_DEVBUF); 536 537 if (sa->sa_intr) 538 free(sa->sa_intr, M_DEVBUF); 539 540 if (sa->sa_promvaddrs) 541 free(sa->sa_promvaddrs, M_DEVBUF); 542 543 bzero(sa, sizeof(struct sbus_attach_args));/*DEBUG*/ 544 } 545 546 547 int 548 _sbus_bus_map(t, ba, size, flags, va, hp) 549 bus_space_tag_t t; 550 bus_addr_t ba; 551 bus_size_t size; 552 int flags; 553 vaddr_t va; 554 bus_space_handle_t *hp; 555 { 556 struct sbus_softc *sc = t->cookie; 557 int slot = BUS_ADDR_IOSPACE(ba); 558 int i; 559 560 for (i = 0; i < sc->sc_nrange; i++) { 561 struct sbus_range *rp = &sc->sc_range[i]; 562 563 if (rp->cspace != slot) 564 continue; 565 566 /* We've found the connection to the parent bus */ 567 return (bus_space_map2(sc->sc_bustag, 568 BUS_ADDR(rp->pspace, 569 rp->poffset + BUS_ADDR_PADDR(ba)), 570 size, flags, va, hp)); 571 } 572 573 return (EINVAL); 574 } 575 576 static paddr_t 577 sbus_bus_mmap(t, ba, off, prot, flags) 578 bus_space_tag_t t; 579 bus_addr_t ba; 580 off_t off; 581 int prot; 582 int flags; 583 { 584 struct sbus_softc *sc = t->cookie; 585 int slot = BUS_ADDR_IOSPACE(ba); 586 int i; 587 588 for (i = 0; i < sc->sc_nrange; i++) { 589 struct sbus_range *rp = &sc->sc_range[i]; 590 591 if (rp->cspace != slot) 592 continue; 593 594 return (bus_space_mmap(sc->sc_bustag, 595 BUS_ADDR(rp->pspace, 596 rp->poffset + BUS_ADDR_PADDR(ba)), 597 off, prot, flags)); 598 } 599 600 return (-1); 601 } 602 603 bus_addr_t 604 sbus_bus_addr(t, btype, offset) 605 bus_space_tag_t t; 606 u_int btype; 607 u_int offset; 608 { 609 610 /* XXX: sbus_bus_addr should be g/c'ed */ 611 return (BUS_ADDR(btype, offset)); 612 } 613 614 615 /* 616 * Each attached device calls sbus_establish after it initializes 617 * its sbusdev portion. 618 */ 619 void 620 sbus_establish(sd, dev) 621 register struct sbusdev *sd; 622 register struct device *dev; 623 { 624 register struct sbus_softc *sc; 625 register struct device *curdev; 626 627 /* 628 * We have to look for the sbus by name, since it is not necessarily 629 * our immediate parent (i.e. sun4m /iommu/sbus/espdma/esp) 630 * We don't just use the device structure of the above-attached 631 * sbus, since we might (in the future) support multiple sbus's. 632 */ 633 for (curdev = dev->dv_parent; ; curdev = curdev->dv_parent) { 634 if (!curdev || !curdev->dv_xname) 635 panic("sbus_establish: can't find sbus parent for %s", 636 sd->sd_dev->dv_xname 637 ? sd->sd_dev->dv_xname 638 : "<unknown>" ); 639 640 if (strncmp(curdev->dv_xname, "sbus", 4) == 0) 641 break; 642 } 643 sc = (struct sbus_softc *) curdev; 644 645 sd->sd_dev = dev; 646 sd->sd_bchain = sc->sc_sbdev; 647 sc->sc_sbdev = sd; 648 } 649 650 /* 651 * Reset the given sbus. (???) 652 */ 653 void 654 sbusreset(sbus) 655 int sbus; 656 { 657 register struct sbusdev *sd; 658 struct sbus_softc *sc = sbus_cd.cd_devs[sbus]; 659 struct device *dev; 660 661 printf("reset %s:", sc->sc_dev.dv_xname); 662 for (sd = sc->sc_sbdev; sd != NULL; sd = sd->sd_bchain) { 663 if (sd->sd_reset) { 664 dev = sd->sd_dev; 665 (*sd->sd_reset)(dev); 666 printf(" %s", dev->dv_xname); 667 } 668 } 669 } 670 671 672 /* 673 * Get interrupt attributes for an Sbus device. 674 */ 675 int 676 sbus_get_intr(sc, node, ipp, np) 677 struct sbus_softc *sc; 678 int node; 679 struct sbus_intr **ipp; 680 int *np; 681 { 682 int error, n; 683 u_int32_t *ipl = NULL; 684 685 /* 686 * The `interrupts' property contains the Sbus interrupt level. 687 */ 688 if (PROM_getprop(node, "interrupts", sizeof(int), np, (void **)&ipl) == 0) { 689 /* Change format to an `struct sbus_intr' array */ 690 struct sbus_intr *ip; 691 ip = malloc(*np * sizeof(struct sbus_intr), M_DEVBUF, M_NOWAIT); 692 if (ip == NULL) { 693 free(ipl, M_DEVBUF); 694 return (ENOMEM); 695 } 696 for (n = 0; n < *np; n++) { 697 ip[n].sbi_pri = ipl[n]; 698 ip[n].sbi_vec = 0; 699 } 700 free(ipl, M_DEVBUF); 701 *ipp = ip; 702 return (0); 703 } 704 705 /* 706 * Fall back on `intr' property. 707 */ 708 *ipp = NULL; 709 error = PROM_getprop(node, "intr", sizeof(struct sbus_intr), 710 np, (void **)ipp); 711 switch (error) { 712 case 0: 713 for (n = *np; n-- > 0;) { 714 (*ipp)[n].sbi_pri &= 0xf; 715 (*ipp)[n].sbi_pri |= SBUS_INTR_COMPAT; 716 } 717 break; 718 case ENOENT: 719 error = 0; 720 break; 721 } 722 723 return (error); 724 } 725 726 727 /* 728 * Install an interrupt handler for an Sbus device. 729 */ 730 void * 731 sbus_intr_establish(t, pri, level, flags, handler, arg) 732 bus_space_tag_t t; 733 int pri; 734 int level; 735 int flags; 736 int (*handler) __P((void *)); 737 void *arg; 738 { 739 struct sbus_softc *sc = t->cookie; 740 struct intrhand *ih; 741 int pil; 742 743 ih = (struct intrhand *) 744 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 745 if (ih == NULL) 746 return (NULL); 747 748 /* 749 * Translate Sbus interrupt priority to CPU interrupt level 750 */ 751 if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) != 0) 752 pil = pri; 753 else if ((pri & SBUS_INTR_COMPAT) != 0) 754 pil = pri & ~SBUS_INTR_COMPAT; 755 else 756 pil = sc->sc_intr2ipl[pri]; 757 758 ih->ih_fun = handler; 759 ih->ih_arg = arg; 760 if ((flags & BUS_INTR_ESTABLISH_FASTTRAP) != 0) 761 intr_fasttrap(pil, (void (*)__P((void)))handler); 762 else 763 intr_establish(pil, ih); 764 return (ih); 765 } 766 767 static bus_space_tag_t 768 sbus_alloc_bustag(sc) 769 struct sbus_softc *sc; 770 { 771 bus_space_tag_t sbt; 772 773 sbt = (bus_space_tag_t) 774 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 775 if (sbt == NULL) 776 return (NULL); 777 778 bzero(sbt, sizeof *sbt); 779 sbt->cookie = sc; 780 sbt->parent = sc->sc_bustag; 781 sbt->sparc_bus_map = _sbus_bus_map; 782 sbt->sparc_bus_mmap = sbus_bus_mmap; 783 sbt->sparc_intr_establish = sbus_intr_establish; 784 return (sbt); 785 } 786 787 int 788 sbus_error() 789 { 790 struct sbus_softc *sc = sbus_sc; 791 bus_space_handle_t bh = sc->sc_bh; 792 u_int32_t afsr, afva; 793 char bits[64]; 794 static int straytime, nstray; 795 int timesince; 796 797 afsr = bus_space_read_4(sc->sc_bustag, bh, SBUS_AFSR_REG); 798 afva = bus_space_read_4(sc->sc_bustag, bh, SBUS_AFAR_REG); 799 printf("sbus error:\n\tAFSR %s\n", 800 bitmask_snprintf(afsr, SBUS_AFSR_BITS, bits, sizeof(bits))); 801 printf("\taddress: 0x%x%x\n", afsr & SBUS_AFSR_PAH, afva); 802 803 /* For now, do the same dance as on stray interrupts */ 804 timesince = time.tv_sec - straytime; 805 if (timesince <= 10) { 806 if (++nstray > 9) 807 panic("too many SBus errors"); 808 } else { 809 straytime = time.tv_sec; 810 nstray = 1; 811 } 812 813 /* Unlock registers and clear interrupt */ 814 bus_space_write_4(sc->sc_bustag, bh, SBUS_AFSR_REG, afsr); 815 816 return (0); 817 } 818