1 /* $NetBSD: swreg.h,v 1.5 2008/04/28 20:23:35 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Register map for the Sun3 SCSI Interface (si) 34 * The first part of this register map is an NCR5380 35 * SCSI Bus Interface Controller (SBIC). The rest is a 36 * DMA controller and custom logic for the OBIO interface (3/50,3/60,4/110) 37 * 38 * Modified for Sun 4 systems by Jason R. Thorpe <thorpej@NetBSD.org>. 39 */ 40 41 /* 42 * Note that the obio version on the 4/1xx (the so-called "SCSI Weird", or 43 * "sw" controller) is laid out a bit differently, and hence the evilness 44 * with unions. Also, the "sw" doesn't appear to have a FIFO. 45 */ 46 47 #if __for_reference_only__ 48 struct sw_regs { 49 /* 50 * Am5380 Register map (no padding). See dev/ic/ncr5380reg.h 51 */ 52 struct ncr5380regs { 53 u_char r[8]; 54 } sci; 55 56 /* DMA controller registers on OBIO */ 57 u_int dma_addr; /* DMA address */ 58 u_int dma_count; /* DMA count */ 59 u_int pad0; /* no-existent register */ 60 u_int sw_csr; /* sw control/status */ 61 u_int bpr; /* sw byte pack */ 62 }; 63 #endif 64 65 /* 66 * Size of NCR5380 registers located at the bottom of the register bank. 67 */ 68 #define NCR5380REGS_SZ 8 69 70 /* 71 * Register definition for the `sw' OBIO controller 72 */ 73 #define SWREG_DMA_ADDR (NCR5380REGS_SZ + 0) 74 #define SWREG_DMA_CNT (NCR5380REGS_SZ + 4) 75 #define SWREG_CSR (NCR5380REGS_SZ + 12) 76 #define SWREG_BPR (NCR5380REGS_SZ + 16) 77 #define SWREG_BANK_SZ (NCR5380REGS_SZ + 20) 78 79 /* 80 * Status Register. 81 * Note: 82 * (r) indicates bit is read only. 83 * (rw) indicates bit is read or write. 84 * (v) vme host adaptor interface only. 85 * (o) sun3/50 onboard host adaptor interface only. 86 * (b) both vme and sun3/50 host adaptor interfaces. 87 */ 88 #define SW_CSR_DMA_ACTIVE 0x8000 /* (r,o) DMA transfer active */ 89 #define SW_CSR_DMA_CONFLICT 0x4000 /* (r,b) reg accessed while DMA'ing */ 90 #define SW_CSR_DMA_BUS_ERR 0x2000 /* (r,b) bus error during DMA */ 91 #define SW_CSR_ID 0x1000 /* (r,b) 0 for 3/50, 1 for SCSI-3, */ 92 /* 0 if SCSI-3 unmodified */ 93 #define SW_CSR_FIFO_FULL 0x0800 /* (r,b) fifo full */ 94 #define SW_CSR_FIFO_EMPTY 0x0400 /* (r,b) fifo empty */ 95 #define SW_CSR_SBC_IP 0x0200 /* (r,b) sbc interrupt pending */ 96 #define SW_CSR_DMA_IP 0x0100 /* (r,b) DMA interrupt pending */ 97 #define SW_CSR_DMA_EN 0x0010 /* (rw,v) DMA/interrupt enable */ 98 #define SW_CSR_SEND 0x0008 /* (rw,b) DMA dir, 1=to device */ 99 #define SW_CSR_INTR_EN 0x0004 /* (rw,b) interrupts enable */ 100 #define SW_CSR_FIFO_RES 0x0002 /* (rw,b) inits fifo, 0=reset */ 101 #define SW_CSR_SCSI_RES 0x0001 /* (rw,b) reset sbc and udc, 0=reset */ 102