1 /* $NetBSD: zs.c,v 1.92 2002/10/09 08:56:25 jdc Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 #include "opt_ddb.h" 48 #include "opt_kgdb.h" 49 #include "opt_sparc_arch.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/conf.h> 54 #include <sys/device.h> 55 #include <sys/file.h> 56 #include <sys/ioctl.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> 59 #include <sys/tty.h> 60 #include <sys/time.h> 61 #include <sys/syslog.h> 62 63 #include <machine/bsd_openprom.h> 64 #include <machine/autoconf.h> 65 #include <machine/intr.h> 66 #include <machine/eeprom.h> 67 #include <machine/psl.h> 68 #include <machine/z8530var.h> 69 70 #include <dev/cons.h> 71 #include <dev/ic/z8530reg.h> 72 73 #include <sparc/sparc/vaddrs.h> 74 #include <sparc/sparc/auxreg.h> 75 #include <sparc/sparc/auxiotwo.h> 76 #include <sparc/dev/cons.h> 77 78 #include "kbd.h" /* NKBD */ 79 #include "zs.h" /* NZS */ 80 81 /* Make life easier for the initialized arrays here. */ 82 #if NZS < 3 83 #undef NZS 84 #define NZS 3 85 #endif 86 87 /* 88 * Some warts needed by z8530tty.c - 89 * The default parity REALLY needs to be the same as the PROM uses, 90 * or you can not see messages done with printf during boot-up... 91 */ 92 int zs_def_cflag = (CREAD | CS8 | HUPCL); 93 94 /* 95 * The Sun provides a 4.9152 MHz clock to the ZS chips. 96 */ 97 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 98 99 /* 100 * Select software interrupt bit based on TTY ipl. 101 */ 102 #if PIL_TTY == 1 103 # define IE_ZSSOFT IE_L1 104 #elif PIL_TTY == 4 105 # define IE_ZSSOFT IE_L4 106 #elif PIL_TTY == 6 107 # define IE_ZSSOFT IE_L6 108 #else 109 # error "no suitable software interrupt bit" 110 #endif 111 112 #define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(2)) 113 114 /* The layout of this is hardware-dependent (padding, order). */ 115 struct zschan { 116 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 117 u_char zc_xxx0; 118 volatile u_char zc_data; /* data */ 119 u_char zc_xxx1; 120 }; 121 struct zsdevice { 122 /* Yes, they are backwards. */ 123 struct zschan zs_chan_b; 124 struct zschan zs_chan_a; 125 }; 126 127 /* ZS channel used as the console device (if any) */ 128 void *zs_conschan_get, *zs_conschan_put; 129 130 static u_char zs_init_reg[16] = { 131 0, /* 0: CMD (reset, etc.) */ 132 0, /* 1: No interrupts yet. */ 133 0, /* 2: IVECT */ 134 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 135 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 136 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 137 0, /* 6: TXSYNC/SYNCLO */ 138 0, /* 7: RXSYNC/SYNCHI */ 139 0, /* 8: alias for data port */ 140 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 141 0, /*10: Misc. TX/RX control bits */ 142 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 143 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 144 0, /*13: BAUDHI (default=9600) */ 145 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 146 ZSWR15_BREAK_IE, 147 }; 148 149 /* Console ops */ 150 static int zscngetc __P((dev_t)); 151 static void zscnputc __P((dev_t, int)); 152 static void zscnpollc __P((dev_t, int)); 153 154 struct consdev zs_consdev = { 155 NULL, 156 NULL, 157 zscngetc, 158 zscnputc, 159 zscnpollc, 160 NULL, 161 }; 162 163 164 /**************************************************************** 165 * Autoconfig 166 ****************************************************************/ 167 168 /* Definition of the driver for autoconfig. */ 169 static int zs_match_mainbus __P((struct device *, struct cfdata *, void *)); 170 static int zs_match_obio __P((struct device *, struct cfdata *, void *)); 171 static void zs_attach_mainbus __P((struct device *, struct device *, void *)); 172 static void zs_attach_obio __P((struct device *, struct device *, void *)); 173 174 #if defined(SUN4D) 175 #include <sparc/dev/bootbusvar.h> 176 177 static int zs_match_bootbus __P((struct device *, struct cfdata *, void *)); 178 static void zs_attach_bootbus __P((struct device *, struct device *, void *)); 179 180 CFATTACH_DECL(zs_bootbus, sizeof(struct zsc_softc), 181 zs_match_bootbus, zs_attach_bootbus, NULL, NULL); 182 #endif /* SUN4D */ 183 184 static void zs_attach __P((struct zsc_softc *, struct zsdevice *, int)); 185 static int zs_print __P((void *, const char *name)); 186 187 CFATTACH_DECL(zs_mainbus, sizeof(struct zsc_softc), 188 zs_match_mainbus, zs_attach_mainbus, NULL, NULL); 189 190 CFATTACH_DECL(zs_obio, sizeof(struct zsc_softc), 191 zs_match_obio, zs_attach_obio, NULL, NULL); 192 193 extern struct cfdriver zs_cd; 194 195 /* Interrupt handlers. */ 196 static int zshard __P((void *)); 197 static int zssoft __P((void *)); 198 199 static int zs_get_speed __P((struct zs_chanstate *)); 200 201 /* Console device support */ 202 static int zs_console_flags __P((int, int, int)); 203 204 /* Power management hooks */ 205 int zs_enable __P((struct zs_chanstate *)); 206 void zs_disable __P((struct zs_chanstate *)); 207 208 209 /* 210 * Is the zs chip present? 211 */ 212 static int 213 zs_match_mainbus(parent, cf, aux) 214 struct device *parent; 215 struct cfdata *cf; 216 void *aux; 217 { 218 struct mainbus_attach_args *ma = aux; 219 220 if (strcmp(cf->cf_name, ma->ma_name) != 0) 221 return (0); 222 223 return (1); 224 } 225 226 static int 227 zs_match_obio(parent, cf, aux) 228 struct device *parent; 229 struct cfdata *cf; 230 void *aux; 231 { 232 union obio_attach_args *uoba = aux; 233 struct obio4_attach_args *oba; 234 235 if (uoba->uoba_isobio4 == 0) { 236 struct sbus_attach_args *sa = &uoba->uoba_sbus; 237 238 if (strcmp(cf->cf_name, sa->sa_name) != 0) 239 return (0); 240 241 return (1); 242 } 243 244 oba = &uoba->uoba_oba4; 245 return (bus_space_probe(oba->oba_bustag, oba->oba_paddr, 246 1, 0, 0, NULL, NULL)); 247 } 248 249 #if defined(SUN4D) 250 static int 251 zs_match_bootbus(parent, cf, aux) 252 struct device *parent; 253 struct cfdata *cf; 254 void *aux; 255 { 256 struct bootbus_attach_args *baa = aux; 257 258 return (strcmp(cf->cf_name, baa->ba_name) == 0); 259 } 260 #endif /* SUN4D */ 261 262 static void 263 zs_attach_mainbus(parent, self, aux) 264 struct device *parent; 265 struct device *self; 266 void *aux; 267 { 268 struct zsc_softc *zsc = (void *) self; 269 struct mainbus_attach_args *ma = aux; 270 271 zsc->zsc_bustag = ma->ma_bustag; 272 zsc->zsc_dmatag = ma->ma_dmatag; 273 zsc->zsc_promunit = PROM_getpropint(ma->ma_node, "slave", -2); 274 zsc->zsc_node = ma->ma_node; 275 276 /* 277 * For machines with zs on mainbus (all sun4c models), we expect 278 * the device registers to be mapped by the PROM. 279 */ 280 zs_attach(zsc, ma->ma_promvaddr, ma->ma_pri); 281 } 282 283 static void 284 zs_attach_obio(parent, self, aux) 285 struct device *parent; 286 struct device *self; 287 void *aux; 288 { 289 struct zsc_softc *zsc = (void *) self; 290 union obio_attach_args *uoba = aux; 291 292 if (uoba->uoba_isobio4 == 0) { 293 struct sbus_attach_args *sa = &uoba->uoba_sbus; 294 void *va; 295 struct zs_chanstate *cs; 296 int channel; 297 298 if (sa->sa_nintr == 0) { 299 printf(" no interrupt lines\n"); 300 return; 301 } 302 303 /* 304 * Some sun4m models (Javastations) may not map the zs device. 305 */ 306 if (sa->sa_npromvaddrs > 0) 307 va = (void *)sa->sa_promvaddr; 308 else { 309 bus_space_handle_t bh; 310 311 if (sbus_bus_map(sa->sa_bustag, 312 sa->sa_slot, 313 sa->sa_offset, 314 sa->sa_size, 315 BUS_SPACE_MAP_LINEAR, &bh) != 0) { 316 printf(" cannot map zs registers\n"); 317 return; 318 } 319 va = (void *)bh; 320 } 321 322 /* 323 * Check if power state can be set, e.g. Tadpole 3GX 324 */ 325 if (PROM_getpropint(sa->sa_node, "pwr-on-auxio2", 0)) 326 { 327 printf (" powered via auxio2"); 328 for (channel = 0; channel < 2; channel++) { 329 cs = &zsc->zsc_cs_store[channel]; 330 cs->enable = zs_enable; 331 cs->disable = zs_disable; 332 } 333 } 334 335 zsc->zsc_bustag = sa->sa_bustag; 336 zsc->zsc_dmatag = sa->sa_dmatag; 337 zsc->zsc_promunit = PROM_getpropint(sa->sa_node, "slave", -2); 338 zsc->zsc_node = sa->sa_node; 339 zs_attach(zsc, va, sa->sa_pri); 340 } else { 341 struct obio4_attach_args *oba = &uoba->uoba_oba4; 342 bus_space_handle_t bh; 343 bus_addr_t paddr = oba->oba_paddr; 344 345 /* 346 * As for zs on mainbus, we require a PROM mapping. 347 */ 348 if (bus_space_map(oba->oba_bustag, 349 paddr, 350 sizeof(struct zsdevice), 351 BUS_SPACE_MAP_LINEAR | OBIO_BUS_MAP_USE_ROM, 352 &bh) != 0) { 353 printf(" cannot map zs registers\n"); 354 return; 355 } 356 zsc->zsc_bustag = oba->oba_bustag; 357 zsc->zsc_dmatag = oba->oba_dmatag; 358 /* 359 * Find prom unit by physical address 360 * We're just comparing the address (not the iospace) here 361 */ 362 paddr = BUS_ADDR_PADDR(paddr); 363 if (cpuinfo.cpu_type == CPUTYP_4_100) 364 /* 365 * On the sun4/100, the top-most 4 bits are zero 366 * on obio addresses; force them to 1's for the 367 * sake of the comparison here. 368 */ 369 paddr |= 0xf0000000; 370 zsc->zsc_promunit = 371 (paddr == 0xf1000000) ? 0 : 372 (paddr == 0xf0000000) ? 1 : 373 (paddr == 0xe0000000) ? 2 : -2; 374 375 zs_attach(zsc, (void *)bh, oba->oba_pri); 376 } 377 } 378 379 #if defined(SUN4D) 380 static void 381 zs_attach_bootbus(parent, self, aux) 382 struct device *parent; 383 struct device *self; 384 void *aux; 385 { 386 struct zsc_softc *zsc = (void *) self; 387 struct bootbus_attach_args *baa = aux; 388 void *va; 389 390 if (baa->ba_nintr == 0) { 391 printf(": no interrupt lines\n"); 392 return; 393 } 394 395 if (baa->ba_npromvaddrs > 0) 396 va = (void *) baa->ba_promvaddrs; 397 else { 398 bus_space_handle_t bh; 399 400 if (bus_space_map(baa->ba_bustag, 401 BUS_ADDR(baa->ba_slot, baa->ba_offset), 402 baa->ba_size, BUS_SPACE_MAP_LINEAR, &bh) != 0) { 403 printf(": cannot map zs registers\n"); 404 return; 405 } 406 va = (void *) bh; 407 } 408 409 zsc->zsc_bustag = baa->ba_bustag; 410 zsc->zsc_promunit = PROM_getpropint(baa->ba_node, "slave", -2); 411 zsc->zsc_node = baa->ba_node; 412 zs_attach(zsc, va, baa->ba_intr[0].oi_pri); 413 } 414 #endif /* SUN4D */ 415 416 /* 417 * Attach a found zs. 418 * 419 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 420 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 421 */ 422 static void 423 zs_attach(zsc, zsd, pri) 424 struct zsc_softc *zsc; 425 struct zsdevice *zsd; 426 int pri; 427 { 428 struct zsc_attach_args zsc_args; 429 struct zs_chanstate *cs; 430 int s, channel; 431 static int didintr, prevpri; 432 433 if (zsd == NULL) { 434 printf("configuration incomplete\n"); 435 return; 436 } 437 438 printf(" softpri %d\n", PIL_TTY); 439 440 /* 441 * Initialize software state for each channel. 442 */ 443 for (channel = 0; channel < 2; channel++) { 444 struct zschan *zc; 445 446 zsc_args.channel = channel; 447 cs = &zsc->zsc_cs_store[channel]; 448 zsc->zsc_cs[channel] = cs; 449 450 cs->cs_channel = channel; 451 cs->cs_private = NULL; 452 cs->cs_ops = &zsops_null; 453 cs->cs_brg_clk = PCLK / 16; 454 455 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 456 457 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 458 zsc->zsc_node, 459 channel); 460 461 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 462 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 463 zsc_args.consdev = &zs_consdev; 464 } 465 466 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 467 zs_conschan_get = zc; 468 } 469 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 470 zs_conschan_put = zc; 471 } 472 /* Childs need to set cn_dev, etc */ 473 474 cs->cs_reg_csr = &zc->zc_csr; 475 cs->cs_reg_data = &zc->zc_data; 476 477 bcopy(zs_init_reg, cs->cs_creg, 16); 478 bcopy(zs_init_reg, cs->cs_preg, 16); 479 480 /* XXX: Consult PROM properties for this?! */ 481 cs->cs_defspeed = zs_get_speed(cs); 482 cs->cs_defcflag = zs_def_cflag; 483 484 /* Make these correspond to cs_defcflag (-crtscts) */ 485 cs->cs_rr0_dcd = ZSRR0_DCD; 486 cs->cs_rr0_cts = 0; 487 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 488 cs->cs_wr5_rts = 0; 489 490 /* 491 * Clear the master interrupt enable. 492 * The INTENA is common to both channels, 493 * so just do it on the A channel. 494 */ 495 if (channel == 0) { 496 zs_write_reg(cs, 9, 0); 497 } 498 499 /* 500 * Look for a child driver for this channel. 501 * The child attach will setup the hardware. 502 */ 503 if (!config_found(&zsc->zsc_dev, (void *)&zsc_args, zs_print)) { 504 /* No sub-driver. Just reset it. */ 505 u_char reset = (channel == 0) ? 506 ZSWR9_A_RESET : ZSWR9_B_RESET; 507 s = splzs(); 508 zs_write_reg(cs, 9, reset); 509 splx(s); 510 } 511 } 512 513 /* 514 * Now safe to install interrupt handlers. Note the arguments 515 * to the interrupt handlers aren't used. Note, we only do this 516 * once since both SCCs interrupt at the same level and vector. 517 */ 518 if (!didintr) { 519 didintr = 1; 520 prevpri = pri; 521 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, 0, 522 zshard, NULL); 523 bus_intr_establish(zsc->zsc_bustag, PIL_TTY, 524 IPL_SOFTSERIAL, 525 BUS_INTR_ESTABLISH_SOFTINTR, 526 zssoft, NULL); 527 } else if (pri != prevpri) 528 panic("broken zs interrupt scheme"); 529 530 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 531 zsc->zsc_dev.dv_xname, "intr"); 532 533 /* 534 * Set the master interrupt enable and interrupt vector. 535 * (common to both channels, do it on A) 536 */ 537 cs = zsc->zsc_cs[0]; 538 s = splhigh(); 539 /* interrupt vector */ 540 zs_write_reg(cs, 2, zs_init_reg[2]); 541 /* master interrupt control (enable) */ 542 zs_write_reg(cs, 9, zs_init_reg[9]); 543 splx(s); 544 545 #if 0 546 /* 547 * XXX: L1A hack - We would like to be able to break into 548 * the debugger during the rest of autoconfiguration, so 549 * lower interrupts just enough to let zs interrupts in. 550 * This is done after both zs devices are attached. 551 */ 552 if (zsc->zsc_promunit == 1) { 553 printf("zs1: enabling zs interrupts\n"); 554 (void)splfd(); /* XXX: splzs - 1 */ 555 } 556 #endif 557 } 558 559 static int 560 zs_print(aux, name) 561 void *aux; 562 const char *name; 563 { 564 struct zsc_attach_args *args = aux; 565 566 if (name != NULL) 567 printf("%s: ", name); 568 569 if (args->channel != -1) 570 printf(" channel %d", args->channel); 571 572 return (UNCONF); 573 } 574 575 static volatile int zssoftpending; 576 577 /* 578 * Our ZS chips all share a common, autovectored interrupt, 579 * so we have to look at all of them on each interrupt. 580 */ 581 static int 582 zshard(arg) 583 void *arg; 584 { 585 struct zsc_softc *zsc; 586 int unit, rr3, rval, softreq; 587 588 rval = softreq = 0; 589 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 590 struct zs_chanstate *cs; 591 592 zsc = zs_cd.cd_devs[unit]; 593 if (zsc == NULL) 594 continue; 595 rr3 = zsc_intr_hard(zsc); 596 /* Count up the interrupts. */ 597 if (rr3) { 598 rval |= rr3; 599 zsc->zsc_intrcnt.ev_count++; 600 } 601 if ((cs = zsc->zsc_cs[0]) != NULL) 602 softreq |= cs->cs_softreq; 603 if ((cs = zsc->zsc_cs[1]) != NULL) 604 softreq |= cs->cs_softreq; 605 } 606 607 /* We are at splzs here, so no need to lock. */ 608 if (softreq && (zssoftpending == 0)) { 609 zssoftpending = IE_ZSSOFT; 610 #if defined(SUN4M) 611 if (CPU_ISSUN4M) 612 raise(0, PIL_TTY); 613 else 614 #endif 615 ienab_bis(IE_ZSSOFT); 616 } 617 return (rval); 618 } 619 620 /* 621 * Similar scheme as for zshard (look at all of them) 622 */ 623 static int 624 zssoft(arg) 625 void *arg; 626 { 627 struct zsc_softc *zsc; 628 int s, unit; 629 630 /* This is not the only ISR on this IPL. */ 631 if (zssoftpending == 0) 632 return (0); 633 634 /* 635 * The soft intr. bit will be set by zshard only if 636 * the variable zssoftpending is zero. The order of 637 * these next two statements prevents our clearing 638 * the soft intr bit just after zshard has set it. 639 */ 640 /* ienab_bic(IE_ZSSOFT); */ 641 zssoftpending = 0; 642 643 /* Make sure we call the tty layer at spltty. */ 644 s = spltty(); 645 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 646 zsc = zs_cd.cd_devs[unit]; 647 if (zsc == NULL) 648 continue; 649 (void)zsc_intr_soft(zsc); 650 } 651 splx(s); 652 return (1); 653 } 654 655 656 /* 657 * Compute the current baud rate given a ZS channel. 658 */ 659 static int 660 zs_get_speed(cs) 661 struct zs_chanstate *cs; 662 { 663 int tconst; 664 665 tconst = zs_read_reg(cs, 12); 666 tconst |= zs_read_reg(cs, 13) << 8; 667 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 668 } 669 670 /* 671 * MD functions for setting the baud rate and control modes. 672 */ 673 int 674 zs_set_speed(cs, bps) 675 struct zs_chanstate *cs; 676 int bps; /* bits per second */ 677 { 678 int tconst, real_bps; 679 680 if (bps == 0) 681 return (0); 682 683 #ifdef DIAGNOSTIC 684 if (cs->cs_brg_clk == 0) 685 panic("zs_set_speed"); 686 #endif 687 688 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 689 if (tconst < 0) 690 return (EINVAL); 691 692 /* Convert back to make sure we can do it. */ 693 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 694 695 /* XXX - Allow some tolerance here? */ 696 if (real_bps != bps) 697 return (EINVAL); 698 699 cs->cs_preg[12] = tconst; 700 cs->cs_preg[13] = tconst >> 8; 701 702 /* Caller will stuff the pending registers. */ 703 return (0); 704 } 705 706 int 707 zs_set_modes(cs, cflag) 708 struct zs_chanstate *cs; 709 int cflag; /* bits per second */ 710 { 711 int s; 712 713 /* 714 * Output hardware flow control on the chip is horrendous: 715 * if carrier detect drops, the receiver is disabled, and if 716 * CTS drops, the transmitter is stoped IN MID CHARACTER! 717 * Therefore, NEVER set the HFC bit, and instead use the 718 * status interrupt to detect CTS changes. 719 */ 720 s = splzs(); 721 cs->cs_rr0_pps = 0; 722 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 723 cs->cs_rr0_dcd = 0; 724 if ((cflag & MDMBUF) == 0) 725 cs->cs_rr0_pps = ZSRR0_DCD; 726 } else 727 cs->cs_rr0_dcd = ZSRR0_DCD; 728 if ((cflag & CRTSCTS) != 0) { 729 cs->cs_wr5_dtr = ZSWR5_DTR; 730 cs->cs_wr5_rts = ZSWR5_RTS; 731 cs->cs_rr0_cts = ZSRR0_CTS; 732 } else if ((cflag & CDTRCTS) != 0) { 733 cs->cs_wr5_dtr = 0; 734 cs->cs_wr5_rts = ZSWR5_DTR; 735 cs->cs_rr0_cts = ZSRR0_CTS; 736 } else if ((cflag & MDMBUF) != 0) { 737 cs->cs_wr5_dtr = 0; 738 cs->cs_wr5_rts = ZSWR5_DTR; 739 cs->cs_rr0_cts = ZSRR0_DCD; 740 } else { 741 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 742 cs->cs_wr5_rts = 0; 743 cs->cs_rr0_cts = 0; 744 } 745 splx(s); 746 747 /* Caller will stuff the pending registers. */ 748 return (0); 749 } 750 751 752 /* 753 * Read or write the chip with suitable delays. 754 */ 755 756 u_char 757 zs_read_reg(cs, reg) 758 struct zs_chanstate *cs; 759 u_char reg; 760 { 761 u_char val; 762 763 *cs->cs_reg_csr = reg; 764 ZS_DELAY(); 765 val = *cs->cs_reg_csr; 766 ZS_DELAY(); 767 return (val); 768 } 769 770 void 771 zs_write_reg(cs, reg, val) 772 struct zs_chanstate *cs; 773 u_char reg, val; 774 { 775 *cs->cs_reg_csr = reg; 776 ZS_DELAY(); 777 *cs->cs_reg_csr = val; 778 ZS_DELAY(); 779 } 780 781 u_char 782 zs_read_csr(cs) 783 struct zs_chanstate *cs; 784 { 785 u_char val; 786 787 val = *cs->cs_reg_csr; 788 ZS_DELAY(); 789 return (val); 790 } 791 792 void 793 zs_write_csr(cs, val) 794 struct zs_chanstate *cs; 795 u_char val; 796 { 797 *cs->cs_reg_csr = val; 798 ZS_DELAY(); 799 } 800 801 u_char 802 zs_read_data(cs) 803 struct zs_chanstate *cs; 804 { 805 u_char val; 806 807 val = *cs->cs_reg_data; 808 ZS_DELAY(); 809 return (val); 810 } 811 812 void zs_write_data(cs, val) 813 struct zs_chanstate *cs; 814 u_char val; 815 { 816 *cs->cs_reg_data = val; 817 ZS_DELAY(); 818 } 819 820 /**************************************************************** 821 * Console support functions (Sun specific!) 822 * Note: this code is allowed to know about the layout of 823 * the chip registers, and uses that to keep things simple. 824 * XXX - I think I like the mvme167 code better. -gwr 825 ****************************************************************/ 826 827 /* 828 * Handle user request to enter kernel debugger. 829 */ 830 void 831 zs_abort(cs) 832 struct zs_chanstate *cs; 833 { 834 struct zschan *zc = zs_conschan_get; 835 int rr0; 836 837 /* Wait for end of break to avoid PROM abort. */ 838 /* XXX - Limit the wait? */ 839 do { 840 rr0 = zc->zc_csr; 841 ZS_DELAY(); 842 } while (rr0 & ZSRR0_BREAK); 843 844 #if defined(KGDB) 845 zskgdb(cs); 846 #elif defined(DDB) 847 Debugger(); 848 #else 849 printf("stopping on keyboard abort\n"); 850 callrom(); 851 #endif 852 } 853 854 int zs_getc __P((void *arg)); 855 void zs_putc __P((void *arg, int c)); 856 857 /* 858 * Polled input char. 859 */ 860 int 861 zs_getc(arg) 862 void *arg; 863 { 864 struct zschan *zc = arg; 865 int s, c, rr0; 866 867 s = splhigh(); 868 /* Wait for a character to arrive. */ 869 do { 870 rr0 = zc->zc_csr; 871 ZS_DELAY(); 872 } while ((rr0 & ZSRR0_RX_READY) == 0); 873 874 c = zc->zc_data; 875 ZS_DELAY(); 876 splx(s); 877 878 /* 879 * This is used by the kd driver to read scan codes, 880 * so don't translate '\r' ==> '\n' here... 881 */ 882 return (c); 883 } 884 885 /* 886 * Polled output char. 887 */ 888 void 889 zs_putc(arg, c) 890 void *arg; 891 int c; 892 { 893 struct zschan *zc = arg; 894 int s, rr0; 895 896 s = splhigh(); 897 898 /* Wait for transmitter to become ready. */ 899 do { 900 rr0 = zc->zc_csr; 901 ZS_DELAY(); 902 } while ((rr0 & ZSRR0_TX_READY) == 0); 903 904 /* 905 * Send the next character. 906 * Now you'd think that this could be followed by a ZS_DELAY() 907 * just like all the other chip accesses, but it turns out that 908 * the `transmit-ready' interrupt isn't de-asserted until 909 * some period of time after the register write completes 910 * (more than a couple instructions). So to avoid stray 911 * interrupts we put in the 2us delay regardless of cpu model. 912 */ 913 zc->zc_data = c; 914 delay(2); 915 916 splx(s); 917 } 918 919 /*****************************************************************/ 920 /* 921 * Polled console input putchar. 922 */ 923 int 924 zscngetc(dev) 925 dev_t dev; 926 { 927 return (zs_getc(zs_conschan_get)); 928 } 929 930 /* 931 * Polled console output putchar. 932 */ 933 void 934 zscnputc(dev, c) 935 dev_t dev; 936 int c; 937 { 938 zs_putc(zs_conschan_put, c); 939 } 940 941 void 942 zscnpollc(dev, on) 943 dev_t dev; 944 int on; 945 { 946 /* No action needed */ 947 } 948 949 int 950 zs_console_flags(promunit, node, channel) 951 int promunit; 952 int node; 953 int channel; 954 { 955 int cookie, flags = 0; 956 957 switch (prom_version()) { 958 case PROM_OLDMON: 959 case PROM_OBP_V0: 960 /* 961 * Use `promunit' and `channel' to derive the PROM 962 * stdio handles that correspond to this device. 963 */ 964 if (promunit == 0) 965 cookie = PROMDEV_TTYA + channel; 966 else if (promunit == 1 && channel == 0) 967 cookie = PROMDEV_KBD; 968 else 969 cookie = -1; 970 971 if (cookie == prom_stdin()) 972 flags |= ZS_HWFLAG_CONSOLE_INPUT; 973 974 /* 975 * Prevent the keyboard from matching the output device 976 * (note that PROMDEV_KBD == PROMDEV_SCREEN == 0!). 977 */ 978 if (cookie != PROMDEV_KBD && cookie == prom_stdout()) 979 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 980 981 break; 982 983 case PROM_OBP_V2: 984 case PROM_OBP_V3: 985 case PROM_OPENFIRM: 986 987 /* 988 * Match the nodes and device arguments prepared by 989 * consinit() against our device node and channel. 990 * (The device argument is the part of the OBP path 991 * following the colon, as in `/obio/zs@0,100000:a') 992 */ 993 994 /* Default to channel 0 if there are no explicit prom args */ 995 cookie = 0; 996 997 if (node == prom_stdin_node) { 998 if (prom_stdin_args[0] != '\0') 999 /* Translate (a,b) -> (0,1) */ 1000 cookie = prom_stdin_args[0] - 'a'; 1001 1002 if (channel == cookie) 1003 flags |= ZS_HWFLAG_CONSOLE_INPUT; 1004 } 1005 1006 if (node == prom_stdout_node) { 1007 if (prom_stdout_args[0] != '\0') 1008 /* Translate (a,b) -> (0,1) */ 1009 cookie = prom_stdout_args[0] - 'a'; 1010 1011 if (channel == cookie) 1012 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 1013 } 1014 1015 break; 1016 1017 default: 1018 break; 1019 } 1020 1021 return (flags); 1022 } 1023 1024 /* 1025 * Power management hooks for zsopen() and zsclose(). 1026 * We use them to power on/off the ports, if necessary. 1027 */ 1028 int 1029 zs_enable(cs) 1030 struct zs_chanstate *cs; 1031 { 1032 auxiotwoserialendis (ZS_ENABLE); 1033 cs->enabled = 1; 1034 return(0); 1035 } 1036 1037 void 1038 zs_disable(cs) 1039 struct zs_chanstate *cs; 1040 { 1041 auxiotwoserialendis (ZS_DISABLE); 1042 cs->enabled = 0; 1043 } 1044