1 /* $NetBSD: fpu.c,v 1.15 2002/01/19 03:30:54 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 #include <sys/param.h> 48 #include <sys/proc.h> 49 #include <sys/signal.h> 50 #include <sys/systm.h> 51 #include <sys/syslog.h> 52 #include <sys/signalvar.h> 53 54 #include <machine/instr.h> 55 #include <machine/reg.h> 56 57 #include <sparc/fpu/fpu_emu.h> 58 #include <sparc/fpu/fpu_extern.h> 59 60 int fpe_debug = 0; 61 62 #ifdef DEBUG 63 /* 64 * Dump a `fpn' structure. 65 */ 66 void 67 fpu_dumpfpn(struct fpn *fp) 68 { 69 static char *class[] = { 70 "SNAN", "QNAN", "ZERO", "NUM", "INF" 71 }; 72 73 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 74 fp->fp_sign ? '-' : ' ', 75 fp->fp_mant[0], fp->fp_mant[1], 76 fp->fp_mant[2], fp->fp_mant[3], 77 fp->fp_exp); 78 } 79 #endif 80 81 /* 82 * fpu_execute returns the following error numbers (0 = no error): 83 */ 84 #define FPE 1 /* take a floating point exception */ 85 #define NOTFPU 2 /* not an FPU instruction */ 86 87 /* 88 * Translate current exceptions into `first' exception. The 89 * bits go the wrong way for ffs() (0x10 is most important, etc). 90 * There are only 5, so do it the obvious way. 91 */ 92 #define X1(x) x 93 #define X2(x) x,x 94 #define X4(x) x,x,x,x 95 #define X8(x) X4(x),X4(x) 96 #define X16(x) X8(x),X8(x) 97 98 static char cx_to_trapx[] = { 99 X1(FSR_NX), 100 X2(FSR_DZ), 101 X4(FSR_UF), 102 X8(FSR_OF), 103 X16(FSR_NV) 104 }; 105 static u_char fpu_codes[] = { 106 X1(FPE_FLTINEX_TRAP), 107 X2(FPE_FLTDIV_TRAP), 108 X4(FPE_FLTUND_TRAP), 109 X8(FPE_FLTOVF_TRAP), 110 X16(FPE_FLTOPERR_TRAP) 111 }; 112 113 /* 114 * The FPU gave us an exception. Clean up the mess. Note that the 115 * fp queue can only have FPops in it, never load/store FP registers 116 * nor FBfcc instructions. Experiments with `crashme' prove that 117 * unknown FPops do enter the queue, however. 118 */ 119 void 120 fpu_cleanup(p, fs) 121 register struct proc *p; 122 #ifndef SUN4U 123 register struct fpstate *fs; 124 #else /* SUN4U */ 125 register struct fpstate64 *fs; 126 #endif /* SUN4U */ 127 { 128 register int i, fsr = fs->fs_fsr, error; 129 union instr instr; 130 struct fpemu fe; 131 132 switch ((fsr >> FSR_FTT_SHIFT) & FSR_FTT_MASK) { 133 134 case FSR_TT_NONE: 135 panic("fpu_cleanup: No fault"); /* ??? */ 136 break; 137 138 case FSR_TT_IEEE: 139 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_IEEE\n")); 140 /* XXX missing trap address! */ 141 if ((i = fsr & FSR_CX) == 0) 142 panic("fpu ieee trap, but no exception"); 143 trapsignal(p, SIGFPE, fpu_codes[i - 1]); 144 break; /* XXX should return, but queue remains */ 145 146 case FSR_TT_UNFIN: 147 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_UNFIN\n")); 148 #ifdef SUN4U 149 if (fs->fs_qsize == 0) { 150 printf("fpu_cleanup: unfinished fpop"); 151 /* The book sez reexecute or emulate. */ 152 return; 153 } 154 break; 155 156 #endif /* SUN4U */ 157 case FSR_TT_UNIMP: 158 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_UNIMP\n")); 159 if (fs->fs_qsize == 0) 160 panic("fpu_cleanup: unimplemented fpop"); 161 break; 162 163 case FSR_TT_SEQ: 164 panic("fpu sequence error"); 165 /* NOTREACHED */ 166 167 case FSR_TT_HWERR: 168 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_HWERR\n")); 169 log(LOG_ERR, "fpu hardware error (%s[%d])\n", 170 p->p_comm, p->p_pid); 171 uprintf("%s[%d]: fpu hardware error\n", p->p_comm, p->p_pid); 172 trapsignal(p, SIGFPE, -1); /* ??? */ 173 goto out; 174 175 default: 176 printf("fsr=0x%x\n", fsr); 177 panic("fpu error"); 178 } 179 180 /* emulate the instructions left in the queue */ 181 fe.fe_fpstate = fs; 182 for (i = 0; i < fs->fs_qsize; i++) { 183 instr.i_int = fs->fs_queue[i].fq_instr; 184 if (instr.i_any.i_op != IOP_reg || 185 (instr.i_op3.i_op3 != IOP3_FPop1 && 186 instr.i_op3.i_op3 != IOP3_FPop2)) 187 panic("bogus fpu queue"); 188 error = fpu_execute(&fe, instr); 189 switch (error) { 190 191 case 0: 192 continue; 193 194 case FPE: 195 trapsignal(p, SIGFPE, 196 fpu_codes[(fs->fs_fsr & FSR_CX) - 1]); 197 break; 198 199 case NOTFPU: 200 #ifdef SUN4U 201 #ifdef DEBUG 202 printf("fpu_cleanup: not an FPU error -- sending SIGILL\n"); 203 Debugger(); 204 #endif 205 #endif /* SUN4U */ 206 trapsignal(p, SIGILL, 0); /* ??? code? */ 207 break; 208 209 default: 210 panic("fpu_cleanup 3"); 211 /* NOTREACHED */ 212 } 213 /* XXX should stop here, but queue remains */ 214 } 215 out: 216 fs->fs_qsize = 0; 217 } 218 219 #ifdef notyet 220 /* 221 * If we have no FPU at all (are there any machines like this out 222 * there!?) we have to emulate each instruction, and we need a pointer 223 * to the trapframe so that we can step over them and do FBfcc's. 224 * We know the `queue' is empty, though; we just want to emulate 225 * the instruction at tf->tf_pc. 226 */ 227 fpu_emulate(p, tf, fs) 228 struct proc *p; 229 register struct trapframe *tf; 230 #ifndef SUN4U 231 register struct fpstate *fs; 232 #else /* SUN4U */ 233 register struct fpstate64 *fs; 234 #endif /* SUN4U */ 235 { 236 237 do { 238 fetch instr from pc 239 decode 240 if (integer instr) { 241 /* 242 * We do this here, rather than earlier, to avoid 243 * losing even more badly than usual. 244 */ 245 if (p->p_addr->u_pcb.pcb_uw) { 246 write_user_windows(); 247 if (rwindow_save(p)) 248 sigexit(p, SIGILL); 249 } 250 if (loadstore) { 251 do_it; 252 pc = npc, npc += 4 253 } else if (fbfcc) { 254 do_annul_stuff; 255 } else 256 return; 257 } else if (fpu instr) { 258 fe.fe_fsr = fs->fs_fsr &= ~FSR_CX; 259 error = fpu_execute(&fe, fs, instr); 260 switch (error) { 261 etc; 262 } 263 } else 264 return; 265 if (want to reschedule) 266 return; 267 } while (error == 0); 268 } 269 #endif 270 271 /* 272 * Execute an FPU instruction (one that runs entirely in the FPU; not 273 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 274 * modified to reflect the setting the hardware would have left. 275 * 276 * Note that we do not catch all illegal opcodes, so you can, for instance, 277 * multiply two integers this way. 278 */ 279 int 280 fpu_execute(fe, instr) 281 register struct fpemu *fe; 282 union instr instr; 283 { 284 register struct fpn *fp; 285 #ifndef SUN4U 286 register int opf, rs1, rs2, rd, type, mask, fsr, cx; 287 register struct fpstate *fs; 288 #else /* SUN4U */ 289 register int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; 290 register struct fpstate64 *fs; 291 #endif /* SUN4U */ 292 u_int space[4]; 293 294 /* 295 * `Decode' and execute instruction. Start with no exceptions. 296 * The type of any i_opf opcode is in the bottom two bits, so we 297 * squish them out here. 298 */ 299 opf = instr.i_opf.i_opf; 300 /* 301 * The low two bits of the opf field for floating point insns usually 302 * correspond to the operation width: 303 * 304 * 0: Invalid 305 * 1: Single precision float 306 * 2: Double precision float 307 * 3: Quad precision float 308 * 309 * The exceptions are the integer to float conversion instructions. 310 * 311 * For double and quad precision, the low bit if the rs or rd field 312 * is actually the high bit of the register number. 313 */ 314 315 type = opf & 3; 316 mask = 0x3 >> (3 - type); 317 318 rs1 = instr.i_opf.i_rs1; 319 rs1 = (rs1 & ~mask) | ((rs1 & mask & 0x1) << 5); 320 rs2 = instr.i_opf.i_rs2; 321 rs2 = (rs2 & ~mask) | ((rs2 & mask & 0x1) << 5); 322 rd = instr.i_opf.i_rd; 323 rd = (rd & ~mask) | ((rd & mask & 0x1) << 5); 324 #ifdef DIAGNOSTIC 325 if ((rs1 | rs2 | rd) & mask) 326 /* This may be an FPU insn but it is illegal. */ 327 return (NOTFPU); 328 #endif 329 fs = fe->fe_fpstate; 330 fe->fe_fsr = fs->fs_fsr & ~FSR_CX; 331 fe->fe_cx = 0; 332 #ifdef SUN4U 333 /* 334 * Check to see if we're dealing with a fancy cmove and handle 335 * it first. 336 */ 337 if (instr.i_op3.i_op3 == IOP3_FPop2 && (opf&0xff0) != (FCMP&0xff0)) { 338 switch (opf >>= 2) { 339 case FMVFC0 >> 2: 340 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC0\n")); 341 cond = (fs->fs_fsr>>FSR_FCC_SHIFT)&FSR_FCC_MASK; 342 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 343 rs1 = fs->fs_regs[rs2]; 344 goto mov; 345 case FMVFC1 >> 2: 346 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC1\n")); 347 cond = (fs->fs_fsr>>FSR_FCC1_SHIFT)&FSR_FCC_MASK; 348 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 349 rs1 = fs->fs_regs[rs2]; 350 goto mov; 351 case FMVFC2 >> 2: 352 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC2\n")); 353 cond = (fs->fs_fsr>>FSR_FCC2_SHIFT)&FSR_FCC_MASK; 354 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 355 rs1 = fs->fs_regs[rs2]; 356 goto mov; 357 case FMVFC3 >> 2: 358 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC3\n")); 359 cond = (fs->fs_fsr>>FSR_FCC3_SHIFT)&FSR_FCC_MASK; 360 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 361 rs1 = fs->fs_regs[rs2]; 362 goto mov; 363 case FMVIC >> 2: 364 /* Presume we're curproc */ 365 DPRINTF(FPE_INSN, ("fpu_execute: FMVIC\n")); 366 cond = (curproc->p_md.md_tf->tf_tstate>>TSTATE_CCR_SHIFT)&PSR_ICC; 367 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 368 rs1 = fs->fs_regs[rs2]; 369 goto mov; 370 case FMVXC >> 2: 371 /* Presume we're curproc */ 372 DPRINTF(FPE_INSN, ("fpu_execute: FMVXC\n")); 373 cond = (curproc->p_md.md_tf->tf_tstate>>(TSTATE_CCR_SHIFT+XCC_SHIFT))&PSR_ICC; 374 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 375 rs1 = fs->fs_regs[rs2]; 376 goto mov; 377 case FMVRZ >> 2: 378 /* Presume we're curproc */ 379 DPRINTF(FPE_INSN, ("fpu_execute: FMVRZ\n")); 380 rs1 = instr.i_fmovr.i_rs1; 381 if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] != 0) 382 return (0); /* success */ 383 rs1 = fs->fs_regs[rs2]; 384 goto mov; 385 case FMVRLEZ >> 2: 386 /* Presume we're curproc */ 387 DPRINTF(FPE_INSN, ("fpu_execute: FMVRLEZ\n")); 388 rs1 = instr.i_fmovr.i_rs1; 389 if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] > 0) 390 return (0); /* success */ 391 rs1 = fs->fs_regs[rs2]; 392 goto mov; 393 case FMVRLZ >> 2: 394 /* Presume we're curproc */ 395 DPRINTF(FPE_INSN, ("fpu_execute: FMVRLZ\n")); 396 rs1 = instr.i_fmovr.i_rs1; 397 if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] >= 0) 398 return (0); /* success */ 399 rs1 = fs->fs_regs[rs2]; 400 goto mov; 401 case FMVRNZ >> 2: 402 /* Presume we're curproc */ 403 DPRINTF(FPE_INSN, ("fpu_execute: FMVRNZ\n")); 404 rs1 = instr.i_fmovr.i_rs1; 405 if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] == 0) 406 return (0); /* success */ 407 rs1 = fs->fs_regs[rs2]; 408 goto mov; 409 case FMVRGZ >> 2: 410 /* Presume we're curproc */ 411 DPRINTF(FPE_INSN, ("fpu_execute: FMVRGZ\n")); 412 rs1 = instr.i_fmovr.i_rs1; 413 if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] <= 0) 414 return (0); /* success */ 415 rs1 = fs->fs_regs[rs2]; 416 goto mov; 417 case FMVRGEZ >> 2: 418 /* Presume we're curproc */ 419 DPRINTF(FPE_INSN, ("fpu_execute: FMVRGEZ\n")); 420 rs1 = instr.i_fmovr.i_rs1; 421 if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] < 0) 422 return (0); /* success */ 423 rs1 = fs->fs_regs[rs2]; 424 goto mov; 425 default: 426 DPRINTF(FPE_INSN, 427 ("fpu_execute: unknown v9 FP inst %x opf %x\n", 428 instr.i_int, opf)); 429 return (NOTFPU); 430 } 431 } 432 #endif /* SUN4U */ 433 switch (opf >>= 2) { 434 435 default: 436 DPRINTF(FPE_INSN, 437 ("fpu_execute: unknown basic FP inst %x opf %x\n", 438 instr.i_int, opf)); 439 return (NOTFPU); 440 441 case FMOV >> 2: /* these should all be pretty obvious */ 442 DPRINTF(FPE_INSN, ("fpu_execute: FMOV\n")); 443 rs1 = fs->fs_regs[rs2]; 444 goto mov; 445 446 case FNEG >> 2: 447 DPRINTF(FPE_INSN, ("fpu_execute: FNEG\n")); 448 rs1 = fs->fs_regs[rs2] ^ (1 << 31); 449 goto mov; 450 451 case FABS >> 2: 452 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 453 rs1 = fs->fs_regs[rs2] & ~(1 << 31); 454 mov: 455 #ifndef SUN4U 456 fs->fs_regs[rd] = rs1; 457 #else /* SUN4U */ 458 i = 1<<(type-1); 459 fs->fs_regs[rd++] = rs1; 460 while (--i > 0) 461 fs->fs_regs[rd++] = fs->fs_regs[++rs2]; 462 #endif /* SUN4U */ 463 fs->fs_fsr = fe->fe_fsr; 464 return (0); /* success */ 465 466 case FSQRT >> 2: 467 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 468 fpu_explode(fe, &fe->fe_f1, type, rs2); 469 fp = fpu_sqrt(fe); 470 break; 471 472 case FADD >> 2: 473 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 474 fpu_explode(fe, &fe->fe_f1, type, rs1); 475 fpu_explode(fe, &fe->fe_f2, type, rs2); 476 fp = fpu_add(fe); 477 break; 478 479 case FSUB >> 2: 480 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 481 fpu_explode(fe, &fe->fe_f1, type, rs1); 482 fpu_explode(fe, &fe->fe_f2, type, rs2); 483 fp = fpu_sub(fe); 484 break; 485 486 case FMUL >> 2: 487 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 488 fpu_explode(fe, &fe->fe_f1, type, rs1); 489 fpu_explode(fe, &fe->fe_f2, type, rs2); 490 fp = fpu_mul(fe); 491 break; 492 493 case FDIV >> 2: 494 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 495 fpu_explode(fe, &fe->fe_f1, type, rs1); 496 fpu_explode(fe, &fe->fe_f2, type, rs2); 497 fp = fpu_div(fe); 498 break; 499 500 case FCMP >> 2: 501 DPRINTF(FPE_INSN, ("fpu_execute: FCMP\n")); 502 fpu_explode(fe, &fe->fe_f1, type, rs1); 503 fpu_explode(fe, &fe->fe_f2, type, rs2); 504 fpu_compare(fe, 0); 505 goto cmpdone; 506 507 case FCMPE >> 2: 508 DPRINTF(FPE_INSN, ("fpu_execute: FCMPE\n")); 509 fpu_explode(fe, &fe->fe_f1, type, rs1); 510 fpu_explode(fe, &fe->fe_f2, type, rs2); 511 fpu_compare(fe, 1); 512 cmpdone: 513 /* 514 * The only possible exception here is NV; catch it 515 * early and get out, as there is no result register. 516 */ 517 cx = fe->fe_cx; 518 fsr = fe->fe_fsr | (cx << FSR_CX_SHIFT); 519 if (cx != 0) { 520 if (fsr & (FSR_NV << FSR_TEM_SHIFT)) { 521 fs->fs_fsr = (fsr & ~FSR_FTT) | 522 (FSR_TT_IEEE << FSR_FTT_SHIFT); 523 return (FPE); 524 } 525 fsr |= FSR_NV << FSR_AX_SHIFT; 526 } 527 fs->fs_fsr = fsr; 528 return (0); 529 530 case FSMULD >> 2: 531 case FDMULX >> 2: 532 DPRINTF(FPE_INSN, ("fpu_execute: FSMULx\n")); 533 if (type == FTYPE_EXT) 534 return (NOTFPU); 535 fpu_explode(fe, &fe->fe_f1, type, rs1); 536 fpu_explode(fe, &fe->fe_f2, type, rs2); 537 type++; /* single to double, or double to quad */ 538 fp = fpu_mul(fe); 539 break; 540 541 #ifdef SUN4U 542 case FXTOS >> 2: 543 case FXTOD >> 2: 544 case FXTOQ >> 2: 545 DPRINTF(FPE_INSN, ("fpu_execute: FXTOx\n")); 546 type = FTYPE_LNG; 547 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 548 type = opf & 3; /* sneaky; depends on instruction encoding */ 549 break; 550 551 case FTOX >> 2: 552 DPRINTF(FPE_INSN, ("fpu_execute: FTOX\n")); 553 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 554 type = FTYPE_LNG; 555 /* Recalculate destination register */ 556 rd = instr.i_opf.i_rd; 557 break; 558 559 #endif /* SUN4U */ 560 case FTOI >> 2: 561 DPRINTF(FPE_INSN, ("fpu_execute: FTOI\n")); 562 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 563 type = FTYPE_INT; 564 /* Recalculate destination register */ 565 rd = instr.i_opf.i_rd; 566 break; 567 568 case FTOS >> 2: 569 case FTOD >> 2: 570 case FTOQ >> 2: 571 DPRINTF(FPE_INSN, ("fpu_execute: FTOx\n")); 572 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 573 /* Recalculate rd with correct type info. */ 574 type = opf & 3; /* sneaky; depends on instruction encoding */ 575 mask = 0x3 >> (3 - type); 576 rd = instr.i_opf.i_rd; 577 rd = (rd & ~mask) | ((rd & mask & 0x1) << 5); 578 break; 579 } 580 581 /* 582 * ALU operation is complete. Collapse the result and then check 583 * for exceptions. If we got any, and they are enabled, do not 584 * alter the destination register, just stop with an exception. 585 * Otherwise set new current exceptions and accrue. 586 */ 587 fpu_implode(fe, fp, type, space); 588 cx = fe->fe_cx; 589 fsr = fe->fe_fsr; 590 if (cx != 0) { 591 mask = (fsr >> FSR_TEM_SHIFT) & FSR_TEM_MASK; 592 if (cx & mask) { 593 /* not accrued??? */ 594 fs->fs_fsr = (fsr & ~FSR_FTT) | 595 (FSR_TT_IEEE << FSR_FTT_SHIFT) | 596 (cx_to_trapx[(cx & mask) - 1] << FSR_CX_SHIFT); 597 return (FPE); 598 } 599 fsr |= (cx << FSR_CX_SHIFT) | (cx << FSR_AX_SHIFT); 600 } 601 fs->fs_fsr = fsr; 602 DPRINTF(FPE_REG, ("-> %c%d\n", (type == FTYPE_LNG) ? 'x' : 603 ((type == FTYPE_INT) ? 'i' : 604 ((type == FTYPE_SNG) ? 's' : 605 ((type == FTYPE_DBL) ? 'd' : 606 ((type == FTYPE_EXT) ? 'q' : '?')))), 607 rd)); 608 fs->fs_regs[rd] = space[0]; 609 if (type >= FTYPE_DBL || type == FTYPE_LNG) { 610 fs->fs_regs[rd + 1] = space[1]; 611 if (type > FTYPE_DBL) { 612 fs->fs_regs[rd + 2] = space[2]; 613 fs->fs_regs[rd + 3] = space[3]; 614 } 615 } 616 return (0); /* success */ 617 } 618