1 /* $NetBSD: fpu_explode.c,v 1.9 2002/10/16 11:05:10 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines: `explode' the machine's `packed binary' format numbers 49 * into our internal format. 50 */ 51 52 #if defined(_KERNEL_OPT) 53 #include "opt_sparc_arch.h" 54 #endif 55 56 #include <sys/types.h> 57 #include <sys/systm.h> 58 59 #include <machine/ieee.h> 60 #include <machine/instr.h> 61 #include <machine/reg.h> 62 63 #include <sparc/fpu/fpu_arith.h> 64 #include <sparc/fpu/fpu_emu.h> 65 #include <sparc/fpu/fpu_extern.h> 66 67 /* 68 * N.B.: in all of the following, we assume the FP format is 69 * 70 * --------------------------- 71 * | s | exponent | fraction | 72 * --------------------------- 73 * 74 * (which represents -1**s * 1.fraction * 2**exponent), so that the 75 * sign bit is way at the top (bit 31), the exponent is next, and 76 * then the remaining bits mark the fraction. A zero exponent means 77 * zero or denormalized (0.fraction rather than 1.fraction), and the 78 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 79 * 80 * Since the sign bit is always the topmost bit---this holds even for 81 * integers---we set that outside all the *tof functions. Each function 82 * returns the class code for the new number (but note that we use 83 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 84 */ 85 86 /* 87 * int -> fpn. 88 */ 89 int 90 fpu_itof(fp, i) 91 register struct fpn *fp; 92 register u_int i; 93 { 94 95 if (i == 0) 96 return (FPC_ZERO); 97 /* 98 * The value FP_1 represents 2^FP_LG, so set the exponent 99 * there and let normalization fix it up. Convert negative 100 * numbers to sign-and-magnitude. Note that this relies on 101 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 102 */ 103 fp->fp_exp = FP_LG; 104 fp->fp_mant[0] = (int)i < 0 ? -i : i; 105 fp->fp_mant[1] = 0; 106 fp->fp_mant[2] = 0; 107 fp->fp_mant[3] = 0; 108 fpu_norm(fp); 109 return (FPC_NUM); 110 } 111 112 #ifdef SUN4U 113 /* 114 * 64-bit int -> fpn. 115 */ 116 int 117 fpu_xtof(fp, i) 118 register struct fpn *fp; 119 register u_int64_t i; 120 { 121 122 if (i == 0) 123 return (FPC_ZERO); 124 /* 125 * The value FP_1 represents 2^FP_LG, so set the exponent 126 * there and let normalization fix it up. Convert negative 127 * numbers to sign-and-magnitude. Note that this relies on 128 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 129 */ 130 fp->fp_exp = FP_LG2; 131 *((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i; 132 fp->fp_mant[2] = 0; 133 fp->fp_mant[3] = 0; 134 fpu_norm(fp); 135 return (FPC_NUM); 136 } 137 #endif /* SUN4U */ 138 139 #define mask(nbits) ((1L << (nbits)) - 1) 140 141 /* 142 * All external floating formats convert to internal in the same manner, 143 * as defined here. Note that only normals get an implied 1.0 inserted. 144 */ 145 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 146 if (exp == 0) { \ 147 if (allfrac == 0) \ 148 return (FPC_ZERO); \ 149 fp->fp_exp = 1 - expbias; \ 150 fp->fp_mant[0] = f0; \ 151 fp->fp_mant[1] = f1; \ 152 fp->fp_mant[2] = f2; \ 153 fp->fp_mant[3] = f3; \ 154 fpu_norm(fp); \ 155 return (FPC_NUM); \ 156 } \ 157 if (exp == (2 * expbias + 1)) { \ 158 if (allfrac == 0) \ 159 return (FPC_INF); \ 160 fp->fp_mant[0] = f0; \ 161 fp->fp_mant[1] = f1; \ 162 fp->fp_mant[2] = f2; \ 163 fp->fp_mant[3] = f3; \ 164 return (FPC_QNAN); \ 165 } \ 166 fp->fp_exp = exp - expbias; \ 167 fp->fp_mant[0] = FP_1 | f0; \ 168 fp->fp_mant[1] = f1; \ 169 fp->fp_mant[2] = f2; \ 170 fp->fp_mant[3] = f3; \ 171 return (FPC_NUM) 172 173 /* 174 * 32-bit single precision -> fpn. 175 * We assume a single occupies at most (64-FP_LG) bits in the internal 176 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 177 */ 178 int 179 fpu_stof(fp, i) 180 register struct fpn *fp; 181 register u_int i; 182 { 183 register int exp; 184 register u_int frac, f0, f1; 185 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 186 187 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 188 frac = i & mask(SNG_FRACBITS); 189 f0 = frac >> SNG_SHIFT; 190 f1 = frac << (32 - SNG_SHIFT); 191 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 192 } 193 194 /* 195 * 64-bit double -> fpn. 196 * We assume this uses at most (96-FP_LG) bits. 197 */ 198 int 199 fpu_dtof(fp, i, j) 200 register struct fpn *fp; 201 register u_int i, j; 202 { 203 register int exp; 204 register u_int frac, f0, f1, f2; 205 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 206 207 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 208 frac = i & mask(DBL_FRACBITS - 32); 209 f0 = frac >> DBL_SHIFT; 210 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 211 f2 = j << (32 - DBL_SHIFT); 212 frac |= j; 213 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 214 } 215 216 /* 217 * 128-bit extended -> fpn. 218 */ 219 int 220 fpu_qtof(fp, i, j, k, l) 221 register struct fpn *fp; 222 register u_int i, j, k, l; 223 { 224 register int exp; 225 register u_int frac, f0, f1, f2, f3; 226 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */ 227 228 /* 229 * Note that ext and fpn `line up', hence no shifting needed. 230 */ 231 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 232 frac = i & mask(EXT_FRACBITS - 3 * 32); 233 f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT)); 234 f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT)); 235 f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT)); 236 f3 = l << EXT_SHIFT; 237 frac |= j | k | l; 238 FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3); 239 } 240 241 /* 242 * Explode the contents of a register / regpair / regquad. 243 * If the input is a signalling NaN, an NV (invalid) exception 244 * will be set. (Note that nothing but NV can occur until ALU 245 * operations are performed.) 246 */ 247 void 248 fpu_explode(fe, fp, type, reg) 249 register struct fpemu *fe; 250 register struct fpn *fp; 251 int type, reg; 252 { 253 register u_int s, *space; 254 #ifdef SUN4U 255 u_int64_t l, *xspace; 256 257 xspace = (u_int64_t *)&fe->fe_fpstate->fs_regs[reg & ~1]; 258 l = xspace[0]; 259 #endif /* SUN4U */ 260 space = &fe->fe_fpstate->fs_regs[reg]; 261 s = space[0]; 262 fp->fp_sign = s >> 31; 263 fp->fp_sticky = 0; 264 switch (type) { 265 #ifdef SUN4U 266 case FTYPE_LNG: 267 s = fpu_xtof(fp, l); 268 break; 269 #endif /* SUN4U */ 270 271 case FTYPE_INT: 272 s = fpu_itof(fp, s); 273 break; 274 275 case FTYPE_SNG: 276 s = fpu_stof(fp, s); 277 break; 278 279 case FTYPE_DBL: 280 s = fpu_dtof(fp, s, space[1]); 281 break; 282 283 case FTYPE_EXT: 284 s = fpu_qtof(fp, s, space[1], space[2], space[3]); 285 break; 286 287 default: 288 panic("fpu_explode"); 289 } 290 291 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 292 /* 293 * Input is a signalling NaN. All operations that return 294 * an input NaN operand put it through a ``NaN conversion'', 295 * which basically just means ``turn on the quiet bit''. 296 * We do this here so that all NaNs internally look quiet 297 * (we can tell signalling ones by their class). 298 */ 299 fp->fp_mant[0] |= FP_QUIETBIT; 300 fe->fe_cx = FSR_NV; /* assert invalid operand */ 301 s = FPC_SNAN; 302 } 303 fp->fp_class = s; 304 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' : 305 ((type == FTYPE_INT) ? 'i' : 306 ((type == FTYPE_SNG) ? 's' : 307 ((type == FTYPE_DBL) ? 'd' : 308 ((type == FTYPE_EXT) ? 'q' : '?')))), 309 reg)); 310 #ifdef DEBUG 311 if (fpe_debug & FPE_REG) { 312 if (type == FTYPE_INT) printf("%d ", s); 313 #ifdef SUN4U 314 #ifdef _LP64 315 if (type == FTYPE_LNG) printf("%ld ", l); 316 #else 317 if (type == FTYPE_LNG) printf("%lld ", l); 318 #endif 319 #endif /* SUN4U */ 320 } 321 #endif /* DEBUG */ 322 DUMPFPN(FPE_REG, fp); 323 DPRINTF(FPE_REG, ("\n")); 324 } 325