1 /* $NetBSD: cpu.h,v 1.49 2002/02/03 14:10:02 darrenr Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 45 */ 46 47 #ifndef _CPU_H_ 48 #define _CPU_H_ 49 50 /* 51 * CTL_MACHDEP definitions. 52 */ 53 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 54 #define CPU_BOOTED_DEVICE 2 /* string: device booted from */ 55 #define CPU_BOOT_ARGS 3 /* string: args booted with */ 56 #define CPU_MAXID 4 /* number of valid machdep ids */ 57 58 #define CTL_MACHDEP_NAMES { \ 59 { 0, 0 }, \ 60 { "booted_kernel", CTLTYPE_STRING }, \ 61 { "booted_device", CTLTYPE_STRING }, \ 62 { "boot_args", CTLTYPE_STRING }, \ 63 } 64 65 #ifdef _KERNEL 66 /* 67 * Exported definitions unique to SPARC cpu support. 68 */ 69 70 #if !defined(_LKM) && defined(_KERNEL_OPT) 71 #include "opt_multiprocessor.h" 72 #include "opt_lockdebug.h" 73 #include "opt_sparc_arch.h" 74 #endif 75 76 #include <machine/psl.h> 77 #include <machine/intr.h> 78 #include <sparc/sparc/cpuvar.h> 79 #include <sparc/sparc/intreg.h> 80 81 /* 82 * definitions of cpu-dependent requirements 83 * referenced in generic code 84 */ 85 #define curcpu() (cpuinfo.ci_self) 86 #define curproc (curcpu()->ci_curproc) 87 #define CPU_IS_PRIMARY(ci) ((ci)->master) 88 89 #define cpu_swapin(p) /* nothing */ 90 #define cpu_swapout(p) /* nothing */ 91 #define cpu_wait(p) /* nothing */ 92 #define cpu_number() (cpuinfo.ci_cpuid) 93 94 #if defined(MULTIPROCESSOR) 95 void cpu_boot_secondary_processors __P((void)); 96 #endif 97 98 /* 99 * Arguments to hardclock, softclock and gatherstats encapsulate the 100 * previous machine state in an opaque clockframe. The ipl is here 101 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 102 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 103 */ 104 struct clockframe { 105 u_int psr; /* psr before interrupt, excluding PSR_ET */ 106 u_int pc; /* pc at interrupt */ 107 u_int npc; /* npc at interrupt */ 108 u_int ipl; /* actual interrupt priority level */ 109 u_int fp; /* %fp at interrupt */ 110 }; 111 typedef struct clockframe clockframe; 112 113 extern int eintstack[]; 114 115 #define CLKF_USERMODE(framep) (((framep)->psr & PSR_PS) == 0) 116 #define CLKF_BASEPRI(framep) (((framep)->psr & PSR_PIL) == 0) 117 #define CLKF_PC(framep) ((framep)->pc) 118 #if defined(MULTIPROCESSOR) 119 #define CLKF_INTR(framep) \ 120 ((framep)->fp > (u_int)cpuinfo.eintstack - INT_STACK_SIZE && \ 121 (framep)->fp < (u_int)cpuinfo.eintstack) 122 #else 123 #define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack) 124 #endif 125 126 #if defined(SUN4M) 127 extern void raise __P((int, int)); 128 #if !(defined(SUN4) || defined(SUN4C)) 129 #define setsoftint() raise(0,1) 130 #else /* both defined */ 131 #define setsoftint() (cputyp == CPU_SUN4M ? raise(0,1) : ienab_bis(IE_L1)) 132 #endif /* !4,!4c */ 133 #else /* 4m not defined */ 134 #define setsoftint() ienab_bis(IE_L1) 135 #endif /* SUN4M */ 136 137 void softintr_init __P((void)); 138 void *softnet_cookie; 139 140 #define setsoftnet() softintr_schedule(softnet_cookie); 141 142 extern int want_ast; 143 144 /* 145 * Preempt the current process if in interrupt from user mode, 146 * or after the current trap/syscall if in system mode. 147 */ 148 extern int want_resched; /* resched() was called */ 149 #define need_resched(ci) (want_resched = 1, want_ast = 1) 150 151 /* 152 * Give a profiling tick to the current process when the user profiling 153 * buffer pages are invalid. On the sparc, request an ast to send us 154 * through trap(), marking the proc as needing a profiling tick. 155 */ 156 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1) 157 158 /* 159 * Notify the current process (p) that it has a signal pending, 160 * process as soon as possible. 161 */ 162 #define signotify(p) (want_ast = 1) 163 164 /* Number of CPUs in the system */ 165 extern int ncpu; 166 167 /* 168 * Only one process may own the FPU state. 169 * 170 * XXX this must be per-cpu (eventually) 171 */ 172 extern struct proc *fpproc; /* FPU owner */ 173 extern int foundfpu; /* true => we have an FPU */ 174 175 /* 176 * Interrupt handler chains. Interrupt handlers should return 0 for 177 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 178 * handler into the list. The handler is called with its (single) 179 * argument, or with a pointer to a clockframe if ih_arg is NULL. 180 */ 181 extern struct intrhand { 182 int (*ih_fun) __P((void *)); 183 void *ih_arg; 184 struct intrhand *ih_next; 185 } *intrhand[15]; 186 187 void intr_establish __P((int level, struct intrhand *)); 188 void intr_disestablish __P((int level, struct intrhand *)); 189 190 /* 191 * intr_fasttrap() is a lot like intr_establish, but is used for ``fast'' 192 * interrupt vectors (vectors that are not shared and are handled in the 193 * trap window). Such functions must be written in assembly. 194 */ 195 void intr_fasttrap __P((int level, void (*vec)(void))); 196 197 void intr_lock_kernel __P((void)); 198 void intr_unlock_kernel __P((void)); 199 200 /* disksubr.c */ 201 struct dkbad; 202 int isbad __P((struct dkbad *bt, int, int, int)); 203 /* machdep.c */ 204 int ldcontrolb __P((caddr_t)); 205 void dumpconf __P((void)); 206 caddr_t reserve_dumppages __P((caddr_t)); 207 /* clock.c */ 208 struct timeval; 209 void lo_microtime __P((struct timeval *)); 210 int clockintr __P((void *));/* level 10 (clock) interrupt code */ 211 int statintr __P((void *)); /* level 14 (statclock) interrupt code */ 212 /* locore.s */ 213 struct fpstate; 214 void savefpstate __P((struct fpstate *)); 215 void loadfpstate __P((struct fpstate *)); 216 int probeget __P((caddr_t, int)); 217 void write_all_windows __P((void)); 218 void write_user_windows __P((void)); 219 void proc_trampoline __P((void)); 220 void switchexit __P((struct proc *)); 221 struct pcb; 222 void snapshot __P((struct pcb *)); 223 struct frame *getfp __P((void)); 224 int xldcontrolb __P((caddr_t, struct pcb *)); 225 void copywords __P((const void *, void *, size_t)); 226 void qcopy __P((const void *, void *, size_t)); 227 void qzero __P((void *, size_t)); 228 /* trap.c */ 229 void kill_user_windows __P((struct proc *)); 230 int rwindow_save __P((struct proc *)); 231 /* amd7930intr.s */ 232 void amd7930_trap __P((void)); 233 /* cons.c */ 234 int cnrom __P((void)); 235 /* zs.c */ 236 void zsconsole __P((struct tty *, int, int, void (**)(struct tty *, int))); 237 #ifdef KGDB 238 void zs_kgdb_init __P((void)); 239 #endif 240 /* fb.c */ 241 void fb_unblank __P((void)); 242 /* cache.c */ 243 void cache_flush __P((caddr_t, u_int)); 244 /* kgdb_stub.c */ 245 #ifdef KGDB 246 void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *)); 247 void kgdb_connect __P((int)); 248 void kgdb_panic __P((void)); 249 #endif 250 /* emul.c */ 251 struct trapframe; 252 int fixalign __P((struct proc *, struct trapframe *)); 253 int emulinstr __P((int, struct trapframe *)); 254 /* cpu.c */ 255 void mp_pause_cpus __P((void)); 256 void mp_resume_cpus __P((void)); 257 void mp_halt_cpus __P((void)); 258 /* msiiep.c */ 259 void msiiep_swap_endian __P((int)); 260 261 /* 262 * 263 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 264 * of the trap vector table. The next eight bits are supplied by the 265 * hardware when the trap occurs, and the bottom four bits are always 266 * zero (so that we can shove up to 16 bytes of executable code---exactly 267 * four instructions---into each trap vector). 268 * 269 * The hardware allocates half the trap vectors to hardware and half to 270 * software. 271 * 272 * Traps have priorities assigned (lower number => higher priority). 273 */ 274 275 struct trapvec { 276 int tv_instr[4]; /* the four instructions */ 277 }; 278 extern struct trapvec *trapbase; /* the 256 vectors */ 279 280 extern void wzero __P((void *, u_int)); 281 extern void wcopy __P((const void *, void *, u_int)); 282 283 #endif /* _KERNEL */ 284 #endif /* _CPU_H_ */ 285