1 /* $NetBSD: ctlreg.h,v 1.23 2002/08/24 17:27:21 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Harvard University. 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgement: 29 * This product includes software developed by the University of 30 * California, Berkeley and its contributors. 31 * 4. Neither the name of the University nor the names of its contributors 32 * may be used to endorse or promote products derived from this software 33 * without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 45 * SUCH DAMAGE. 46 * 47 * @(#)ctlreg.h 8.1 (Berkeley) 6/11/93 48 */ 49 50 /* 51 * Sun4m support by Aaron Brown, Harvard University. 52 * Changes Copyright (c) 1995 The President and Fellows of Harvard College. 53 * All rights reserved. 54 */ 55 56 /* 57 * Sun 4, 4c, and 4m control registers. (includes address space definitions 58 * and some registers in control space). 59 */ 60 61 /* 62 * The Alternate address spaces. 63 */ 64 65 /* 0x00 unused */ 66 /* 0x01 unused */ 67 #define ASI_CONTROL 0x02 /* cache enable, context reg, etc */ 68 #define ASI_SEGMAP 0x03 /* [4/4c] segment maps */ 69 #define ASI_SRMMUFP 0x03 /* [4m] ref mmu flush/probe */ 70 #define ASI_PTE 0x04 /* [4/4c] PTE space (pmegs) */ 71 #define ASI_SRMMU 0x04 /* [4m] ref mmu registers */ 72 #define ASI_REGMAP 0x06 /* [4/3-level MMU ] region maps */ 73 #define ASI_HWFLUSHSEG 0x05 /* [4/4c] hardware assisted version of FLUSHSEG */ 74 #define ASI_HWFLUSHPG 0x06 /* [4/4c] hardware assisted version of FLUSHPG */ 75 #define ASI_SRMMUDIAG 0x06 /* [4m] */ 76 #define ASI_HWFLUSHCTX 0x07 /* [4/4c] hardware assisted version of FLUSHCTX */ 77 78 #define ASI_USERI 0x08 /* I-space (user) */ 79 #define ASI_KERNELI 0x09 /* I-space (kernel) */ 80 #define ASI_USERD 0x0a /* D-space (user) */ 81 #define ASI_KERNELD 0x0b /* D-space (kernel) */ 82 83 #define ASI_FLUSHREG 0x7 /* [4/4c] flush cache by region */ 84 #define ASI_FLUSHSEG 0x0c /* [4/4c] flush cache by segment */ 85 #define ASI_FLUSHPG 0x0d /* [4/4c] flush cache by page */ 86 #define ASI_FLUSHCTX 0x0e /* [4/4c] flush cache by context */ 87 88 #define ASI_DCACHE 0x0f /* [4] flush data cache */ 89 90 #define ASI_ICACHETAG 0x0c /* [4m] instruction cache tag */ 91 #define ASI_ICACHEDATA 0x0d /* [4m] instruction cache data */ 92 #define ASI_DCACHETAG 0x0e /* [4m] data cache tag */ 93 #define ASI_DCACHEDATA 0x0f /* [4m] data cache data */ 94 #define ASI_IDCACHELFP 0x10 /* [4m] flush i&d cache line (page) */ 95 #define ASI_IDCACHELFS 0x11 /* [4m] flush i&d cache line (seg) */ 96 #define ASI_IDCACHELFR 0x12 /* [4m] flush i&d cache line (reg) */ 97 #define ASI_IDCACHELFC 0x13 /* [4m] flush i&d cache line (ctxt) */ 98 #define ASI_IDCACHELFU 0x14 /* [4m] flush i&d cache line (user) */ 99 #define ASI_BLOCKCOPY 0x17 /* [4m] hypersparc: hardware block copy */ 100 #define ASI_BLOCKFILL 0x1f /* [4m] hypersparc: hardware block fill */ 101 #define ASI_BYPASS 0x20 /* [4m] sun ref mmu bypass, 102 ie. direct phys access */ 103 #define ASI_CSR 0x2f /* [4d] cpu-unit CSR space */ 104 #define ASI_ECSR 0x2f /* [4d] cpu-unit ECSR space */ 105 #define ASI_HICACHECLR 0x31 /* [4m] hypersparc only: I-cache flash clear */ 106 #define ASI_ICACHECLR 0x36 /* [4m] ms1 only: I-cache flash clear */ 107 #define ASI_DCACHECLR 0x37 /* [4m] ms1 only: D-cache flash clear */ 108 #define ASI_DCACHEDIAG 0x39 /* [4m] data cache diagnostic register access */ 109 110 /* 111 * [4/4c] Registers in the control space (ASI_CONTROL). 112 */ 113 #define AC_IDPROM 0x00000000 /* [4] ID PROM */ 114 #define AC_CONTEXT 0x30000000 /* [4/4c] context register (byte) */ 115 #define AC_SYSENABLE 0x40000000 /* [4/4c] system enable register (byte) */ 116 #define AC_DVMA_ENABLE 0x50000000 /* [4] enable user dvma */ 117 #define AC_BUS_ERR 0x60000000 /* [4] bus error register */ 118 #define AC_SYNC_ERR 0x60000000 /* [4c] sync (memory) error reg */ 119 #define AC_SYNC_VA 0x60000004 /* [4c] sync error virtual addr */ 120 #define AC_ASYNC_ERR 0x60000008 /* [4c] async error reg */ 121 #define AC_ASYNC_VA 0x6000000c /* [4c] async error virtual addr */ 122 #define AC_DIAG_REG 0x70000000 /* [4] diagnostic reg */ 123 #define AC_CACHETAGS 0x80000000 /* [4/4c?] cache tag base address */ 124 #define AC_CACHEDATA 0x90000000 /* [4] cached data [sun4/400?] */ 125 #define AC_DVMA_MAP 0xd0000000 /* [4] user dvma map entries */ 126 #define AC_VMEINTVEC 0xe0000000 /* [4] vme interrupt vector */ 127 #define AC_SERIAL 0xf0000000 /* [4/4c] special serial port sneakiness */ 128 /* AC_SERIAL is not used in the kernel (it is for the PROM) */ 129 130 /* XXX: does not belong here */ 131 #define ME_REG_IERR 0x80 /* memory err ctrl reg error intr pending bit */ 132 133 /* 134 * [4/4c] 135 * Bits in sync error register. Reading the register clears these; 136 * otherwise they accumulate. The error(s) occurred at the virtual 137 * address stored in the sync error address register, and may have 138 * been due to, e.g., what would usually be called a page fault. 139 * Worse, the bits accumulate during instruction prefetch, so 140 * various bits can be on that should be off. 141 */ 142 #define SER_WRITE 0x8000 /* error occurred during write */ 143 #define SER_INVAL 0x80 /* PTE had PG_V off */ 144 #define SER_PROT 0x40 /* operation violated PTE prot */ 145 #define SER_TIMEOUT 0x20 /* bus timeout (non-existent mem) */ 146 #define SER_SBUSERR 0x10 /* S-Bus bus error */ 147 #define SER_MEMERR 0x08 /* memory ecc/parity error */ 148 #define SER_SZERR 0x02 /* [4/vme?] size error, whatever that is */ 149 #define SER_WATCHDOG 0x01 /* watchdog reset (never see this) */ 150 151 #define SER_BITS \ 152 "\20\20WRITE\10INVAL\7PROT\6TIMEOUT\5SBUSERR\4MEMERR\2SZERR\1WATCHDOG" 153 154 /* 155 * [4/4c] 156 * Bits in async error register (errors from DVMA or Sun-4 cache 157 * writeback). The corresponding bit is also set in the sync error reg. 158 * 159 * A writeback invalid error means there is a bug in the PTE manager. 160 * 161 * The word is that the async error register does not work right. 162 */ 163 #define AER_WBINVAL 0x80 /* writeback found PTE without PG_V */ 164 #define AER_TIMEOUT 0x20 /* bus timeout */ 165 #define AER_DVMAERR 0x10 /* bus error during DVMA */ 166 167 #define AER_BITS "\20\10WBINVAL\6TIMEOUT\5DVMAERR" 168 169 /* 170 * [4/4c] Bits in system enable register. 171 */ 172 #define SYSEN_DVMA 0x20 /* Enable dvma */ 173 #define SYSEN_CACHE 0x10 /* Enable cache */ 174 #define SYSEN_IOCACHE 0x40 /* Enable IO cache */ 175 #define SYSEN_VIDEO 0x08 /* Enable on-board video */ 176 #define SYSEN_RESET 0x04 /* Reset the hardware */ 177 #define SYSEN_RESETVME 0x02 /* Reset the VME bus */ 178 179 180 /* 181 * [4m] Bits in ASI_CONTROL space, sun4m only. 182 */ 183 #define MXCC_STREAM_DATA 0x1c00000 /* Stream data register */ 184 #define MXCC_STREAM_SRC 0x1c00100 /* Stream source register */ 185 #define MXCC_STREAM_DST 0x1c00200 /* Stream dest register */ 186 #define MXCC_CTRLREG 0x1c00a00 /* Control register for MXCC */ 187 188 /* Bits in MXCC_CTRLREG */ 189 #define MXCC_CTRLREG_HC 0x1 /* Half cache (Xbus only) */ 190 #define MXCC_CTRLREG_CS 0x2 /* E-cache size (Xbus only) */ 191 #define MXCC_CTRLREG_CE 0x4 /* Enable e-cache */ 192 #define MXCC_CTRLREG_PE 0x8 /* Parity enable */ 193 #define MXCC_CTRLREG_MC 0x10 /* Multiple command enable */ 194 #define MXCC_CTRLREG_PF 0x20 /* Prefetch enable */ 195 #define MXCC_CTRLREG_WI 0x40 /* Write invalidate (Xbus only) */ 196 #define MXCC_CTRLREG_BWC_MASK 0x180 /* Bus watch count (Xbus only) */ 197 #define MXCC_CTRLREG_RC 0x200 /* Read reference count */ 198 199 /* 200 * Stream register usage: 201 * To fill a block with some value, load that value into the 64 byte 202 * stream data register (using double-word access; on Mbus only the 203 * lower 32 bytes are used), then write the physical address of 204 * the destination into the stream destination register. 205 * 206 * To copy a block, write the physical address of the source into 207 * the stream source register causing the block to be transferred 208 * into the stream data register, then write the physical address of 209 * the destination into the stream destination register. 210 * 211 * In both cases, or in the MXCC_STREAM_CE bit to make the transactions 212 * cache-coherent. Note that stream operations do not cause cache 213 * lines to be allocated. 214 */ 215 #define MXCC_STREAM_BLKSZ 32 /* Unit for stream ops */ 216 #define MXCC_STREAM_C 0x1000000000ULL /* Cacheable bit for stream ops */ 217 218 /* 219 * Bits in ASI_SRMMUFP space. 220 * Bits 8-11 determine the type of flush/probe. 221 * Address bits 12-31 hold the page frame. 222 */ 223 #define ASI_SRMMUFP_L3 (0<<8) /* probe L3 | flush L3 PTE */ 224 #define ASI_SRMMUFP_L2 (1<<8) /* probe L2 | flush L2/L3 PTE/PTD's */ 225 #define ASI_SRMMUFP_L1 (2<<8) /* probe L1 | flush L1/L2/L3 PTE/PTD's*/ 226 #define ASI_SRMMUFP_L0 (3<<8) /* probe L0 | flush L0/L1/L2/L3 PTE/PTD's */ 227 #define ASI_SRMMUFP_LN (4<<8) /* probe all | flush all levels */ 228 229 /* 230 * [4m] Registers and bits in the SPARC Reference MMU (ASI_SRMMU). 231 */ 232 #define SRMMU_PCR 0x00000000 /* Processor control register */ 233 #define SRMMU_CXTPTR 0x00000100 /* Context table pointer register */ 234 #define SRMMU_CXR 0x00000200 /* Context register */ 235 #define SRMMU_SFSR 0x00000300 /* Synchronous fault status reg */ 236 #define SRMMU_SFAR 0x00000400 /* Synchronous fault address reg */ 237 #define SRMMU_AFSR 0x00000500 /* Asynchronous fault status reg (HS) */ 238 #define SRMMU_AFAR 0x00000600 /* Asynchronous fault address reg (HS)*/ 239 #define SRMMU_PCFG 0x00000600 /* Processor configuration reg (TURBO)*/ 240 #define SRMMU_TLBCTRL 0x00001000 /* TLB replacement control reg */ 241 242 243 /* 244 * [4m] Bits in SRMMU control register. One set per module. 245 */ 246 #define VIKING_PCR_ME 0x00000001 /* MMU Enable */ 247 #define VIKING_PCR_NF 0x00000002 /* Fault inhibit bit */ 248 #define VIKING_PCR_PSO 0x00000080 /* Partial Store Ordering enable */ 249 #define VIKING_PCR_DCE 0x00000100 /* Data cache enable bit */ 250 #define VIKING_PCR_ICE 0x00000200 /* SuperSPARC instr. cache enable */ 251 #define VIKING_PCR_SB 0x00000400 /* Store buffer enable bit */ 252 #define VIKING_PCR_MB 0x00000800 /* MBus mode: 0=MXCC, 1=no MXCC */ 253 #define VIKING_PCR_PE 0x00001000 /* Enable memory parity checking */ 254 #define VIKING_PCR_BM 0x00002000 /* 1 iff booting */ 255 #define VIKING_PCR_SE 0x00004000 /* Coherent bus snoop enable */ 256 #define VIKING_PCR_AC 0x00008000 /* 1=cache non-MMU accesses */ 257 #define VIKING_PCR_TC 0x00010000 /* 1=cache table walks */ 258 259 #define HYPERSPARC_PCR_ME 0x00000001 /* MMU Enable */ 260 #define HYPERSPARC_PCR_NF 0x00000002 /* Fault inhibit bit */ 261 #define HYPERSPARC_PCR_CE 0x00000100 /* Cache enable bit */ 262 #define HYPERSPARC_PCR_CM 0x00000400 /* Cache mode: 1=write-back */ 263 #define HYPERSPARC_PCR_MR 0x00000800 /* Memory reflection: 1 = on */ 264 #define HYPERSPARC_PCR_CS 0x00001000 /* cache size: 1=256k, 0=128k */ 265 #define HYPERSPARC_PCR_C 0x00002000 /* enable cache when MMU off */ 266 #define HYPERSPARC_PCR_BM 0x00004000 /* 1 iff booting */ 267 #define HYPERSPARC_PCR_MID 0x00078000 /* MBus module ID MID<3:0> */ 268 #define HYPERSPARC_PCR_WBE 0x00080000 /* Write buffer enable */ 269 #define HYPERSPARC_PCR_SE 0x00100000 /* Coherent bus snoop enable */ 270 #define HYPERSPARC_PCR_CWR 0x00200000 /* Cache wrap enable */ 271 272 #define CYPRESS_PCR_ME 0x00000001 /* MMU Enable */ 273 #define CYPRESS_PCR_NF 0x00000002 /* Fault inhibit bit */ 274 #define CYPRESS_PCR_CE 0x00000100 /* Cache enable bit */ 275 #define CYPRESS_PCR_CL 0x00000200 /* Cache Lock (604 only) */ 276 #define CYPRESS_PCR_CM 0x00000400 /* Cache mode: 1=write-back */ 277 #define CYPRESS_PCR_MR 0x00000800 /* Memory reflection: 1=on (605 only) */ 278 #define CYPRESS_PCR_C 0x00002000 /* enable cache when MMU off */ 279 #define CYPRESS_PCR_BM 0x00004000 /* 1 iff booting */ 280 #define CYPRESS_PCR_MID 0x00078000 /* MBus module ID MID<3:0> (605 only) */ 281 #define CYPRESS_PCR_MV 0x00080000 /* Multichip Valid */ 282 #define CYPRESS_PCR_MCM 0x00300000 /* Multichip Mask */ 283 #define CYPRESS_PCR_MCA 0x00c00000 /* Multichip Address */ 284 285 #define MS1_PCR_ME 0x00000001 /* MMU Enable */ 286 #define MS1_PCR_NF 0x00000002 /* Fault inhibit bit */ 287 #define MS1_PCR_DCE 0x00000100 /* Data cache enable */ 288 #define MS1_PCR_ICE 0x00000200 /* Instruction cache enable */ 289 #define MS1_PCR_RC 0x00000c00 /* DRAM Refresh control */ 290 #define MS1_PCR_PE 0x00001000 /* Enable memory parity checking */ 291 #define MS1_PCR_BM 0x00004000 /* 1 iff booting */ 292 #define MS1_PCR_AC 0x00008000 /* 1=cache if ME==0 (and [ID]CE on) */ 293 #define MS1_PCR_ID 0x00010000 /* 1=disable ITBR */ 294 #define MS1_PCR_PC 0x00020000 /* Parity control: 0=even,1=odd */ 295 #define MS1_PCR_MV 0x00100000 /* Memory data View (diag) */ 296 #define MS1_PCR_DV 0x00200000 /* Data View (diag) */ 297 #define MS1_PCR_AV 0x00400000 /* Address View (diag) */ 298 #define MS1_PCR_STW 0x00800000 /* Software Tablewalk enable */ 299 300 #define SWIFT_PCR_ME 0x00000001 /* MMU Enable */ 301 #define SWIFT_PCR_NF 0x00000002 /* Fault inhibit bit */ 302 #define SWIFT_PCR_DCE 0x00000100 /* Data cache enable */ 303 #define SWIFT_PCR_ICE 0x00000200 /* Instruction cache enable */ 304 #define SWIFT_PCR_RC 0x00003c00 /* DRAM Refresh control */ 305 #define SWIFT_PCR_BM 0x00004000 /* 1 iff booting */ 306 #define SWIFT_PCR_AC 0x00008000 /* 1=cache if ME=0 (and [ID]CE on) */ 307 #define SWIFT_PCR_PA 0x00010000 /* TCX/SX control */ 308 #define SWIFT_PCR_PC 0x00020000 /* Parity control: 0=even,1=odd */ 309 #define SWIFT_PCR_PE 0x00040000 /* Enable memory parity checking */ 310 #define SWIFT_PCR_PMC 0x00180000 /* Page mode control */ 311 #define SWIFT_PCR_BF 0x00200000 /* Branch Folding */ 312 #define SWIFT_PCR_WP 0x00400000 /* Watch point enable */ 313 #define SWIFT_PCR_STW 0x00800000 /* Software Tablewalk enable */ 314 315 #define TURBOSPARC_PCR_ME 0x00000001 /* MMU Enable */ 316 #define TURBOSPARC_PCR_NF 0x00000002 /* Fault inhibit bit */ 317 #define TURBOSPARC_PCR_ICS 0x00000004 /* I-cache snoop enable */ 318 #define TURBOSPARC_PCR_PSO 0x00000008 /* Partial Store order (ro!) */ 319 #define TURBOSPARC_PCR_DCE 0x00000100 /* Data cache enable */ 320 #define TURBOSPARC_PCR_ICE 0x00000200 /* Instruction cache enable */ 321 #define TURBOSPARC_PCR_RC 0x00003c00 /* DRAM Refresh control */ 322 #define TURBOSPARC_PCR_BM 0x00004000 /* 1 iff booting */ 323 #define TURBOSPARC_PCR_PC 0x00020000 /* Parity ctrl: 0=even,1=odd */ 324 #define TURBOSPARC_PCR_PE 0x00040000 /* Enable parity checking */ 325 #define TURBOSPARC_PCR_PMC 0x00180000 /* Page mode control */ 326 327 /* The Turbosparc's Processor Configuration Register */ 328 #define TURBOSPARC_PCFG_SCC 0x00000007 /* e-cache config */ 329 #define TURBOSPARC_PCFG_SE 0x00000008 /* e-cache enable */ 330 #define TURBOSPARC_PCFG_US2 0x00000010 /* microsparc II compat */ 331 #define TURBOSPARC_PCFG_WT 0x00000020 /* write-through enable */ 332 #define TURBOSPARC_PCFG_SBC 0x000000c0 /* SBus Clock */ 333 #define TURBOSPARC_PCFG_WS 0x03800000 /* DRAM wait states */ 334 #define TURBOSPARC_PCFG_RAH 0x0c000000 /* DRAM Row Address Hold */ 335 #define TURBOSPARC_PCFG_AXC 0x30000000 /* AFX Clock */ 336 #define TURBOSPARC_PCFG_SNP 0x40000000 /* DVMA Snoop enable */ 337 #define TURBOSPARC_PCFG_IOCLK 0x80000000 /* I/O clock ratio */ 338 339 340 /* Implementation and Version fields are common to all modules */ 341 #define SRMMU_PCR_VER 0x0f000000 /* Version of MMU implementation */ 342 #define SRMMU_PCR_IMPL 0xf0000000 /* Implementation number of MMU */ 343 344 345 /* [4m] Bits in the Synchronous Fault Status Register */ 346 #define SFSR_EM 0x00020000 /* Error mode watchdog reset occurred */ 347 #define SFSR_CS 0x00010000 /* Control Space error */ 348 #define SFSR_SB 0x00008000 /* SS: Store Buffer Error */ 349 #define SFSR_PERR 0x00006000 /* Parity error code */ 350 #define SFSR_P 0x00004000 /* SS: Parity error */ 351 #define SFSR_UC 0x00001000 /* Uncorrectable error */ 352 #define SFSR_TO 0x00000800 /* S-Bus timeout */ 353 #define SFSR_BE 0x00000400 /* S-Bus bus error */ 354 #define SFSR_LVL 0x00000300 /* Pagetable level causing the fault */ 355 #define SFSR_AT 0x000000e0 /* Access type */ 356 #define SFSR_FT 0x0000001c /* Fault type */ 357 #define SFSR_FAV 0x00000002 /* Fault Address is valid */ 358 #define SFSR_OW 0x00000001 /* Overwritten with new fault */ 359 360 #define SFSR_BITS "\177\020" \ 361 "b\21EM\0b\20CS\0b\17SB\0f\15\2PERR\0" \ 362 "b\14UC\0b\13TO\0b\12BE\0f\10\2LVL\0" \ 363 "f\05\3AT\0f\02\3FT\0b\01FAV\0b\01OW" 364 365 /* [4m] Synchronous Fault Types */ 366 #define SFSR_FT_NONE (0 << 2) /* no fault */ 367 #define SFSR_FT_INVADDR (1 << 2) /* invalid address fault */ 368 #define SFSR_FT_PROTERR (2 << 2) /* protection fault */ 369 #define SFSR_FT_PRIVERR (3 << 2) /* privelege violation */ 370 #define SFSR_FT_TRANSERR (4 << 2) /* translation fault */ 371 #define SFSR_FT_BUSERR (5 << 2) /* access bus error */ 372 #define SFSR_FT_INTERR (6 << 2) /* internal error */ 373 #define SFSR_FT_RESERVED (7 << 2) /* reserved */ 374 375 /* [4m] Synchronous Fault Access Types */ 376 #define SFSR_AT_LDUDATA (0 << 5) /* Load user data */ 377 #define SFSR_AT_LDSDATA (1 << 5) /* Load supervisor data */ 378 #define SFSR_AT_LDUTEXT (2 << 5) /* Load user text */ 379 #define SFSR_AT_LDSTEXT (3 << 5) /* Load supervisor text */ 380 #define SFSR_AT_STUDATA (4 << 5) /* Store user data */ 381 #define SFSR_AT_STSDATA (5 << 5) /* Store supervisor data */ 382 #define SFSR_AT_STUTEXT (6 << 5) /* Store user text */ 383 #define SFSR_AT_STSTEXT (7 << 5) /* Store supervisor text */ 384 #define SFSR_AT_SUPERVISOR (1 << 5) /* Set iff supervisor */ 385 #define SFSR_AT_TEXT (2 << 5) /* Set iff text */ 386 #define SFSR_AT_STORE (4 << 5) /* Set iff store */ 387 388 /* [4m] Synchronous Fault PT Levels */ 389 #define SFSR_LVL_0 (0 << 8) /* Context table entry */ 390 #define SFSR_LVL_1 (1 << 8) /* Region table entry */ 391 #define SFSR_LVL_2 (2 << 8) /* Segment table entry */ 392 #define SFSR_LVL_3 (3 << 8) /* Page table entry */ 393 394 /* [4m] Asynchronous Fault Status Register bits */ 395 #define AFSR_AFO 0x00000001 /* Async. fault occurred */ 396 #define AFSR_AFA 0x000000f0 /* Bits <35:32> of faulting phys addr */ 397 #define AFSR_AFA_RSHIFT 4 /* Shift to get AFA to bit 0 */ 398 #define AFSR_AFA_LSHIFT 28 /* Shift to get AFA to bit 32 */ 399 #define AFSR_BE 0x00000400 /* Bus error */ 400 #define AFSR_TO 0x00000800 /* Bus timeout */ 401 #define AFSR_UC 0x00001000 /* Uncorrectable error */ 402 #define AFSR_SE 0x00002000 /* System error */ 403 404 #define AFSR_BITS "\177\020" \ 405 "b\15SE\0b\14UC\0b\13TO\0b\12BE\0f\04\4AFA\0b\0AFO\0" 406 407 /* [4m] TLB Replacement Control Register bits */ 408 #define TLBC_DISABLE 0x00000020 /* Disable replacement counter */ 409 #define TLBC_RCNTMASK 0x0000001f /* Replacement counter (0-31) */ 410 411 412 /* 413 * The Ross Hypersparc has an Instruction Cache Control Register (ICCR) 414 * It contains an enable bit for the on-chip instruction cache and a bit 415 * that controls whether a FLUSH instruction causes an Unimplemented 416 * Flush Trap or just flushes the appropriate instruction cache line. 417 * The ICCR register is implemented as Ancillary State register number 31. 418 */ 419 #define HYPERSPARC_ICCR_ICE 1 /* Instruction cache enable */ 420 #define HYPERSPARC_ICCR_FTD 2 /* Unimpl. flush trap disable */ 421 #define HYPERSPARC_ASRNUM_ICCR 31 /* ICCR == ASR#31 */ 422